DDmJmOSTRANSPUTERDATABOOKThird edition 1992i.,L ~ ~ ~ ; ~ ~ 1 1 ' : ~ ? ~ ~INMOS is a member of the SGS-THOMSON Microelectronics GroupINMOS Databook SeriesTransputer DatabookMilitary and Space Transputer DatabookTransputer Development and iq Systems DatabookTransputer Applications Notebook: Architecture and SoftwareTransputer Applications Notebook: Systems and PerformanceT9000 Transputer Products Overview ManualGraphics DatabookCopyright INMOS Limited 1992INMOS reserves the right to make changes in specifications at any time and without notice.The information furnished by INMOS in this publication is believed to be accurate; however,no responsibility is assumed for its use, nor for any infringement of patents or other rightsof third parties resulting from its use. No licence is granted under any patents, trademarksor other rights of INMOS.e,OmnlOS, IMS and occam are trademarks of INMOS Limited.INMOS Limited is a member of the SGS-THOMSON Microelectronics Group.INMOS document number: 72 TRN 203 02ORDER CODE: DBTRANST/3PRINTED IN ITALYI Contents overviewContents .Notation and nomenclature xviilransputer product numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. xviii1 Company overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 lransputer architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 lransputer overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 lransputer instruction set summary 455 lransputer performance 596 IMS 1805 transputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 IMS 1801 transputer 1278 IMS 1426 transputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1639 IMS 1425 transputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 21910 IMS 1400 transputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 27111 IMS 1225 transputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 32312 IMS 1222 transputer .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 36113 IMS C004 programmable link switch 39714 IMS C011 link adaptor 41715 IMS C012 link adaptor 441A Packaging specifications 463B Obsolete devices 479Contents overviewI ContentsNotation and nomenclature xviiSignificance xviiSignal naming conventions xviiReferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. xviiExamples xviiTransputer product numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. xviii1 Company overview .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 INMOS.......................................................... 22 SGSTHOMSON Microelectronics................................. 23 Introduction to transputers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Quality and reliability 35 Military products 36 Development systems 32 Transputer architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Introduction..................................................... 61.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Transputers and occam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.2 System design rationale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.2.1 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.2.2 Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.2.3 Programmable components 81.3 Systems architecture rationale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.3.1 Point to point communication links. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.3.2 Local memory 91.4 Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 occam model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.12.2Overview .occam overview .2.2.1 Processes .Assignment .Input .1112121212ii ContentsOutput. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2.2 Constructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Parallel 13Communication .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Conditional. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Alternation 14Loop 15Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Replication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.2.3 Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.2.4 Declarations, arrays and subscripts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.2.5 Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.2.6 Functions 172.2.7 Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.2.8 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.2.9 Peripheral access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.3 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18PLACED PAR. .. .. .. . .. .. .. .. 18PRI PAR... .. .. .. .. .. .. . .. . 182.3.1 INMOS standard links 183 Error handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Program development ~ . . . . . 204.1 Logical behavior 204.2 Performance measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.3 Separate compilation of occam and other languages. . . . . . . . . . . . . . . . . . . . . . . . . . 204.4 Memory map and placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Physical architecture 225.1 INMOS serial links 225.1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.1.2 Link electrical specification 225.2 System services 225.2.1 Powering up and down, running and stopping . . . . . . . . . . . . . . . . . . . . . . . 225.2.2 Clock distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.3 Bootstrapping from ROM or from a link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.4 Peripheral interfacing 233 Transputer overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Transputer internal architecture 261.1 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271.2 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271.2.1 Direct functions 281.2.2 Prefix functions 281.2.3 Indirect functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Contents iii1.2.4 Expression evaluation 291.2.5 Efficiency of encoding 291.3 Support for concurrency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301.3.1 Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311.3.2 Interrupt latency 321.4 Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321.4.1 Internal channel communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321.4.2 External channel communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341.4.3 Communication links 351.5 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361.6 Alternative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371.7 Floating point instructions 371.7.1 Optimizing use of the stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381.7.2 Concurrent operation of FPU and CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381.8 Floating point unit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391.9 Graphics capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401.9.1 Example - drawing colored text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 Conclusion 434 Transputer instruction set summary 451 Introduction..................................................... 46Product identity numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Floating point unit .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Notation 472 Descheduling points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 Error instructions 484 Debugging support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 Floating point errors for the IMS T801 and IMS T805 only. . . . . . . . . . . 496 Block move 497 General instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 Floating' point instructions 568.1 Floating point instructions for IMS T801 and IMS T805 only. . . . . . . . . . . . . . . . . . . . 568.2 Floating point instructions for IMS T400, IMS T425 and IMS T426 only. . . . . . . . . . 585 Transputer performance 591 Introduction..................................................... 602 Performance overview 603 Fast multiply, TIMES 634 Arithmetic 635 Floating point operations 655.1 Floating point operations for IMS T801 and IMS T805 only 65iv Contents5.1.1 Floating point functions 655.2 Floating point operations for IMS T222 and IMS T225 . . . . . . . . . . . . . . . . . . . . . . . . . 665.3 Floating point operations for IMS T400, IMS T425 and IMS T426 . . . . . . . . . . . . . . . 665.4 Special purpose functions and procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 Effect of external memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 Interrupt latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 IMS T805 transputer 711 Introduction..................................................... 722 Pin designations 753 Floating point unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784.1 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784.2 CapPlus, CapMinus 784.3 Clockln. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784.4 ProcSpeedSelectO-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794.5 Bootstrap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804.6 Peek and poke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804.7 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814.8 Analyse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814.9 Error, Errorln 835 Memory......................................................... 846 External memory interface 866.1 Pin functions 876.1.1 MemAD2-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876.1.2 notMemRd 876.1.3 MemnotWrDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876.1.4 notMemWrBO-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876.1.5 notMemSO-4 ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876.1.6 MemWait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876.1.7 MemnotRfD1................................................... 876.1.8 notMemRf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876.1.9 RefreshPending. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876.1.10 MemReq, MemGranted 886.1.11 MemConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886.1.12 ProcClockOut. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . 886.2 Read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Contents v6.3 Write cycle ' . .. . .. . . .. . . . 956.4 Wait.................................................................... 966.5 Memory refresh .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986.6 Direct memory access 1016.7 Memory configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1046.7.1 Internal configuration 1046.7.2 External configuration 1067 Events.......................................................... 1128 Links........................................................... 1149 Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1179.1 DC electrical characteristics 1179.2 Equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1189.3 AC timing characteristics '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-199.4 Power rating " 12110 Package pinouts 12210.1 84 pin grid array package '. . . . . . . . . . . . . . . . .. 12210.2 84 pin PLCC J-bend package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12310.3 100 pin cavity-down ceramic quad flat pack package 12411 Ordering........................................................ 1257 IMST801 transputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1271 Introduction..................................................... 1282 Pin designations 1313 Floating point unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1324 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1344.1 Power , 1344.2 CapPlus, CapMinus 1344.3 Clockln. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. 1344.4 ProcSpeedSelectO-2 , 1354.5 Bootstrap , 1364.6 Peek and poke , 1364.7 Reset ' , 1374.8 Analyse , 1374.9 ErrorOut , 139vi Contents5 Memory......................................................... 1406 External memory interface 1426.1 Pin functions 1426.1.1 MemA2-31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1426.1.2 MemDO-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1426.1.3 notMemCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. 1436.1.4 notMemWrBO-3................................................ 1446.1.5 MemWait...................................................... 1446.1.6 MemReq, MemGranted ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1446.1.7 ProcClockOut. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1446.2 Read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1456.3 Write cycle 1466.4 Wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1476.5 Direct memory access 1497 Events ... ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1518 Links 1539 Electrical specifications : . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1569.1 DC electrical characteristics '........ 1569.2 Equivalent circuits '. . . . . . . . . .. 1589.3 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1599.4 Power rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16010 Package pinouts 16110.1 100 pin grid array package 16111 Ordering........................................................ 1628 IMS 1426 transputer 1631 Introduction '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1642 Pin designations 1663 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1683.1 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1683.2 CapPlus, CapMinus 1683.3 Clockln. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1683.4 ProcSpeedSelectO-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1693.5 Bootstrap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1703.6 Peek and poke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 170Contents vii3.7 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1713.8 Analyse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1713.9 Error, Errorln 1734 Memory 1745 External memory interface 1765.1 Pin functions 1775.1.1 MemAD2-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1775.1.2 ParityDataBitO-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1775.1.3 ParityCheckEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1775. 1.4 SoftParityError . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1775.1.5 HardParityError ,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1775.1.6 ParityErrorln, ParityErrorOut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1775.1.7 notMemRd 1775.1.8 MemnotWrDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1775.1.9 notMemWrBO-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1775.1.10 notMemSO-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1785.1.11 MemWait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1785.1.12 MemnotRfD1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1785.1.13 notMemRf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1785.1.14 RefreshPending. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1785.1.15 MemReq, MemGranted .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1785.1.16 MemConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1785.1.17 ProcClockOut. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1785.2 Processor clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1795.3 Strobes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1805.4 Read cycle 1825.5 Write cycle 1855.6 Parity errors 1875.7 Wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1905.8 Memory refresh .... . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1925.9 Direct memory access 1955.10 Memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1975.10.1 Internal configuration 1985.10.2 External configuration 2016 Events.......................................................... 2067 Links 2088 Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2118.1 Absolute maximum ratings 2118.2 Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2118.3 DC electrical characteristics 2128.4 Equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2128.5 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 213viii Contents8.6 Power rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . .. 2159 Package pinouts 2169.1 100 pin cavity-down ceramic quad flat pack package 21610 Ordering 2179 IMS 1425 transputer 2191 Introduction..................................................... 2202 Pin designations 2223 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2233.1 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2233.2 CapPlus, CapMinus 2233.3 Clockln. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2233.4 ProcSpeedSelectO-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2243.5 Bootstrap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2253.6 Peek and poke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2253.7 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2263.8 Analyse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2263.9 Error, Errorln 2284 Memory ........................................ 2295 External memory interface 2315.1 Pin functions 2325.1.1 MemAD2-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2325.1.2 notMemRd 2325.1.3 MemnotWrDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2325.1.4 notMemWrBO-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2325.1.5 notMemSO-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2325.1.6 MemWait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2325.1.7 MemnotRfD1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2325.1.8 notMemRf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2325.1.9 RefreshPending. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2325.1.10 MemReq, MemGranted 2335.1.11 MemConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2335.1.12 ProcClockOut. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2335.2 Read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2355.3 Write cycle 2405.4 Wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2415.5 Memory refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2435.6 Direct memory access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 246Contents ix5.7 Memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2495.7.1 Internal configuration 2495.7.2 External configuration 2516 Events.......................................................... 2577 Links 2598 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2628.1 Absolute maximum ratings 2628.2 Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2628.3 DC electrical characteristics 2638.4 Equivalent circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2638.5 AC timing characteristics , . . . . . . . . . .. 2648.6 Power rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2669 Package pinouts 2679.1 84 pin grid array package 2679.2 84 pin PLCC J-bend package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2689.3 100 pin cavity-down ceramic quad flat pack package 26910 Ordering 27010 IMS 1400 transputer 2711 Introduction..................................................... 2722 Pin designations 2743 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2753.1 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2753.2 CapPlus, CapMinus 2753.3 Clockln. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2753.4 ProcSpeedSelectO-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. 2763.5 Bootstrap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2773.6 Peek and poke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2773.7 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2783.8 Analyse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2783.9 Error, Errorln 2804 Memory - 2815 External memory interface 2835.1 Pin functions 284x Contents5.1.1 MemAD2-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2845.1.2 notMemRd 2845.1.3 MemnotWrDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2845.1.4 notMemWrBO-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2845.1.5 notMemSO-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2845.1.6 MemWait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2845.1.7 MemnotRfD1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2845.1.8 notMemRf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2845.1.9 RefreshPending. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2845.1.10 MemReq, MemGranted ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2855.1.11 MemConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2855.1.12 ProcClockOut. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2855.2 Read cycle 2875.3 Write cycle 2925.4 Wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2935.5 Memory refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2955.6 Direct memory access 2985.7 Memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3005.7.1 Internal configuration 3005.7.2 External configuration 3026 Events.......................................................... 3087 Links 3108 Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3138.1 DC electrical characteristics 3138.2 Equivalent circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3148.3 AC timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3158.4 Power rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3179 Package pinouts 3189.1 84 pin PLCC J-bend package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3189.2 100 pin plastic quad flat pack 3199.3 84 pin grid array package 32010 Ordering 32111 IMS 1225 transputer 3231 Introduction..................................................... 3242 Pin designations 3263 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3273.1 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 327Contents xi3.2 CapPlus, CapMinus 3273.3 Clockln .. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3273.4 ProcSpeedSelectO-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3293.5 Bootstrap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3293.6 Peek and poke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3303.7 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3303.8 Analyse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3303.9 Error '. . . . . . . . . . . . . . .. 3324 Memory......................................................... 3335 External memory interface 3355.1 Pin functions 3365.1.1 MemAO-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3365.1.2 MemDO-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3365.1.3 notMemWrBO-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3375.1.4 notMemCE '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3375.1.5 MemBAcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3375.1.6 MemWait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3375.1.7 MemReq, MemGranted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3375.1.8 ProcClockOut. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3375.2 Processor clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3385.3 Read cycles 3395.4 Write cycles 3405.5 MemBAcc 3415.5.1 Word Read/Write in Byte Access Mode 3415.5.2 Byte Write in Byte Access Mode 342Writing a Most Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 342Writing a Least Significant Byte 3425.6 Wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. 3445.7 Direct memory access 3456 Events.......................................................... 3487 Links .. 3498 Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3528.1 Absolute maximum ratings 3528.2 Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3528.3 DC electrical characteristics 3538.4 Equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3548.5 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3558.6 Power rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3569 Package pinouts 3579.1 68 pin grid array package 357xii Contents9.2 68 pin PLCC J-bend package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3589.3 100 pin cavity-up ceramic quad flat pack (CQFP) package. . . . . . . . . . . . . . . . . . . .. 35910 Ordering . . . . .. 36012 IMS 1222 transputer . . . . .. 3611 Introduction...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3622 Pin designations 3643 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3653.1 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3653.2 CapPlus, CapMinus 3653.3 Clockln. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3653.4 Bootstrap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3663.5 Peek and poke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3673.6 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3673.7 Analyse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3673.8 Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3694 Memory.......................................................... 3705 External memory interface 3725.1 ProcClockOut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3725.2 Tstates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3735.3 Internal access 3735.4 MemAO-15 . .. .. . . .. . .. .. . . . .. 3735.5 MemDO-15 3735.6 notMemWrBO-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3745.7 notMemCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3755.8 MemBAcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3785.8.1 Word Read/Write in Byte Access Mode ;........... 3785.8.2 Byte Write in Byte Access Mode 378Writing a Most Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 378Writing a Least Significant Byte 3785.9 MemWait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3805.10 MemReq, MemGranted 3826 Events.......................................................... 3847 Links 3858 Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3888.1 DC electrical characteristics ;............................ 388Contents xiii8.2 Equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3898.3 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3908.4 Power rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. 392'9 Package pinouts 3939.1 68 pin grid array package 3939.2 68 pin PLCC J-bend package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. 39410 Ordering '. . . . . . . . . .. 39513 IMS C004 programmable link switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3971 Introduction..................................................... 3982 Pin designations 3993 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4003.1 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4003.2 CapPlus, CapMinus 4003.3 Clockln. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4003.4 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4024 Links 4035 Switch implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4066 Applications 4076.1 Link switching 4076.2 Multiple IMS C004 control 4076.3 Bidirectional exchange , . . . . . . . .. 4076.4 Bus systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4077 Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4117.1 DC electrical characteristics 4117.2 Equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4127.3 AC timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4137.4 Power rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4148 Package pinouts 4158.1 84 pin grid array package 4159 Ordering ' 41614 IMS C011 link adaptor 4171 Introduction..................................................... 4182 Pin designations ~ . . . . . . . . . . . .. 4193 System services ..'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4203.1 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 420xiv Contents3.2 CapMinus ,: . . . . . . . . . . . . . .. 4203.3 Clockln. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4203.4 SeparatelQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4213.5 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4224 Links 4245 Mode 1 parallel interface 4275.1 Input port 4275.2 Output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4286 Mode 2 parallel interface 4296.1 DO-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4296.2 notCS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4296.3 RnotW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4296.4 RSO-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4296.4.1 Input Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4296.4.2 Input Status Register 4326.4.3 Output Data Register 4326.4.4 Output Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4326.5 Inputlnt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4326.6 Outputlnt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4336.7 Data read 4336.8 Data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4337 Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4347.1 DC electrical characteristics 4347.2 Equivalent circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. 4357.3 AC timing characteristics .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4367.4 Power'rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4388 Package pinouts 4398.1 28 pin DIL package and 28 pin SOJ package pinout 4399 Ordering ~ . . . . . . . . . . . . . . . . . . . . . . 44015 IMS C012 link adaptor 4411 Introduction..................................................... 4422 Pin designations '................. 443:,; System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4443.1 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 444Contents xv3.2 CapMinus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4443.3 Clockl n 4443.4 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4464 Links 4475 Parallel interface 4505.1 DO-7:.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4505.2 notCS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4505.3 RnotW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4505.4 RSO-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4505.4.1 Input Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4505.4.2 Input Status Register 4535.4.3 Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4535.4.4 Output Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4535.5 Inputlnt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4535.6 Outputlnt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4545.7 Data read 4545.8 Data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4546 Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4556.1 DC electrical characteristics 4556.2 Equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4566.3 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4576.4 Power rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4597 Package pinouts 4607.1 24 pin dual-in-line package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4608 Ordering........................................................ 461A Packaging specifications 4631 24 pin plastic dual-in-line (OIL) package dimensions 4642 28 pin plastic dual-in-line (OIL) package dimensions 4653 28 pin ceramic dual-in-line (OIL) package dimensions . . . . . . . . . . . . .. 4664 28 pin plastic small outline J-Ieaded (SOJ) package dimensions 4675 28 pin leadless chip carrier (LCC) package dimensions 4686 68 pin grid array (PGA) package dimensions 4697 pin leadless chip carrier (PLCC) J-bend packagedimensions 4708 84 pin grid array (PGA) package dimensions 4719 pin leadless chip carrier (PLCC) J-bend packagedimensions 47210 100 pin ceramic quad flat pack (CQFP) package dimensions. . . . . . .. 47310.1 100 pin cavity-down ceramic quad flat pack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 473xvi Contents10.2 100 pin cavity-up ceramic quad flat pack 47411 100 pin plastic quad flat pack (PQFP) package dimensions. . . . . . . .. 47512 100 pin grid array (PGA) package dimensions 47613 Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 477B Obsolete devices 4791 Introduction..................................................... 4801 IMS T800 transputer 4811. 1 Package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4821.1.1 84 pin grid array package ....,.................................... 4822 IMS T414 transputer 4832. 1 Package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4842.1.1 84 pin grid array package 4842.1.2 84 pin PLCC J-bend package , 4853 IMS T212 transputer 4873.1 Package specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4883.1.1 68 pin grid array package 4884 IMS M212 disk processor 4894.1 Package specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4904.1.1 68 pin grid array package 490Notation and nomenclatureNotation and nomenclatureThe nomenclature and notation in general use throughout this databook is described below.SignificancexviiThe bits in a byte are numbered 0 to 7, with bit 0 least significant. The bytes in words are numbered from 0,with byte 0 least significant. In general, wherever a value is treated as a number of component values, thecomponents are numbered in order of increasing numerical significance, with the least significant compo-nent numbered O. Where values are stored in memory, the least significant component value is stored atthe lowest (most negative) address.Similarly, components of arrays are numbered starting from 0 and stored in memory with component 0at the lowest address.Transputer memory is byte addressed, with words aligned on four-byte boundaries for 32 bit devices andon two-byte boundaries for 16 bit devices.Hexadecimal values are prefixed with #, as in #1DFWhere a byte is transmitted serially, it is always transmitted least significant bit (0) first. In general, wherev-er a value is transmitted as a number of component values, the least significant component is transmittedfirst. Where an array is transmitted serially, component 0 is transmitted first. Consequently, block transfersto and from memory areperformed starting with the lowest (most negative) address and ending with thehighest (most positive) one.In diagrams, the least significant component of a value is to the right hand side of the diagram. Compo-nent 0 of an array is at the bottom of a diagram, as are the most negative memory locations.Signal naming conventionsSignal names identifying individual pins of a transputer chip have been chosen to avoid being cryptic, giv-ing as much information as possible. The majority of transputer signals are active high. Those which areactive low have names commencing with not; names such as RnotW imply that the first component ofthe name refers to its active high state and the second to its active lowstate. Capitals are used to introducenew components of a name, as in ProcClockOut.All transputer signals described in the text of this databook are printed in bold. Registers and flags internalto a device are also printed in bold; instruction operation codes are printed in italics. Italics are also usedfor emphasis. occam program notation is printed in a fixed space teletype style.ReferencesThe databook is divided into chapters each containing a number of sections and subsections. Figures andtables have reference numbers tied to relevant sections of a particular chapter and unless otherwise statedrefer to sections within the current chapter.ExamplesSoftware and hardware examples given in this databook are outline design studies and are included toillustrate various ways in which transputers can be used. The examples are not intended to provide accu-rate application designs.xviiiTransputer product numbersProduct numbers take the following form:IMS abbbc-xyyzIMS = INMOS company identifiera =Product groupT =TransputerC =Communications peripheralS = general softwareo = Development softwareF =Application softwareB=Motherboards and TRAMsbbb = Unique product identifiere.g. 805 =32 bit transputer, FPU, 4K memory, 4 links.c =Revision codeTransputer product numbersThis is not present on all products.Product traceability is guaranteed by a separate lot number found elsewhere on the package.x =Package typeG=PGAP =Plastic OILS =Ceramic OILJ =PLCCF == 0SEQproduct := 1SEQ i = 1 FOR nproduct .- product * iRESULT productdefines the function factorial, which may appear in expressions such asm := factorial (6)2.2.7 ExpressionsAn expression is constructed from the operators given in table 2.2, from variables, numbers, the truth val-ues TRUE and FALSE, and the brackets ( and) .Operator Operand types Description+ - * / REM integer, real arithmetic operatorsPLUS MINUS TIMES AFTER integer modulo arithmetic= any primitive relational operators> < >= < "-integers bitwise operators: and, or, xor, not integer shift operatorsTable 2.2 OperatorsFor example, the expression(5 + 7) / 2evaluates to 6, and the expression(#lDF /\ #FO) 4evaluates to #0 (the character # introduces a hexadecimal constant).A string is represented as a sequence of ASCII characters, enclosed in double quotation marks". If thestring has n characters, then it is an array of type [nJ BYTE.2.2.8 TimerAll transputers incorporate a timer. The implementation directly supports the occam model of time. Eachprocess can have its own independent timer, which can be used for internal measurement or for real timescheduling.A timer input sets a variable to a value of type INT representing the time. The value is derived from a clock,which changes at regular intervals, for example:tim ? vsets the variable v to the current value of a free running clock, declared as the timer tim.18A delayed input takes the following formtim ? AFTER e2 Transputer architectureA delayed input is unable to proceed until the value of the timer satisfies (timer AFTER e). The comparisonperformed is a modulo comparison. This provides the effect that, starting at any point in the timer's cycle,the previous half cycle of the timer is considered as being before the current time, and the next half cycleis considered as being after the current time.2.2.9 Peripheral accessThe implementation of occam provides for peripheral access by extending the input and output primitiveswith a port input/output mechanism. A port is used like an occam channel, but has the effect of transfer-ring information to and from a block of addresses associated with a peripheral.Ports behave like occam channels in that only one process may input from a port, and only one processmay output to a port. Thus ports provide a secure method of accessing external memory mapped statusregisters etc.Note that there is no synchronization mechanism associated with port input and output. Any timing con-straints which result from the use of asynchronous external hardware will have to be programmed explicit-ly. For example, a value read by a port input may depend upon the time at which the input was executed,and inputting at an invalid time would produce unusable data.During applications development it is recommended that the peripheral is modelled by an occam processconnected via channels.2.3 Configurationoccam programs may be configured for execution on one or many transputers. The transputer develop-ment system provides the necessary tools for correctly distributing a program configured for manytransputers.Configuration does not affect the logical behavior of a program (see section four, Program development).However, it does enable the program to be arranged to ensure that performance requirements are met.PLACED PARA parallel construct may be configured for a network of transputers by using the PLACED PAR construct.Each component process (termed a placement) is executed by a separate transputer. The variables andtimers used in a placement must be declared within each placement process.PRI PAROn any individual transputer, the outermost parallel construct may be configured to prioritize its compo-nents. Each process is executed at a separate priority. The first process has the highest priority, the lastprocess has the lowest priority. Lower priority components may only proceed when all higher priority com-ponents are unable to proceed.2.3.1 INMOS standard linksEach link provides one channel in each direction between two transputers.A channel (which must already have been declared) is associated with a link by a channel association,for example:PLACE LinkOlnput AT 4 :3 Error handling 193 Error handlingErrors in occam programs are either detected by the compilerorcan be handled at runtime in one of threeways.1. Cause the process to STOP allowing other processes to continue.2. Cause the whole system to halt.3. Have an arbitrary (undefined) effect.The occam process STOP starts but never terminates. In method 1, an errant process stops and in partic-ular cannot communicate erroneous data to other processes. Other processes will continue to executeuntil they become dependent on data from the stopped process. It is therefore possible, for example, towrite a process which uses a timeout to warn of a stopped process, or to construct a redundant systemin which several processes performing the same task are used to enable the system to continue after oneof them has failed.Method 1 is the preferred method of executing a program.Method 2 is useful for program development and can be used to bring transputers to an immediate halt,preventing execution of further instructions. The transputer Error output can be used to inform the trans-puter development system that such an error has occurred. No variable local to the process can be over-written with erroneous data, facilitating analysis of the program and data which gave rise to the error.Method 3 is useful only for optimizing programs which are known to be correct!When a system has stopped or halted as a result of an error, the state of all transputers in the system canbe analyzed using the transputer development system.For languages other than occam, the transputer provides facilities for handling individual errors by soft-ware.204 Program development2 Transputer architectureThe development of programs for multiple processor systems can involve experimentation. In somecases, the most effective configuration is not always clear until a substantial amount of work has beendone. For this reason, it is desirable that most of the design and programming can be completed beforehardware construction is started.4.1 Logical behaviorAn important property of occam in this context is that it provides a clear notion of 'logical behavior'; thisrelates to those aspects of a program not affected by real time effects.It is guaranteed that the logical behavior of a program is not altered by the way in which the processesare mapped onto processors, or by the speed of processing and communication. Consequently a programultimately intended for a network oftransputers can be compiled, executed and tested on a single comput-er used for program development.Even if the application uses only a single transputer, the program can be designed as a set of concurrentprocesses which could run on a number of transputers. This design style follows the best traditions ofstructured programming; the processes operate completely independently on their own variables exceptwhere they explicitly interact, via channels. The set of concurrent processes can run on a single transputeror, for a higher performance product, the processes can be partitioned amongst a number of transputers.It is necessary to ensure, on the development system, that the logical behavior satisfies the applicationrequirements. The only ways in which one execution of a program can differ from another in functionalterms result from dependencies upon input data and the selection of components of an ALT. Thus a simplemethod of ensuring that the application can be distributed to achieve any desired performance is to designthe program to behave 'correctly' regardless of input data and ALT selection.4.2 Performance measurementPerformance information is useful to gauge overall throughput of an application, and has to be consideredcarefully in applications with real time constraints.Prior to running in the target environment, an occam program should be relatively mature, and indee9should be correct except for interactions which do not obey the occam synchronization rules. These areprecisely the external interactions of the program where the world will not wait to communicate with anoccam process which is not ready. Thus the set of interactions that need to be tested within the targetenvironment are well identified.Because, in occam, every program is a process, it is extremely easy to add monitor processes or simula-tion processes to represent parts of the real time environment, arid then to simulate and monitor the antici-pated real time interactions. The occam concept of time and its implementation in the transputer is impor-tant. Every process can have an independent timer enabling, for example, all the real time interactionsto be modelled by separate processes and any time dependent features to be simulated.4.3 Separate compilation of occam and other languagesA program portion which is separately compiled, and possibly written in a language other than occam,may be executed on a single transputer.If the program is written in occam, then it takes the form of a single PROC, with only channel parameters.If the program is written in a language other than occam, then a run-time system is provided which pro-vides input/output to occam channels.4 Program development21Such separately compiled program portions are linked together by a framework of channels, termed a har-ness. The harness is written in occam. It includes all configuration information, and in particular specifiesthe transputer configuration in which the separately compiled program portion is executed.Transputers are designed to allow efficient implementations of high level languages, such as C, Pascaland Fortran. Such languages will be available in addition to occam.At runtime, a program written in such a language is treated as a single occam process. Facilities are pro-vided in the implementations of these languages to allow such a program to communicate on occamchannels. It can thus communicate with other such programs, or with programs written in occam. Theseprograms may reside on the same transputer, in which case the channels are implemented in store, ormay reside on different transputers, in which case the channels are implemented by transputer links.It is therefore possible to implement occam processes in conventional high level languages, and arrangefor them to communicate. It is possible for different parts of the same application to be implemented indifferent high level languages.The standard input and output facilities provided within these languages are implemented by a well-de-fined protocol of communications on occam channels.The development system provides facilities for management of separately compiled occam.4.4 Memory map and placementThe low level memory model is of a signed address space.Memory is byte addressed, the lowest addressed byte occupying the least significant byte position withinthe word.The implementation of occam supports the allocation of the code and data areas of an occam processto specific areas of memory. Such a process must be a separately compiled PROC, and must not referenceany variables and timers other than those declared within it.225 Physical architecture5.1 INMOS serial links5.1.1 Overview2 Transputer architectureAll transputers have several links. The link protocol and electrical characteristics form a standard for allINMOS transputer and peripheral products.All transputers support a standard link communications frequency of 10 Mbits/sec. Some devices alsosupport other data rates. Maintaining a standard communications frequency means that devices of mixedperformance and type can intercommunicate easily.Each link consists of two unidirectional signal wires carrying both data and control bits. The link signalsare TTl compatible so that their range can be easily extended by inserting buffers.The INMOS communication links provide for communication between devices on the same printed circuitboard or between printed circuit boards via a back plane. They are intended to be used in electrically quietenvironments in the same way as logic signals between TTl gates.The number of links, and any communication speeds in addition to the standard speed of 10 Mbits/sec,are given in the product data for each product.5.1.2 Link electrical specificationThe quiescent state of the link signals is low, for a zero. The link input signals and output signals are stan-dard TTl compatible signals.For correct functioning of the links the specifications for maximum variation in clock frequency betweentwo transputers joined by a link and maximum capacitive load must be met. Each transputer product alsohas specified the maximum permissible variation in delay in buffering, and minimum permissible edge gra-dients. Details of these specifications are provided in the product data.Provided that these specifications are met then any buffering employed may introduce an arbitrary delayinto a link signal without affecting its correct operation.5.2 System services5.2.1 Powering up and down, running and stoppingAt all times the specification of input voltages with respect to the GND and VCC pins must be met. Thisincludes the times when the VCC pins are ramping to 5 V, and also while they are ramping from 5 V downto 0 V.The system services comprise the clocks, power, and signals used for initialization.The specification includes minimum times that VCC must be within specification, the input clock must beoscillating, and the Reset signal must be high before Reset goes low. These specifications ensure thatinternal clocks and logic have settled before the transputer starts.When the transputer is reset the memory interface is initialized (if present and configurable).The processor and INMOS serial links start after reset. The transputer obeys a bootstrap program whichcan either be in off-chip ROM or can be received from one of the links. Howto specify where the bootstrapprogram is taken from depends upon the type of transputer being used. The program will normally loadup a larger program either from ROM or from a peripheral such as a disk.5 Physical architecture23During power down, as during power up, the input and output pins must remain within specification withrespect to both GND and VCC.A software error, such as arithmetic overflow, array bounds violation or divide by zero, causes an error flagto be set in the transputer processor. The flag is directly connected to the Error pin. Both the flag and thepin can be ignored, or the transputer stopped. Stopping the transputer on an error means that the errorcannot cause further corruption.As well as containing the error in this way it is possible to determine the state of the transputer and itsmemory at the time the error occurred.5.2.2 Clock distributionAll transputers operate from a standard 5MHz input clock. High speed clocks are derived internally fromthe lowfrequency input to avoid the problems of distributing high frequency clocks. Within limits the mark-to-space ratio, the voltage levels and the transition times are immaterial. The limits on these are given inthe product data for each product. The asynchronous data reception of the links means that differencesin the clock phase between chips is unimportant.The important characteristic of the transputer's input clock is its stability, such as is provided by a crystaloscillator. An R-C oscillator is inadequate. The edges of the clock should be monotonic (without kinks),and should not undershoot below -0.5 V.5.3 Bootstrapping from ROM or from a linkThe program which is executed after reset can either reside in ROM in the transputer's address space orit can be loaded via anyone of the transputer's INMOS serial links.The transputer bootstraps from ROM by transferring control to the top two bytes in memory, which will in-variably contain a backward jump into ROM.If bootstrapping from a link, the transputer bootstraps from the first link to receive a message. The first byteof the message is the count of the number of bytes of program which follow. The program is loaded intomemory starting at a product dependent location MemStart, and then control is transferred to this address.Messages subsequently arriving on other links are not acknowledged until the transputer processor obeysa process which inputs from them. The loading of a network of transputers is controlled by the transputerdevelopment system, which ensures that the first message each transputer receives is the bootstrap pro-gram.5.4 Peripheral interfacingAll transputers contain one or more INMOS serial links. Certain transputer products also have other appli-cation specific interfaces. The peripheral control transputers contain specialized interfaces to control aspecific peripheral or peripheral family.In general, atransputer based application will comprise a number oftransputers which communicate usingINMOS links. There are three methods of communicating with peripherals.The first is by employing peripheral control transputers (eg for graphics or disks), in which the transputerchip connects directly to the peripheral concerned (figure 5.1). The interface to the peripheral is implem-ented by special purpose hardware within the transputer. The application software in the transputer is im-plemented as an occam process, and controls the interface via occam channels linking the processorto the special purpose hardware.The second method is by employing link adaptors (figure 5.2). These devices convert between a link anda specialized interface. The link adaptor is connected to the link of an appropriate transputer, which con-tains the application designer's peripheral device handler implemented as an occam process.24 2 Transputer architectureThe third method is by memory mapping the peripheral onto the memory bus of a transputer (figure 5.3).The peripheral is controlled by memory accesses issued as a result of PORT inputs and outputs. The appli-cation designer's peripheral device handler provides a standard occam channel interface to the rest ofthe application.The first transputers implement an event pin which provides a simple means for an external peripheral torequest attention from a transputer.In all three methods, the peripheral driver interfaces to the rest of the application via occam channels.Consequently, a peripheral device can be simulated by an occam process. This enables testing of allaspects of a transputer system before the construction of hardware.Peripheral controltransputerIPeripheral control H~ __tr_a_ns_p_u_te_r__~ l TransputerII r--'--- ~11 Peripheral control I,'I; transputer II. Figure 5.1 Transputer with peripheral control transputersLink adaptor TransputerFigure 5.2 Transputer with link adaptorsLink adaptorPeripheral chip Peripheral chipTransputerr < - - - - - - - ~ >~ - - - - - - - - - - - - - - -Figure 5.3 Memory mapped peripheralsDITTImos=Chapter 3Transputer.overview25261 Transputer internal architecture3 Transputer overviewInternally, a transputer consists of a memory, processor and communications system connected via a32-bit bus. The bus also connects to the external memory interface, enabling additional local memory tobe used. The processor, memory and communications system each occupy about 25% of the total siliconarea, the remainder being used for power distribution, clock generators and external connections.The processor contains instruction processing logic, instruction and work pointers, and an operand regis-ter. It directly accesses the high speed on-chip memory, which can store data or program. Where largeramounts of memory or programs in ROM are required, the processor has access to 4 Gbytes (32 bit) or64Kbytes (16 bit) of memory via the External Memory Interface (EMI).The floating point transputers each have an on-chip floating point unit. The small size and high perform-ance of this unit come from a design which takes careful note of silicon economics. This contrasts starklywith conventional co-processors, where the floating point unit typically occupies more area than a com-plete micro-processor, and requires a second chip.The block diagram figure 1.1 indicates the way in which the major blocks of the transputer are intercon-nected.RAM RAMMemory interface Memory interfaceFloating point transputer TransputerFigure 1.1 Transputer interconnectionsThe CPU of the transputer contains three registers (A, B and C) used for integer and address arithmetic,which form a hardware stack. Loading a value into the stack pushes B into C, and A into B, before load-ing A. Storing a value from A pops B into A and C into B. Similarly, the FPU includes a three register floa-ting-point evaluation stack, containing the AF, BF, and CF registers. When values are loaded onto, orstored from the stack the AF, BF and CF registers push and pop in the same way as the A, Band C regis-ters.The addresses of floating point values are formed on the CPU stack, and values are transferred betweenthe addressed memory locations and the FPU stack under the control of the CPU. As the CPU stack isused only to hold the addresses of floating point values, the wordlength of the CPU is independent of thatof the FPU. Consequently, itwould be possible to use the same FPU together with a 16-bit CPU. The trans-puter scheduler provides two priority levels. The FPU register stack is duplicated so that when the floatingpoint transputer switches from low to high priority none of the state in the floating point unit is written tomemory. This results in a worst-case interrupt response of about 3 Ils. Furthermore, the duplication of theregister stack enables floating point arithmetic to be used in an interrupt routine without any performancepenalty.Transputer internal architecture 271.1 RegistersThe design of the transputer processor exploits the availability of fast on-chip memory by having only asmall number of registers; the CPU contains six registers which are used in the execution of a sequentialprocess. The small number of registers, together with the simplicity of the instruction set enables the pro-cessor to have relatively simple (and fast) data-paths and control logic.The six registers are:The workspace pointer which points to an area of store where local variables are kept.The instruction pointer which points to the next instruction to be executed.The operand register which is used in the formation of instruction operands.The A, Band C registers which form an evaluation stack.The A, Band C registers are the sources and destinations for most arithmetic and logical operations.Loading a value into the stack pushes B into C, and A into B, before loading A. Storing a value from A,pops B into A and C into B.Registers Locals ProgramABCWorkspaceNext InstructionOperandIFigure 1.2 Registers used in sequential integer processesExpressions are evaluated on the evaluation stack, and instructions refer to the stack implicitly. For exam-ple, the add instruction adds the top two values in the stack and places the result on the top of the stack.The use of a stack removes the need for instructions to respecify the location of their operands. Statisticsgathered from a large number of programs showthat three registers provide an effective balance betweencode compactness and implementation complexity.No hardware mechanism is provided to detect that more than three values have been loaded onto thestack. It is easy for the compiler to ensure that this never happens.Any location in memory can be accessed relative to the workpointer register, enabling the workspace tobe of any size. .Further register details are given in Transputer Instruction Set - A Compiler Writer's Guide.1.2 InstructionsIt was a design decision that the transputer should be programmed in a high-level language. The instruc-tion set has, therefore, been designed for simple and efficient compilation of high-level languages. It con-tains a relatively small number of instructions, all with the same format, chosen to give a compact repre-sentation of the operations most frequently occurring in programs. The instruction set is independent of28 3 Transputer overviewthe processor wordlength, allowing the same microcode to be used for transputers with different word-lengths. Each instruction consists of a single byte divided into two 4-bit parts. The four most significantbits of the byte are a function code, and the four least significant bits are a data value.Function Data7 4 3 o1.2.1 Direct functionsFigure 1.3 Instruction formatThe representation provides for sixteen functions, each with a data value ranging from 0 to 15. Thirteenof these are used to encode the most important functions performed by any computer. These include:load constantload localload non-localjumpadd constantstore localstore non-localconditional jumpload local pointercallThe most common operations in a program are the loading of small literal values, and the loading andstoring of one of a small number of variables. The load constant instruction enables values between 0 and15 to be loaded with a single byte instruction. The load local and store local instructions access locationsin memory relative to the workspace pointer. The first 16 locations can be accessed using a single byteinstruction.The load non-local and store non-local instructions behave similarly, except that they access locations inmemory relative to the A register. Compact sequences of these instructions allow efficient access to datastructures, and provide for simple implementations of the static links or displays used in the implementa-tion of high level programming languages such as occam, C, Fortran, Pascal, or ADA.1.2.2 Prefix functionsTwo more of the function codes are used to allow the operand of any instruction to be extended in length.These are:prefix negative prefixAll instructions are executed by loading the four data bits into the least significant four bits of the operandregister, which is then used as the instruction's operand. All instructions except the prefix instructions endby clearing the operand register, ready for the next instruction.Function7Operand RegisterFigure 1.4 Instruction operand registerThe prefix instruction loads its four data bits into the operand register, and then shifts the operand registerup four places. The negative prefix instruction is similar, except that it complements the operand registerbefore shifting it up. Consequently operands can be extended to any length up to the length of the operandregister by a sequence of prefix instructions. In particular, operands in the range -256 to 255 can be repre-sented using one prefix instruction.Transputer internal architecture 29The use of prefix instructions has certain beneficial consequences. Firstly, they are decoded and executedin the same way as every other instruction, which simplifies and speeds instruction decoding. Secondly,they simplify language compilation, by providing a completely uniform way of allowing any instruction totake an operand of any size. Thirdly, they allow operands to be represented in a form independent of theprocessor wordlength.1.2.3 Indirect functionsThe remaining function code, operate, causes its operand to be interpreted as an operation on the valuesheld in the evaluation stack. This allows up to 16 such operations to be encoded in a single byte instruction.However, the prefix instructions can be used to extend the operand of an operate instruction just like anyother. The instruction representation therefore provides for an indefinite number of operations.The encoding of the indirect functions is chosen so that the most frequently occurring operations are repre-sented without the use of a prefix instruction. These include arithmetic, logical and comparison operationssuch asadd exclusive or greater thanLess frequently occurring operations have encodings which require a single prefix operation (the transput-er instruction set is not large enough to require more than 512 operations to be encoded!).The IMS T800 has additional instructions which load into, operate on, and store from, the floating pointregister stack. It also contains new instructions which support color graphics, pattern recognition and theimplementation of error correcting codes. These instructions have been added whilst retaining the existinginstruction set. This has been possible because of the extensible instruction encoding used in transputers.1.2.4 Expression evaluationEvaluation of expressions sometimes requires use of temporary variables in the workspace, but the num-ber of these can be minimised by careful choice of the evaluation order.Programx:= 0x:= #24x := y + zMnemonicIdc 0stl xpfix 2Idc 4stl xIdl YIdl zaddstl xTable 1.1 Expression evaluation1.2.5 Efficiency of encodingMeasurements show that about 70% of executed instructions are encoded in a single byte (ie without theuse of prefix instructions). Many of these instructions, such as load constant and add require just one pro-cessor cycle.The instruction representation gives a more compact representation of high level language programs thanmore conventional instruction sets. Since a program requires less store to represent it, less of the memorybandwidth is taken up with fetching instructions. Furthermore, as memory is word accessed the processorwill receive several instructions for every fetch.30 3 Transputer overviewShort instructions also improve the effectiveness of instruction prefetch, which in turn improves processorperformance. There is an extra word of prefetch buffer so that the processor rarely has to wait for an in-struction fetch before proceeding. Since the buffer is short, there is little time penalty when a jump instruc-tion causes the buffer contents to be discarded.1.3 Support for concurrencyThe processor provides efficient support for the occam model of concurrency and communication. It hasa microcoded scheduler which enables any number of concurrent processes to be executed together,sharing the processor time. This removes the need for a software kernel. The processor does not needto support the dynamic allocation of storage as the occam compiler is able to perform the allocation ofspace to concurrent processes.A process starts, performs a number of actions, and then either stops without completing or terminatescomplete. Typically, a process is a sequence of instructions. A transputer can run several processes inparallel (concurrently). Processes may be assigned either high or low priority, and there may be any num-ber of each.At any time, a concurrent process may beactive - being executed- on a list waiting to be executedinactive - ready to input- ready to output- waiting until a specified timeThe scheduler operates in such a way that inactive processes do not consume any processor time. Theactive processes waiting to be executed are held on a list. This is a linked list of process workspaces, im-plemented using two registers, one of which points to the first process on the list, the other to the last. Infigure 1.5, S is executing, and P, Q and R are active, awaiting execution. Only the low priority processqueue registers are shown; the high priority process ones perform in a similar manner.Program IFigure 1.5 Linked process listTransputer internal architectureFunction High Priority Low PriorityPointer to front of active process list FptrO Fptr1Pointer to back of active process list BptrO Bptr131Table 1.2 Priority queue control registersA process is executed until it is unable to proceed because it is waiting to input or output, or waiting forthe timer. Whenever a process is unable to proceed, its instruction pointer is saved in its workspace andthe next process is taken from the list. Actual process switch times are very small as little state needs tobe saved; it is not necessary to save the evaluation stack on rescheduling.In order for several processes to operate in parallel, a low priority process is only permitted to run for amaximum of two time slices before it is forcibly descheduled at the next descheduling point (section 2).The time slice period is 5120 cycles of the external 5 MHz clock, giving ticks approximately 1 ms apart.A process can only be descheduled on certain instructions, known as descheduling points. As a result,an expression evaluation can be guaranteed to execute without the process being timesliced part waythrough.Whenever a process is unable to proceed, its instruction pointer is saved in the process workspace andthe next process taken from the list. Process scheduling pointers are updated by instructions which causescheduling operations, and should not be altered directly. Actual process switch times are less than 1 as little state needs to be saved and it is not necessary to save the evaluation stack on rescheduling.The processor provides a number of special operations to support the process model. These include:start process end processWhen a parallel construct is executed, start process instructions are used to create the necessary