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Industrial Motor Drive on a Single FPGALower Cost, Higher Performance, and Faster Design

Drives and motors are an integral part o industrial equipment rom packaging,

robotics, computer numerical control (CNC), machine tools, industrial pumps,

and ans. Designing next-generation drive systems to lower operating costs

requires complex control algorithms at very low latencies as well as a exible

platorm to support changing needs and the ability to design multiple-axis

systems.

raditional drive systems based on ASICs, digital signal processors (DSPs), and

microcontroller units lack the perormance and exibility to address these needs.

Alteras amily o FPGAs provides a scalable platorm that can be used to ooad

control algorithm elements in hardware. You may also integrate the whole drive

system with industry-proven processor architectures while supporting multiple

types o encoders and industrial Ethernet protocols. Tis drive on a chip system

reduces cost and simplies development.

Lower Costs Through Design Integration

Reducetotalcostofownershipwithourdrive-on-a-chip

system:- CombinesaCycloneVFPGAwithahigh-performance,

dual-coreARMprocessorsubsystemorwithour

exibleNiosIIsoftprocessorallowingyoutotightly coupletheprocessorsubsystemwithhardware

acceleratorsformotorcontrol

- Extendfunctionalitybyintegratingindustrial networking,encoderinterfaces,I/O,analog

interfaces,andlogic

Saveboardspaceandreducepowerconsumptionwithfewerrequiredcomponentsandtheabilitytosupport

multi-axiscontrol Adaptquicklytochangingmarketrequirementswithlessdesignworkthroughoursupportforleading

industrialEthernetprotocolsandI/OstandardsIndustrialEthernet

ADC I/F

PositionEncoder I/F

FPGA/CPLDSafety Device

Safety IP

Motor ControlAlgorithm

PHY

PHY

IGBTControl I/F

PowerStage

A/D

Converters

PLC /DCS with Safety

CycloneV FPGA

Encoder(s)

Multiple Motors

ARM/Nios IIProcessorReduce Time To Market

Savedevelopmenttimeandlowerriskfordesigningproductvariantsbyreusingintellectualproperty(IP)

coresandleveragingtheARMecosystem

Reduceyoursafetycerticationtimebyupto24

monthswithourTVRheinland-qualiedIEC61508FunctionalSafetyFPGAdatapackage

Meeting Higher-Performance Drive Requirements

Implementcontrol-loopalgorithmlatenciesoflessthan5susingourvariable-precisionDSPblocks,

multipliers,supportforoatingpoint,andarithmeticDSPfunctions

Optimizeyourdesignbypartitioningbetweensoftware

andhardwareelementsusingourmodel-baseddesignmethodologywithsystem-leveldesigntools

Figure 1: Cyclone V or Cyclone V SoCs: Single Drive Device IntegratesHigh-performance Processor Subsystem with Motor Control Algorithm,

I/O Logic, Industrial Ethernet Protocols, and Safety Elements

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Altera Corporation

101InnovationDriveSanJose,CA95134

USA

Telephone:(408)544-7000

www.altera.com

Altera European Headquarters

HolmersFarmWayHighWycombe

Buckinghamshire

HP124XF

UnitedKingdom

Telephone:(44)1494602000

Altera Japan Ltd.

Shinjukui-LandTower32F6-5-1,Nishi-Shinjuku

Shinjuku-ku,Tokyo163-1332

Japan

Telephone:(81)333409480

www.altera.co.jp

Altera International Ltd.Unit11-18,9/F

MillenniumCity1,Tower1

388KwunTongRoad

KwunTong

Kowloon,HongKong

Telephone:(852)29457000

2013 Altera Corporation. All r ights reserved. ALERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARUS and SRAIX words and logos are trademarks o AlteraCorporation and registered in the U.S. Patent and rademark Oce and in other countries. All other words and logos identied as trademarks or service marks are the property o theirrespective holders as described at www.altera.com/legal.PDF; March 2013 SS-1033-3.0

System-Level Design Flow Tailored for DSP Performance

o optimize your motor control algorithms and designs, you will need versatile tools and a

practical design methodology. Figure 2 shows a tool ow that helps model and simulate the

system, implement complex algorithms with low latency, integrate the hardware/soware

system, and ne-tune the perormance to the exact needs o the motor drive.You also can take advantage o easy-to-use development tools, such as Quartus II design

soware, and system integration tools, such as Qsys and DSP Builder or DSP optimization.

With support or model-based environments such as Simulink/MALAB to model the

algorithm, you can integrate a motor control system directly to the DSP Builder tool or the

most optimized drive designs. Whats more, you can use the amiliar tool ow and resources o

the rich ARM ecosystem with our SoCs to reduce development time and take advantage o

legacy code.

Altera Cyclone V FPGA and Cyclone V SoC Portfolio

Our Cyclone V FPGAs and Cyclone V SoCs join a diverse amily o 28 nm FPGAs that are

tailored to your design requirements. Cyclone V FPGAs provide the industrys lowest system

cost and power, along with multiport memory support such as DDR3/LPDDR, integrated

transceiver options, variable-precision DSP blocks, and perormance levels that make the device

amily ideal or diferentiating your high-volume applications. Youll also get up to 40 percent

lower total power versus the previous generation and ecient logic integration capabilities.

Figure 2: System-Level Optimized Design Flow for Altera SoC Drive System

Want to Dig Deeper?

For more inormation about

Alteras FPGAs and SoCs or motor

control applications, contact your

local Altera sales representative or

FAE, or visit

www.altera.com/industrial.

Model

System

(Optional)

Develop

Algor ith m

in Software

Accelerate Alg ori thm

in Hardware

Simulink/MATLAB

Integrate

System Hardware

Compile

Design

Integrate with

App lic atio n Sof tware

Optimized

System

ARM orNios II

Processor

Quartus IISoftware

ARMor Nios IIProcessor

Software Tools

SoC

Algorithmin C

AlgorithmUsing

DSP Builder

Qsys SystemIntegration

Tool

http://www.altera.com/http://www.altera.co.jp/http://www.altera.co.jp/http://www.altera.com/