US ATLASHL-LHC Upgrade BASIS of ESTIMATE (BoE)

Date of Est: 2/28/2019Prepared by: Junjie ZhuResponsible Inst: University of MichiganDocdb #: HL-LHC-docDB-236

WBS number: 6.6.3 WBS Title: TDC

WBS Dictionary Definition: This WBS covers the design, prototyping, production, and testing of the Time-to-digital converter (TDC) Application-Specific Integrated Circuits (ASIC) for the ATLAS Monitored Drift Tube (MDT) front-end electronics upgrade. This ASIC converts the muon drift time into digital outputs and sends data to the Chamber Service Module (CSM) in either triggerless or triggered mode. In total 15,300 TDC ASICS are needed for the whole MDT system.Estimate Type (check all that apply – see BOE Report for estimate type by activity):

___ Existing Purchase Order or Work Complete___ Engineering Build-up_X_ Extrapolating from Actuals_X_ Analogy__ Expert Opinion

Supporting Documents (including but not limited to): Attachments 1-4

Details of the Base Estimate (Explanation of the Work)This WBS covers the design, prototyping, production, and testing of the TDC ASIC for the upgrade of the ATLAS muon MDT detector. The TDC is responsible for the time digitization of tube signals, which is the basis for all following MDT trigger and readout processing. To satisfy different needs, the TDC needs to either send all muon hits off chambers to the ATLAS counter room (referred to as the triggerless mode) or store digitized timing information in a buffer memory waiting for a trigger accept signal (referred to as the trigger mode). The TDC will be fabricated using the TSMC 130 nm CMOS technology.

Pre-MREFC R&D Phase (Task Groups 01 – 03) The R&D phase consists of one demonstrator and two prototypes. The demonstrator prototype was fabricated using the GlobalFoundires 130 nm CMOS process. The purpose of the demonstrator was to develop and validate the overall TDC design architecture. The first prototype was fabricated using the TSMC 130 nm CMOS process and all needed features were included except TMR for all configuration parameters and clock trees. The second prototype is foreseen to address small issues with the first prototype and have TMR protections implemented. We need to design specific printed-circuit boards and setup a data acquisition system to test each prototype. We will perform studies in our laboratory either in a standalone lab-bench test or with MDT/sMDT chambers. In addition, we will perform radiation tests and have joint tests with latest ASD and CSM prototypes.

MREFC Construction Phase (Task Groups 04 – 05) Production tasks include pre-production and final production runs, chip packaging, QA/QC of all produced ASICs, and shipping to the mezzanine card production sites. A yield factor is applied that

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reflects the efficiency of producing functional dies (90%), the efficiency of functional TDC packages (92%), and the efficiency of functional chips mounted on the mezz cards (90%). The total number of chips to be produced is (15300+1530)/(0.9×0.92×0.9)=22000. Pre-production of 10% ASICs is needed prior to the Production Readiness Review (PRR). These pre-production chips will be used as spares. The following table shows the number of ASICs required.

Cost Estimate

Sum of Value

FY17 FY18 FY19 FY20 FY21 FY22 FY23Grand Total

Pre-MREFC 54,40298,26

9181,49

0 62,992 397,153

ENG 10,36959,07

5 70,118 20,246 159,808EQUIP 49,809 12,020 61,829MAT 13,860 5,840 12,031 17,210 48,941

STU 21,98311,00

9 22,982 12,830 68,804

TECH 22,34

4 15,323 686 38,353TRAVD 2,394 8,154 10,548TRAVF 5,796 3,074 8,870

MREFC264,96

5712,60

6626,93

816,94

81,621,45

8

ENG 117,80

0164,61

5179,11

2 8,199 469,727

EQUIP 394,82

5244,61

2 639,438MAT 14,890 8,910 301 24,102

STU 58,024121,69

6 5,571 185,291

TECH 143,58

5 80,251 72,608 2,876 299,321TRAVF 3,580 3,580

Grand Total 54,40298,26

9181,49

0327,95

7712,60

6626,93

816,94

82,018,61

1

Cost Estimate DescriptionThe overall project cost is composed of M&S (38%), Labor (61%), and Travel (1%). M&S costs mainly come from the non-recurring engineering (NRE) cost for the pre-production/production runs, purchase of wafers to produce 22k chips, and chip packaging. In addition, there is a submission fee for each prototype run (demonstrator, v1, and v2). The v1 prototype submission fee was paid by the ATLAS

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6.6.3 Production SummaryNumber needed on detector 15300

Pre-production 1530Yield factor 0.75

Total number produced 22000

group at University of Science and Technology of China and thus is not included in the cost estimation. Labor costs are estimated based on our past experience to design and test the ATLAS New Small Wheel (NSW) Trigger Data Serializer (TDS) ASIC, which is also a mixed-analog-digital design with similar complexity as the TDC ASIC.

R&D M&S CostsPrior to the construction phase, there are three main activities with the design and tests of a demonstrator prototype, v1 prototype, and v2 prototype. We have successfully designed, fabricated and tested the demonstrator prototype in 2016. This prototype was found to meet the timing resolution and power consumption requirements, however it only includes the triggerless mode. We had the v1 prototype submitted in September 2018 with all functionality included except no TMR for all configuration parameters and clock trees. We also switched to use the TSMC 130 nm CMOS process since multi-project runs for the GlobalFoundries 130 nm CMS process are not available anymore. We plan to have the v2 prototype submitted in August 2019 to fix possible v1 design problems and add TMR protections. For each prototype, we need to package around 40 prototype chips, design and build specific chip test fixtures, perform lab bench tests, radiation tests, and also joint tests with ASD prototypes w/ and w/o MDT chambers at Michigan.

For each prototype, we have costs associated with the design submission, chip packaging, test fixture fabrication and assembly, equipment for lab bench tests, radiation tests and joint tests with ASD prototypes. We need to pay the yearly license fee for the cadence software used for the ASIC design. Prototype run costs are based on quotes from the CERN microelectronics group. Material costs are based upon similar components and test fixtures that we designed for the NSW TDS ASIC. The yearly cadence software license fee is based on the actual vendor quote from cadence.

The prototype submission cost ($35,600 for each prototype submission) can be found in Attachment 1, and the cost of Cadence software annual license fee ($4,500) can be found in Attachment 4. Numbers shown here are direct cost only.

The material task IDs associated are listed below:TDC1117M, 1325M, 1346M, 1495M, 1665M: license fee for the Cadence design softwareTDC1020M, 1030M, 1040M, 1110M: demonstrator ASIC test fixture fabrication/assembly, lab and radiation testsTDC1270M, 1280M, 1290M, 1310M, 1320M, 1330M: v1 prototype ASIC packaging, test fixture fabrication/assembly, lab and radiation tests, joint test with ASDTDC1420M, 1470M, 1480M, 1490M, 1510M, 1520M: v2 prototype ASIC submission, packaging, test fixture fabrication/assembly, lab tests, joint test with ASD

Production M&S CostsWe plan to have a pre-production of 10% of ASICs prior to the PRR. These ASICs will be used to test the newly-built sMDT chambers. Based on the calculation using the program at https://anysilicon.com/die-per-wafer-calculator/, 25 wafers will provide enough TDC dies. Since the minimum number of production wafers we can order from TSMC is 25, we will purchase 25 additional wafers for the final production run. For the QA/QC tests, we need to purchase several sockets to hold chips for mass QA/QC tests. In addition we need to have a DAQ system to collect data and a QA/QC database to record all test results. The NRE cost is applied only once for the pre-production and production runs. NRE and wafer costs are based on quotes from the CERN microelectronics group.

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Material costs for automatic test fixtures are based on similar test fixtures we designed for the NSW TDS ASIC. The cadence software license fee is based on the actual vendor quote.

The quotes for pre-/production NRE and wafers can be found in Attachment 1. Since wafers are purchased in 25 wafer lots, 25 additional wafers are assumed. The total cost (TDC1610M) is listed below:

The cost for the ASIC packaging (22k ASICs in total with $9.8 per ASIC) is split into 2.2k for the pre-production run and 19.8k for the production run. For each run, we need to pay the NRE setup fee ($7500 per setup). The quotes for the packaging and setup costs can be found in Attachment 2. The costs for the packaging of pre-production (TDC1680M) and production (TDC1760M) chips are listed below:

For the QA/QC tests of pre-production and production chips, we plan to have six test fixtures running in parallel, the overall cost is estimated to be $27.1k. This cost also takes into account the purchase of chip sockets, torque drivers, computers, SN labels and a camera/scanner for QA/QC. They are separated into TDC1660M ($2.5k for board production+$1.2k for the assembly of three boards+3×$1.5k for three FPGAs+$800 for other components+$1k for SN labels+$4.5k for computers+$5k for chip sockets and torques=$19.6k), TDC1740M ($1.2k for the assembly of three boards+3×$1.5k for three FPGAs+$800 for other components=$6.5k) and TDC1750M ($1k for purchase of a barcode scanner and cables). Chips will be shipped in four batches to mezz card construction sites, a shipping fee of $200 is assumed for each batch.

The material task IDs associated are listed below:TDC1610M: pre-production submission cost and additional wafersTDC1660M, 1740M, 1750M: pre-production and production chip test fixture fabrication/assembly and automatic testing system for QA/QCTDC1680M, 1760M: packaging for pre-production and production chipsTDC1700M: pre-production chip lab testsTDC1730M, 1767M: QA/QC databaseTDC1775M, 1785, 1795M, 1810M: shipping tested chips to mezz card production sites

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Pre-production and production NRE and wafer cost (TDC1610M)NRE cost for production of the full mask $245,276

25 production wafers 25*$1368=$34,200Total $279,476

Pre-production package and setup cost (TDC1680M)Package cost for 2.2k chips 2200*$9.8=$21,560

Setup fee $7500=$7,500Total $29,060

Production package and setup cost (TDC1760M)Package cost for 19.8k chips 19800*$9.8=$194,040

Setup fee $7500=$7,500Total $201,540

Labor CostsThe TDC ASIC is a mixed analog-digital design with similar complexity as the NSW TDS ASIC designed by the same electronics engineer at Michigan. The NSW TDS has a silicon area of 5.2 × 5.2 mm2 and more than 3 million transistors. We need to perform design, simulation, floor-plan, and post-layout simulation for both prototype and production runs. We also have to work with a packaging company to design chip packaging. A special printed circuit board needs to be designed to test the chip functionality and its performance must be studied. Relevant firmware is also needed for a DAQ system to read out data from the test fixture. Different firmware and DAQ systems are also needed for radiation tests and joint tests with the ASD prototypes with and without MDT chambers. To test the final 22k TDCs, we need to design an automatic chip test fixture and develop relevant firmware. We also need to design and run a QA/QC database to store test results for all ASICs.

We have performed the above work for the NSW TDS ASIC in the past few years and have gained experience with the ASIC design, fabrication and tests at Michigan. The TDC labor cost estimation is based on our past experience on the TDS design. The labor resources consist of one engineer, a technician and engineering student(s). The engineer will focus on the overall system design, simulation and tests for two prototype runs, pre-production and final production runs, database and QA/QC for all chips. The technician will focus on the ASIC simulation, the design of test fixtures, development of firmware and readout system for test fixtures, and QA/QC tests. The engineering student(s) will help with test fixture firmware development and readout system but focus more on prototype testing and production QA/QC.

The total FTE for the TDS design/fabrication/test is 9 (6.3 postdoc-level engineer, 2.7 student) and the total labor cost is $1M. The total FTE for the TDC design/fabrication/test is 11.07 (3.77 senior engineer, 2.87 technicians, and 4.43 students) and the total labor cost is $1.2M. Compared to the labor costs for the TDS ASICs, the salaries for engineer/technician/student have increased, and we also need to have more students to perform QA/QC tests for 22k TDC ASICs (compared to 6k TDS ASICs).

Uncosted LaborA graduate student and a postdoc will spend some fractions of their time at the beginning of the project to study MDT hit rates and radiation tolerance, and later assist the final automatic test fixture design and chip QA/QC tests. The overall uncosted labor contribution is 1.17 FTE.

Travel CostsTwo domestic trips (TDC1100T and TDC1320T) are required for TDC prototype irradiation tests. Each test will take one week and the average cost per day is estimated to be $200 including hotel, car and per diem. The difference for the two cost estimations ($2300 for TDC1100T and $1900 for TDC1320T) is due to the cost for airline tickets to Los Alamos and Brookhaven. These costs do not include overhead.

Four trips to CERN (TDC1080T, TDC1350T, TDC1370T and TDC1560T) are required for the engineer to discuss the design and attend reviews for the demonstrator, two prototypes and final production (separate to pre-MREFC and MREFC). The cost for the first three trips (TDC1080T, TDC1350T, and TDC1370T) is estimated based on our recent trips to CERN: $1500 (flight) +7($60 (hostel) +$50 (per diem)) +$30 (local transportation) = $2300. It is assumed that the engineer will stay three more days for the last trip to finalize the design and prepare for the final production run, the cost for TDC1560T is thus estimated to be $2600. One trip to MPI (TDC1330T) is required for the engineer to learn how to use the ASD chips so that we can test ASD and TDC ASICs together at Michigan. The cost is similar to the

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CERN trip, but only four days are assumed for this trip, the cost is $1500 (flight) +4($50 (hostel) +$50 (per diem)) = $1900. These costs do not include overhead.

We only have one trip to CERN (TDC1560T) arranged during the MREFC period, other trips are all for the pre-MREFC period.

Assumptions: We assume the TSMC 130 nm CMOS process will be used for the final production. We assume two prototype runs are needed to meet the final design specifications.

Schedule:

Dates Development Phase Description

Oct 2016 - Oct 2017 Task Group 01Demonstrator TDC Design, fabrication and tests of the demonstrator.

Oct 2017 – Mar 2019 Task Group 02Prototype v1 Design, fabrication and tests of the v1 prototype.

Apr 2019 - Mar 2020 Task Group 03Prototype v2 Design, fabrication and tests of the v2 prototype.

Apr 2020 - May 2021 Task Group 04Pre-production Fabrication and tests of the pre-produced chips.

May 2021 – Oct 2022 Task Group 05Production and QA/QC

Fabrication and QA/QC tests of all production chips.

Risk Analysis: See Risk Register

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Summary Charts of Maturity and Estimate Type: The cost estimating method is attached below.

Definition of Maturity Categories:Material CategoriesM1: The item is complete or order placedM2: The item has a recent (<1 year) budgetary quote based on a nearly complete design of COTS componentsM3: The item has a recent (<1 year) budgetary quote based on a nearly complete design but there is only one vendorM4: The item has a detailed but not complete design with only minor modification expectedM5: The item has a detailed conceptual design but extensive modifications are likelyM6: The item has unproven fabrication yields and has unique issuesM7: The item does not have a conceptual design yet

Labor CategoriesL0: Project Management Level of EffortL1: The task is completeL2: The task is very similar to one done before with documented durationsL3: The task is conventional, well defined and repeatable (e.g. testing, design of test boards)L4: The task is not completely defined but analogous to past, similar activitiesL5: The task is not well defined

Travel CategoriesPage 7 of 14

T1: Travel contingency

Comments:

The Michigan group has extensive experience in the design, fabrication, test and operation of detectors and frontend electronics for the ATLAS muon spectrometer. We built 80 Big Wheel MDT chambers, and designed and fabricated the present MDT CSM boards. We played a leading role in the integration of all MDTs into the whole ATLAS detector and are currently responsible for daily operations of the MDT detector and front-end electronics. We have successfully designed, fabricated and tested 6000 TDS (trigger data serializer) ASIC for the ATLAS Phase-I upgrade. The TDS ASIC and the TDC ASIC have similar complexity. We have the design and simulation tools and software license setup properly. We also have a computer cluster dedicated for ASIC simulations. We have an MDT test chamber with relevant electronics running at Ann Arbor that allows us to test the TDC that we plan to build. We proposed and have been intensively studying the triggerless mode with simulations and with the current MDT setup in our lab. Michigan is also responsible for building 48 sMDT chambers and all CSM boards for the HL-LHC upgrade.

The main challenges for the MDT TDC design are to meet timing, input and output data rates, radiation-tolerant, power consumption and cost requirements. The MDT detector will be used for the first time at the first-trigger level. The default mode of the TDC is to run in the triggerless mode that sends all hits to the CSM and onto USA-15. In USA-15 the trigger match would be performed providing modest precision data for coincidence with TGCs or RPCs. However, the new TDC will also have the triggered mode implemented for the chamber and test beam studies. The new TDC will run with higher clock frequency and has additional functions to suppress low ADC noise and handle noise burst. The ASIC configuration, clock trees and logics have to be designed carefully to avoid SEE and run properly at 71034 cm-2s-1. Since there are no water-cooling system for the MDT front-end electronics, the TDC power consumption has to be low even though the input data rate has increased significantly and all hits recorded need to be sent to CSM. Most of the specifications for the new TDC are similar to the current AMT (ATLAS Muon TDC).

We have designed a demonstrator TDC ASIC using the GlobalFoundries 130 nm CMOS process. The purpose of this demonstrator was to develop and validate the overall design architecture. Detailed studies indicate that it meets the time resolution and power consumption requirements. We also designed the v1 prototype with all needed features included except the TMR protections for all configuration parameters and clock trees. The layout of the v1 prototype is shown on the left plot of Figure 1 and the test fixture board with a packaged v1 ASIC mounted is shown on the right plot of Figure 1. This prototype used the TSMC 130 nm CMOS process.

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Figure 1: Layout of the TDC v1 prototype and the test fixture board with a packaged v1 TDC ASIC

mounted in the middle.

Attachment 1: Prototype and production MOSIS submission and additional wafer costsThe full mask set NRE cost of $245,276 and 25 engineering wafer cost of $1,368 per wafer are used.

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Attachment 2: Packaging cost

We assume that the NRE cost to setup the package tools $7.5k is needed for both pre-production and final production runs, and the packaging unit price is $9.8.

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Attachment 3: Prototype and production test fixture cost

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Attachment 4: Cost for cadence software license at Michigan

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