Incentia Test Synthesis Solution TestCraft - ednc.com · Incentia Test Synthesis Solution TestCraft...

1incentia

Incentia Test Synthesis Solution

TestCraft

Incentia Test Synthesis SolutionIncentia Test Synthesis Solution

TestCraftTestCraft

Incentia Design Systems, Inc.

October, 2010

2incentia Confidential

Company Introduction

� Mission: SoC nanometer timing and synthesis technology leader

� Channels

Distributors:

Japan (Marubeni), India (ICON),

China (OnePass Solutions),

Korea (ED&C), Israel (AST)

Direct Offices:

USA: Silicon Valley

Southern California

Taiwan: Hsinchu


Incentia Product Offering

� Logic, Low Power, DFT Synthesis solution

DesignCraft, PowerCraft, TestCraft

� Timing analysis solution

TimeCraft: World fastest Static Timing Analyzer (STA)

TimeCraft-LOCV: Location Based OCV

TimeCraft-SSTA: Statistical STA

TimeCraft-SI: Signal Integrity

TimeCrfaft-PCA: Power Analysis

ConstraintCraft: Constraint Management

� Design closure solution

ECOCraft-Timing: Hold-time & Setup-time ECO

ECOCraft-Power: Leakage power ECO


How Incentia Products Fit into Design Flow

DesignCraft(Logic, DFT, Low Power Synthesis)

Complete Timing Analysis

- TimeCraft (Static Timing Analysis)

- TimeCraft–LOCV (90, 65, 45 nm)

- TimeCraft–SSTA (45, 30nm)

- TimeCraft–SI (Signal Integrity Analysis)

- TimeCraft-PCA (Power Analysis)

- ConstraintCraft (Constraint Mgmt, Validation)

Placement & Route

Netlist

Delay Calculation

Timing, Power

Analysis

RC Extraction

Netlist, DEF/GDSII

Netlist, SPEF

RTL

Logic Synthesis

Hold-Time, Power

ECO

Meet Constraints?

No

IC Design Flow Incentia Products

Design Closure

- ECOCraft-Timing (Hold-time & Setup=time ECO)

- ECOCraft-Power (Leakage Power ECO)

YesOK


TestCraft Key Features

�One pass logic and DFT synthesis

�Top-down or bottom-up design methodology

�Scan cell replacement

�DFT rule checking

�Automatic fixing of DFT rule violations

�Scan chain ordering, stitching, balancing

�Smooth integration to Incentia low power solution

�Smooth interface to 3rd-party ATPG tools: STIL format

Mentor (FastScan), Synopsys (TetraMax), SynTest(TurboScan)

�Shorter downstream ATPG runtime

More DFT violations can be fixed during DFT synthesis


Typical DFT Flow (RTL or Netlist Input)

Load SDC constraints

set_scan_implementation

set_dft_rule_option

set_scan_port, set_scan_route

set_scan_cell_connect_style

check_design

check_dft_rule

set_scan_implementation -stitch false

implement_scan

pre_show_dft

set_scan_implementation -stitch true

implement_scan

report_dft

compile_lib, read_design, link_design

make_unique, set target_lib

optimize –scan (for RTL input)

write_design

write_dft_interface

Import Data (Design, Library)

Generate Outputs

Set Design Constraints

Define Scan Chain Architecture

Analyze Design for DFT

Pre-show Scan Chains

Perform Scan Optimization

No

Yes

Result OK?

Stitch Scan Chains

Report Scan Info

No

Yes

Result OK?


Fastest Runtime: STA-based Technology

� Fastest run time: up to 10X faster than any other solutions!

Key technology: STA based static analysis(vs. event driven approach used in other tools)

Bigger designs show bigger speedup

clk_gen

test_gen

DFTdft_tm test_mode_port

top_design

PA3PA4

PA5PA6

clock_port

create_dft_clock

create_clock

CLK

scan_enable_port

PA2

dft_se


Efficient Scan Cell Replacement

�Scan cell replacement

Preserve timing quality of pre-DFT design

clk

scan_in

d

q

scan_enable

d

clk

q / scan_out1

0

SDFFX2

DFFX6

clk

scan_in

d

scan_enable

q / scan_out1

0

SDFFX6

�

�


Scan Chain Planning

�Rich controls in scan chain ordering & stitching

Number of scan chains

Chain length

Balanced chaining

Chaining styles

• Chain with distinctive clock domain: (R1), (R2), (R3)

• Chain with merged clocks: (R1, R2, R3)

• Chain with merged edges: (R1), (R2, R3)

• Chain with merged clocks but not edges: (R1, R2), (R3)

Lock-up latch insertion to avoid timing issues

• Automatic & user-control

clk1 clk2 clk2R1 R2 R3


Scan Chaining: Example

� Chain by distinctive

clock domain

dft_so1

dft_si3 dft_so2

dft_so3

si so

d

clk1dff1

si so

d

clk1dff2

Inst1

si so

d

clk2dff2

Inst3

si so

d

clk2dff1

dft_si1

dft_si2

Top

si so

d

clk1dff1

Inst2

� Chain by merged clocks

si so

d

clk1dff1

si so

d

clk1dff2

Inst1

si so

d

clk2dff2

Inst3

si so

d

clk2dff1

dft_si

dft_so

Top

si so

d

clk1dff1

si so

clk1lat

Inst2

Inserted lock-up latch


Clock Tree Based Scan Chaining

�Clock tree based scan ordering and chaining

Clock tree grouping and ordering

Example: buf1 group first, following by buf2, and buf3 groups

Top

si so

ddff1

si so

ddff2

Inst1

si so

ddff2

Inst3

si so

d

si so

ddff1

si so

Inst2

buf1

buf2

buf3

dff1

dff2

CLK

dft_sodft_sisi so

ddff1

si so

ddff2

Inst1

si so

ddff2

Inst3

si so

d

dft_si

dft_so

Top

si so

ddff1

si so

Inst2

buf1

buf2

buf3

dff1

dff2

CLK

Clock tree information is given { buf1/o,

buf2/o, buf3/o} to guide scan chaining

One possible result if clock tree

information is not considered


Scan Chain Re-chaining

�Scan chain re-chained

Re-balance scan chains on existing scan chains

si sosdff

Scan Section

dft_si1

dft_si2 dft_so1

dft_so2

si sosdff

si sosdff

si sosdff

Scan Section

dft_si1dft_so1

dft_si2 dft_so2si sosdff

si sosdff

si sosdff

si sosdff


DFT Rule Checking & Fixing

�DFT rule violations will cause

Shorter or incorrect scan chains

Lower fault coverage or failure in later ATPG

�Checking of over 25 rule violations

Clock, latch, asynchronous signals, gated clock, tri-state bus, bi-direction port, etc.

�Automatic fixing of over 15 rule violations

MUX-style, disable-style

�Fastest runtime for checking & fixing

Unique patented STA-bases approach


Automatic Fixing of DFT Rule Violations

�DFT Violation Fixing (MUX-Style)

Uncontrollable, Gated, Generated Clock Violation Fixing

Uncontrollable Asynchronous Set/Reset Violation Fixing

1

0

qd

clk

en

1’b0

1

0

dft_fix_async

dft_fix_clk

si

dft_tm

qd

clk

en

1’b0


Automatic Fixing of DFT Rule Violations (Cont)

�DFT Violation Fixing (Disable-Style)

Uncontrollable, Gated, Generated Clock Violation Fixing

Uncontrollable Asynchronous Set/Reset Violation Fixing

qd

clk

en

1’b0

qd

1’b0

si

clk

en

dft_tm

dft_tm



�Same Clock Source Fixing

This fixing can help to reduce buffer insertion by clock tree synthesis.

clk

en0

1

clk

en 0

1dft_fix_clk

Default Fixing CTS Specific Fixing


�Cross Hierarchy Fixing

Reduce the logic count, thus reduce area

FIX VIOLATION

FIX VIOLATION

VIOLATION

VIOLATION

FIX



Testability Estimation

� Testability estimator before ATPG

� Test Point Insertion & Testability Report

Insert test point to hard observe or control point

Report hard to observe or control point

HARD TO

OBSERVE/CONTROL

LOGICS

CONTROL OBSERVE

CONTROLLABILITY

reg1/SON234

Top_in1N32

reg2/SON3405

Terminal Pin

(Starting pt)Net

Level of

Logics

OBSERVABILITY

reg6/CKN4024

Top_out6N21

reg7/DN557

Terminal Pin

(Ending pt)Net

Level of

Logics


Test Point Insertion

� Insert test points at hard to control or observe locations

Main Function

Block

Input Output

d q

obs

dft_fix_clock

si

dft_fix_clock

Main Function

Block

Input

Output

d q

(so)

ctrl

dft_tm

1’b01

0

Inserting control test point

=> A Reg & a MUX are added

Inserting observe test point

=> A MUX is added


Observation Test Point Compression

�Compress multiple observation test points into one test point logic to reduce the logic

Can control # of compressed points

Example: compress obs1, obs2, obs3 into 1 test point logic

test_mode

obs1

D Q

>CK

obsreg

obs3

obs2

Observability Logic

Function Block

test_clk

Output

TD

Scan Chain scan_enable


Sharing Control & Observe Test Point

�Control & observe logic at the same point can be shared

�Example: NET1 is hard to control & observe

Function Block

A

Input NET1

d q

obs

dft_fix_clock

si

dft_fix_clock

Function Block

B

NET1

Output

d q

(so)

ctrl

dft_tm

1’b01

0

dft_fix_clock

Function Block

B

NET1

Output

d q

(so)

ctrl

dft_tm

1

0

Function Block

A

Input


Bypass Logic

�Adding bypass logic for memory blocks or black boxes

Insert observable and/or controllable logics to increase testability

test_mode

SFF_CTRL

READ

WRITE

CLK

x

y

0

1

1’b0SFF_OBS

For Controllability

For Observability

Din_1

.

.

Din_n

Dout_1

.

.

Dout_n

QD

SI

SE SO

QD

SI

SE SO


Seamless DFT and Low Power Integration

�Smooth DFT & low power integration

Automatic DFT insertion for clock gating in Incentia environment

test_mode

obs1

D Q

EN

latch

D Q

>CK

obsreg

obs3

obs2

gated_clk

select

top_clk

Observability Logic

Clock Gating Logic


Multiple Supply Voltages

1.2v0.8v

1.0v

Auto Level Shifter insertion

Auto Level Shifter insertion

… …scan_in scan_out

si so

si so

si so

�DFT for multiple supply voltages

Automatic level shifter insertion when chaining registers from different voltage domains

Scan chain order by voltages


Enhancement for Low Power

�CPF interface support

�Auto library reading and target library link when

sourcing CPF script

�Control of scan-chain crossing voltage domain

�Level-shifter Insertion control of scan-chain crossing voltage domain.

�Level shifter covering IO port and special voltage domain through IO of certain IP

�Support multi-bit scan cell to further reduce area/power


TestCraft Runtime Data

� Perform DFT rule checking, fixing, chaining, and reporting

� Runs 2x to 8x faster than others

0

1

2

3

4

5

6

7

8

Design1 Design2 Design3 Design4

TestCraft

Competitor

6.2M logic instances; 65nmDesign4



1.4M logic instances, 90nmDesign1

Runtime speedup ratio


Summary

� Complete integrated synthesis solution

Logic, Low Power, DFT

� Very fast runtime with big capacity

2X to 5X faster than other solutions!

� Most aggressive reduction in chip area and power consumption

Up to 30% less synthesized gate counts

Up to 20% less power

� Many customer tape-outs in different applications

Communication, networking, wireless, consumer electronics, multi-media, graphics

Easy to adopt

Incentia Test Synthesis Solution TestCraft - ednc.com · Incentia Test Synthesis Solution TestCraft...

Documents

Transcript of Incentia Test Synthesis Solution TestCraft - ednc.com · Incentia Test Synthesis Solution TestCraft...