In Association with: ISSUE 42 – July 2012 · Director of Technology Strategy for Intel...

In Association with: ISSUE 42 – July 2012 – www.future-fab.com

Accelerating the next technology revolution.

http://www.future-fab.com

http://www.smta.org/

http://english.ime.cas.cn/

http://www.fraunhofer.de/en/about-fraunhofer/

http://www.accellera.org

http://www.sematech.org

http://www.si2.org

http://www.imec.be

http://www.sia-online.org

http://www.gsaglobal.org

http://www.cnse.albany.edu

http://www.itrs.net

http://www-leti.cea.fr/en

FUTURE FAB International | Issue 42

Welcome …

…to this answer to “Life the Universe and Everything”issue of Future Fab,* where we’re again attempting theimpossible and achieving the improbable. In such a fast-moving and insanely technical field as that which we inhabit, getting CEOs to write is tough ... let alone gettingthree! We continue our 20/20 Visions quest to give youinsight into the mindset of the industry’s leadership, with Luc Van den hove (CEO – imec) and Dan Armbrust(CEO – SEMATECH) each writing a vision, and David Lam(yes – David “Lam Research” Lam) writing about the re-emergence of E-Beam Litho onto the scene, as EUV’s coststructure cannot be supported by anything but mass-pro-duced devices.

Elsewhere in the issue, we have lots of content from our partner base, featuring articles from imec, FraunhoferCNT/ENAS/IISB, Leti and Si2. We’re continuing to expandour international cooperations with organizations of thistype in order to continue bringing you the future of fabrication.

If you as a reader think there is an organization we arenot currently partnering with but should, give us a holler at [email protected].

For now, enjoy the issue, and thank you for the contin-ued support!

The Future Fab Team

*If you don’t get the reference, you should be ashamed tocall yourself a geek! Sigh ... OK, look at this:http://en.wikipedia.org/wiki/Phrases_from_The_Hitchhiker%27s_Guide_to_the_Galaxy#Answer_to_the_Ultimate_Question_of_Life.2C_the_Universe.2C_and_Everything_.2842.29

mailto:[email protected]

http://en.wikipedia.org/wiki/Phrases_from_The_Hitchhiker%27s_Guide_to_the_Galaxy#Answer_to_the_Ultimate_Question_of_Life.2C_the_Universe.2C_and_Everything_.2842.29

http://www.future-fab.com/?swag42ad

2 | FUTURE FAB International | Issue 42

CONTENTS | FUTURE FAB International | Issue 42

FUTURE VISIONS & CURRENT CONCERNS

12 IntroductionPushkar P. Apte – Pravishyati Inc.

13 Tackling the Growing Complexityand Challenges ThroughWorldwide Open InnovationLuc Van Den Hove – imec

17 Thought Leadership ProfileTotal Facility Solutions

20 Fast-Forward 2020: Envisioningthe Next Decade in TechnologyR&DDan Armbrust – SEMATECH

NEW TECHNOLOGIES & DEVICE STRUCTURES

24 IntroductionJohn Schmitz – NXP Semiconductors

25 Silicon Photonic RevolutionThrough Advanced IntegrationAleksander Biberman –Massachusetts Institute of Technology

DESIGN IMPLEMENTATION &PROCESS INTEGRATION

29 IntroductionPeter Rabin – SanDisk Corp.

30 The Economic Case forDesign/Foundry StandardsSteven E. Schulz – Si2

MANUFACTURING: FAB, SYSTEMS & SOFTWARE

36 IntroductionGiuseppe Fazio – MicronSemiconductors

37 Wait Time Waste (WTW) Metrics,Methodology and Support ToolsJackie Ferrell,1 Les Marshall,2 ChrisCartier,3 Jonathan Matthews,4 ToyshaWalker,5 Alan Weber,6 Lance Rist7 – 1ISMI/SEMATECH 2GLOBALFOUNDRIES3IBM Microelectronics 4Intel 5MicronTechnology 6Cimetrix Inc. 7SeniorIndustry Consultant

LITHOGRAPHY LANDSCAPE

45 IntroductionYayi Wei – GLOBALFOUNDRIES

46 Thought Leadership ProfileNikon

50 E-Beam Direct Write on 300 mmWafers: Maskless Patterning forVarious ApplicationsChristoph Hohle – Fraunhofer-CenterNanoelectronic Technologies

55 E-Beam Lithography RevisitedDavid K. Lam – Multibeam Corporation

62 Practical Implementation of SMOin a Production ScannerTomoyuki Matsuyama,1 MartinMcCallum,2 Holly H. Magoon3 – 1NikonCorporation 2Nikon Precision Europe3Nikon Precision Inc.

Next generation lithography techniques continue to evolve, but IC makers need solutions

today that will keep them on their aggressive technology roadmaps. In order to maintain

production timelines, extension of ArF lithography is vital. To meet this challenge,

Nikon developed two new 193 nm scanners—the latest evolutions of the proven

Streamlign platform, which is already adopted in leading-edge facilities worldwide.

The Nikon NSR-S621D immersion and NSR-S320F dry scanners satisfy the increasingly

demanding requirements for imaging, overlay accuracy, and ultra-high productivity that

are essential for cost-effective 22 nm applications and beyond.

Nikon. Evolution in Action. www.nikonprecision.com

http://www.nikonprecision.com

http://www.future-fab.com/?nikon42ad


CONTENTS | FUTURE FAB International | Issue 42

FRONT END OF LINE

69 IntroductionYannick LeTiec – CEA-Leti

70 Section SponsorHitachi

72 UTBB SOI: A Wolf in Sheep’sClothingThomas Skotnicki,1 Franck Arnaud,1

Olivier Faynot2 – 1STMicroelectronics,Crolles, France 2CEA-Leti, Grenoble,France

80 FOUPs Polymers Against AMCs:The HF CasePaola González-Aguirre,1,2 HervéFontaine,1 Carlos Beitia,1 Jim Ohlsen,2

Jorgen Lundgren2 – 1CEA-Leti,MINATEC Campus 2Entegris Inc.,France

85 Thought Leadership ProfileCyberOptics Semiconductor

BACK END OF LINE

88 IntroductionJon Candelaria – SRC

89 The Bigger Picture: FraunhoferCNT’s BEOL Applied ResearchBenjamin Uhlig, Lukas Gerlich, Romy Liske – Fraunhofer CenterNanoelectronic Technologies

94 A Low-Damage PatterningScheme for Ultra-Low-kDielectricsS. Zimmermann,1 N. Ahner,2 T. Fischer,2

T. Oszinda,3 B. Uhlig,4 S.E. Schulz,1,2

T. Gessner,1,2 – 1Fraunhofer ENAS2Chemnitz University of Technology3GlobalFoundries 4Fraunhofer CNT

METROLOGY, INSPECTION & FAILURE ANALYSIS

102 IntroductionDavide Lodi – Micron Semiconductors

103 Predictive Sampling for DefectDensity Control OperationsM. Pfeffer,1 R. Oechsner,1 L.Pfitzner,1

S. Eckert,2 A. Hartmann,2 H. Gold,3

G. Biebl,4 J. Kaspar4 – 1Fraunhofer IISB2Infineon Technologies 3InfineonTechnologies 4Infineon Technologies

ASSEMBLY, TEST & PACKAGING TECHNOLOGIES

111 IntroductionSteven Greathouse – Plexus Corp

112 Interconnect Test for Wide-IOMemory-on-Logic StacksE.J. Marinissen,1 S.K. Goel,2 A.B. Mehta,2

F. Lee,2 Sergej Deutsch,3 B. Keller,3 V.Chickermane,3 S. Mukherjee,3 N. Sood3

– 1imec 2TSMC 3Cadence DesignSystems

118 Thermal Laser Separation and ItsApplicationsDirk Lewke,1 Matthias Koitzsch,1 MartinSchellenberger,1 Lothar Pfitzner,1 HeinerRyssel,1 Hans-Ulrich Zühlke2 –1Fraunhofer Institute for IntegratedSystems and Device Technology IISB2JENOPTIK AutomatisierungstechnikGmbH

123 Advertisers Index

5www.future-fab.com |

EDITORIAL PANEL

Paolo A. GarginiDirector of Technology Strategy for Intel Corporation

Dr. Paolo Gargini is also responsible for worldwide research activities conducted outside Intel forthe Technology and Manufacturing Group by consortia, institutes and universities. He received doctorates in electrical engineering and physics from the Universita di Bologna, Italy.

Biographies of Future Fab's Panel MembersFor the full versions of the following biographies, please click here.

Mark McClearGlobal Director, Applications Engineering, Cree LED Components

Mark McClear is responsible for LED lighting applications development and Cree’s ApplicationEngineering Technology centers worldwide. He holds a B.S. in electrical engineering from MichiganState University and an MBA from Babson College, and has 11 issued and published U.S. patents inelectronics, LED and solid state lighting.

Michel BrillouëtSenior Adviser, CEA-Leti

Michel Brillouët joined CEA-Leti in 1999, where he managed the silicon R&D. Prior to joining CEA-Leti, he worked for 23 years in the Centre National des Télécommunications (France Telecom R&DCenter), where he held different positions in micro-electronics research. He graduated from ÉcolePolytechnique.

Alain E. KaloyerosSenior Vice President, CEO and Professor, College of Nanoscale Science and Engineering; University at Albany

Alain E. Kaloyeros has authored/co-authored over 150 articles and contributed to eight books onnanoscience, holds 13 U.S. patents, and has won numerous academic awards. He received his Ph.D.in experimental condensed matter physics from the University of Illinois, Urbana-Champaign, in 1987.

Gilbert J. DeclerckExecutive Officer, imec; Member of the Board of Directors, imec International

Gilbert J. Declerck received his Ph.D. in electrical engineering from the University of Leuven in1972. He has authored/co-authored over 200 papers and conference contributions. In 1993, he waselected fellow of the IEEE. Since July 1, 2009, Dr. Declerck has been executive officer imec and amember of the board of directors of imec International.

Didier LouisCorporate and International Communication Manager, CEA-Leti

Louis joined CEA-Leti (France) in 1985, where he received a Ph.D. in metallurgy/electrochemistryfrom the University of Grenoble. He has written more than 30 papers related to etching and strip-ping processing and has co-authored more than 60 scientific papers and eight patents.

http://www.future-fab.com/editorial.asp

6 | FUTURE FAB International | Issue 42 7www.future-fab.com |

EDITORIAL PANEL | FUTURE FAB International | Issue 42

Shishpal RawatChair, AccelleraDirector, Business-Enabling Programs; Intel Corp.

Shishpal Rawat holds M.S. and Ph.D. degrees in computer science from Pennsylvania StateUniversity, University Park, and a B. Tech. degree in electrical engineering from the Indian Instituteof Technology, Kanpur, India.

Jon CandelariaDirector, Interconnect and Packaging Sciences; SRC

Jon Candelaria has over 34 years’ experience in the electronics industry in a wide variety of engi-neering and managerial roles. He received his BSEE and MSEE from the University of New Mexico.

Yannick Le TiecTechnical Expert, CEA-Leti, MINATEC Campus

Yannick Le Tiec joined CEA-Leti in 1995 and received his Ph.D. in materials science and engineeringfrom the Polytechnic Institute, Grenoble, France, and his M.S. in chemistry from the National Schoolof Chemistry, Montpellier, France. He is a CEA-Leti assignee at IBM, Albany (NY), developing theadvanced 22 nm CMOS node and the FDSOI technology.

Alain C. DieboldEmpire Innovation Professor of Nanoscale Science; Executive Director,Center for Nanoscale Metrology, CNSE, University at Albany

Alain’s research focuses on the impact of nanoscale dimensions on the physical properties ofmaterials. He also works in the area of nanoelectronics metrology. Alain is an AVS Fellow and asenior member of IEEE.

Thomas SondermanVice President, Manufacturing Systems Technology; GLOBALFOUNDRIES

Thomas Sonderman obtained a B.S. in chemical engineering from the Missouri University ofScience and Technology in 1986 and an M.S. in electrical engineering from National TechnologicalUniversity in 1991. He is the author of 43 patents and has published numerous articles in the area ofautomated control and manufacturing technology.

Rohan AkolkarSenior Process Engineer, Components Research; Intel Corporation

Dr. Akolkar received the Norman Hackerman Prize of the Electrochemical Society in 2004, andnumerous Intel Logic Technology Development awards. He has authored more than 40 technicalpapers, invited talks, and U.S. patents in the area of electrodeposition.

Christo BojkovSenior Package Development Engineer, TriQuint Semiconductor

Dr. Christo Bojkov has published over 30 publications and holds 15 patents. Since receiving hisdoctorate in chemical engineering, he has worked and taught in academia for over 10 years inphysical chemistry and surface science.

Steve GreathouseGlobal Process Owner for Microelectronics, Plexus Corp.; Idaho

Steve Greathouse has published many articles on technical topics related to semiconductor pack-aging, failure analysis and lead-free packaging. He has a B.S. in electronic physics from WeberState University with advanced studies in material science and computer science.

Daniel J.C. HerrProfessor & Nanoscience Department Chair, JSNN; UNC – Greensboro

Dr. Herr is a pioneer in collaborative nanotechnology research. He is professor and chair of theNanoscience Department at the new Joint School for Nanoscience and Nanoengineering inGreensboro, North Carolina. Until recently, Dr. Herr served as the director of SemiconductorResearch Corporation’s Nanomanufacturing Sciences area. He received his B.A. with honors inchemistry from Wesleyan University in 1976 and his Ph.D. from the University of California at SantaCruz in 1984.

William T. ChenSenior Technical Advisor, ASE (U.S.) Inc.

Bill Chen is the co-chair of the ITRS Assembly and Packaging International Technical WorkingGroup. He was elected a Fellow of IEEE and a Fellow of ASME. He received his B.Sc. at Universityof London, MSc at Brown University and Ph.D. at Cornell University.

Liam MaddenCorporate VP, FPGA Development & Silicon Technology; Xilinx, Inc.

Liam Madden is responsible for foundry technology, computer aided design and advanced pack-age design. He earned a BE from the University College Dublin and an MEng from CornellUniversity. Madden holds five patents in the area of technology and circuit design.

Alan WeberPresident, Alan Weber & Associates

Alan’s consulting company specializes in semiconductor advanced process control, e-diagnosticsand other related manufacturing systems technologies. He has a bachelor’s and a master’s degreein electrical engineering from Rice University.

Yayi WeiPrincipal Member of Technical Staff; GLOBALFOUNDRIES

Dr. Wei investigates advanced lithography processes and materials. He has over 16 years of lithog-raphy experience, including DUV, 193 nm, 157 nm, 193 nm immersion, EUV and E-beam lithography.Dr. Wei has numerous publications and holds several patents in the field of lithography.

David G. SeilerChief, Semiconductor and Dimensional Metrology Division, NIST

David G. Seiler received his Ph.D. and M.S. degrees in physics from Purdue University and his B.S. in physics from Case Western University.



EDITORIAL PANEL | FUTURE FAB International | Issue 42

Giuseppe FazioAdvanced Process & Equipment Control Sr. Engineer; Micron Semiconductors Italy

With a laurea degree in applied physics from Milan University, Giuseppe has working experience inseveral sectors, from research to industry, and vast experience in industrial and scientific instru-mentation. He has authored/co-authored many articles, is an avid contributor at conferences andholds several patents in the semiconductor field.

Peter RabkinDirector of Device & Process Technology, SanDisk Corp.

Dr. Peter Rabkin focuses on development of novel 3D memory technologies and products. Heholds a master’s degree in physics from Tartu University and a Ph.D. in physics of semiconductorsfrom the St. Petersburg Institute of Physics and Technology.

Sitaram R. ArkalgudDirector of Interconnect, SEMATECH

Sitaram R. Arkalgud has over 20 years of R&D and manufacturing experience within the chip indus-try. He has a Ph.D. and a master’s degree in materials engineering from Rensselaer PolytechnicInstitute, and a B.S. in metallurgical engineering from Karnataka Regional Engineering College,Surathkal, India.

Daniel C. EdelsteinIBM Fellow; Manager, BEOL Technology Strategy, IBM T.J. Watson Research Center

Dr. Edelstein played a leadership role in IBM’s industry-first “Cu Chip” technology in 1997, in theintroduction to manufacturing of Cu/Low-k insulation in 2004. He received his B.S., M.S., and Ph.D.degrees in applied physics from Cornell University.

Christian BoitHead, Semiconductor Devices at Berlin University of Technology, Germany

The Berlin University of Technology is an institution for research and development in the areas ofdevice simulation, technology, characterization and reliability. Christian Boit received a diploma inphysics and a Ph.D. in electrical engineering on power devices, then joined Siemens AG’s ResearchLaboratories for Semiconductor Electronics in Munich and has been a pioneer on photoemission.

Pushkar P. AptePresident, Pravishyati Inc.

Dr. Pushkar P. Apte's strategy consulting firm focuses on the high-tech industry. He received hismaster’s and Ph.D. from Stanford University in materials science and electrical engineering, and hisbachelor’s degree in ceramic engineering from the Institute of Technology, Varanasi, India.

Dr. Jiang YanProfessor, IMECAS

Dr. Jiang Yan has authored and co-authored over 30 papers, holds 17 U.S. patents and five Chinapatents. He received his Ph.D. in electrical engineering from the University of Texas at Austin in 1999.

Klaus-Dieter RinnenDirector/Chief Analyst, Dataquest

Klaus-Dieter Rinnen is director for Dataquest’s semiconductor and electronics manufacturinggroup. He received a diploma degree in physics with minors in physical chemistry and mechanicalengineering in Germany, and a Ph.D. in applied physics from Stanford University.

John SchmitzSVP & General Manager, Intellectual Property and Licensing; NXP

John Schmitz holds a master's degree in chemistry from Radboud University of Nijmegen,Netherlands, and a doctorate in physical chemistry from Radboud University Nijmegen. He hasauthored more than 45 papers in various scientific journals and has written books on IC technolo-gy and on thermodynamics.

Lode Lauwers Director Strategic Program Partnerships for Silicon Process & Device Technology, imec

Lode Lauwers has an M.S. in electronics engineering and a Ph.D. in applied sciences. He joinedimec in 1985 as a researcher. Lode manages imec’s core partner research program on sub-32nmCMOS technologies.

Ehrenfried Zschech Division Director for Nanoanalysis & Testing, Fraunhofer Institute forNondestructive Testing; Dresden, Germany

Ehrenfried Zschech received his diploma degree in solid-state physics and his Dr. rer. nat. degreefrom Dresden University of Technology. He has published three books and over 100 papers in scientific journals on solid-state physics and materials science.

Janice M. GoldaDirector, Lithography Capital Equipment Development; Intel Corp.

Janice Golda manages an organization responsible for creating strategies and working with Intel’slithography, mask and metrology suppliers and subsuppliers to deliver equipment meeting Intel’sroadmap technology, capacity and cost requirements. She is a member of the Berkeley CXROAdvisory committee, is Chairman of the Board for the EUV LLC and holds one U.S. patent.

Luigi ColomboTI Fellow

Dr. Luigi Colombo is a TI Fellow working on the Nanoelectronic Research Initiative (NRI). He is author and co-author of over 130 publications, three book chapters, and holds over 60 U.S.patents. Dr. Colombo received his Ph.D. in materials science from the University of Rochester.

Warren SavageChief Executive Officer, IPextreme

Warren Savage has spent his entire career in Silicon Valley, working with leading companies, wherehe focused on building a global scalable semiconductor IP business. In 2004, he founded, and stillleads IPextreme in the mission of unlocking and monetizing captive intellectual property held withinsemiconductor companies and making it available to customers all over the world. He holds a B.S. incomputer engineering from Santa Clara University and an MBA from Pepperdine University.


Published by:Mazik Media Inc.38 Miller Ave., Suite 9Mill Valley, California 94941USA

Tel: 415 381 6800Fax: 415 381 6803

Email: [email protected]

ISSN: 1363-5182

While every effort is made to ensure theaccuracy of the contents of this book,the publisher will accept no responsibilityfor any errors or omissions, or for anyloss or damage, consequential or other-wise, suffered as a result of any materialhere published. The publisher assumesno responsibility for statements made bytheir advertisers in business competition,nor do they assume responsibility forstatements/opinions expressed orimplied in the articles of this publication.

Publisher and CEO . . . . . . | Nikki Wood

Editorial & Digital Projects Director. . . . . . . . | Matt Grimshaw

Art Director . . . . . . . . . . . . | David Witcomb

Editor . . . . . . . . . . . . . . . . . . | Lisa Barr

Marketing Manager . . . . . | Lindsay Poole

Web . . . . . . . . . . . . . . . . . . . | Sara Smith

Production Manager . . . . | Jane Ellis

Future Fab International© 2012 Mazik Media, Inc.The entire contents of this publicationare protected by copyright, fulldetails of which are available from the publisher. All rights reserved.No part of this publication may bereproduced, stored in a retrievalsystem or transmitted in any form or by any means - electronic,mechanical, photocopying, recordingor otherwise - without the priorpermission of the copyright owner.

Click here to return to Table of Contents


Peter RammHead of Device and 3D IntegrationDepartment, Fraunhofer EMFT; Munich

Peter Ramm received his physics and Dr. rer. nat.degrees from the University of Regensburg. He hasauthored or co-authored over 100 publications, includ-ing three book chapters and 23 patents.

Davide Lodi Baseline Defectivity & MetrologyEngineering Manager; MicronSemiconductors Italy

After graduating in physics from the University ofMilan, Davide Lodi started working in 1997 forSTMicroelec-tronics as a process engineer. Afterbecoming the manager of Wet Processes andMetrology Engineer-ing at the NVM R&D Agrate site,he moved to Numonyx, which was acquired byMicron in 2010.

Stephen J. Buffat Staff Research Scientist, Lockheed Martin NanoSystems

Stephen Buffat is responsible for the startup andoperation of Lockheed Martin’s nanotechnology facili-ty and operation in Springfield, Mo. He has authoredor co-authored numerous articles on photolithogra-phy, etch and 300 mm surface preparation processtechnologies.

Steven E. SchulzPresident and CEO, Silicon Integration Initiative, Inc.

Since 2002, Steve Schulz has served as presidentand CEO of Si2, the leading worldwide consortiumof semiconductor and software companies charteredto develop EDA standards. He has a B.S. in electricalengineering from the University of Maryland atCollege Park, and an MBA from the University ofTexas at Dallas.


http://www.linkedin.com/groupRegistration?gid=1839140&csrfToken=ajax%3A4952622841895939617

FUTURE VISIONS & CURRENT CONCERNSClick here to return to Table of Contents

Powered by the engine of semicon-ductor chips, technology and elec-tronics are embedded in almost everyaspect of life in the 21st century. Theglobal semiconductor industry is nowworth ~$300 billion, and supports theeven-larger ~$1.2 trillion electronic sys-tems industry. Two disruptive transi-tions – the advent of nanotechnologyand the rise of the global consumer asthe main end-user – are reshaping theindustry.

First, the Moore’s Law mantra ofmaking things “cheaper, better, fasterand smaller” has driven us into therealm of nanotechnology, where wemust manipulate just a few atoms anddeal with complex quantum effects. Thisrequires several innovations such as newmaterials, new 3D device structures tominimize power consumption, extreme-ultra-violet (EUV) patterning to fabri-cate these tiny devices, and a larger(450 mm) wafer size to reduce cost.

Second, several hundred million peo-ple, particularly from emerging coun-tries, have recently joined the globaleconomy as consumers of high-techproducts. This has created both a chal-lenge and an opportunity for semicon-ductor companies to expand beyond

Pushkar P. AptePresident, Pravishyati Inc.

the traditional domains of computing,communication and entertainment, anddevelop solutions for these new con-sumers in diverse fields such as energy,transportation and health care. Somesolutions require better digital perform-ance, while others require “More-than-Moore” functionality such as biologicalsensors, better analog and powerdevices, and so forth.

Addressing these transitions impos-es a heavy burden – it requires largeinvestments, and the entire supplychain to work together in harmony. Thisis difficult for any single company toachieve unilaterally. So it is critical forcompanies to partition this burdenbetween in-house competitive differen-tiation, and collaborative pre-competi-tive work – for research, standards,improving supply chain agility, etc.Scarce funds in today’s troubled globaleconomy make this doubly important.

This section includes two insightfulpapers from CEOs of two leading pre-competitive research institutions acrossthe Atlantic – SEMATECH and imec.Both have a rich history of enabling andaccelerating progress of the semicon-ductor industry, and paint a compellingpicture of the value of collaboration.

PRINTthis article

E-MAILthis article

13www.future-fab.com |12 | FUTURE FAB International | Issue 42

20/20VISIONSFUTURE VISIONS & CURRENT CONCERNS

Between now and 2020, our planet andits people face a number of challenges.Challenges that have to do with the sus-tainability of our growth path in – amongother areas – health care, energy use andmobility.

The solutions to tackle these challengeswill be complex, but they will surelyinclude the use of technology. For a part,this will be the technology that we alreadyhave, be it further perfected.

But from what I see today in our labs, wemay also expect technological breakthroughsthat will feed entire new industries.

This technology will be needed to man-age the growing amount and complexityof data and communication. It will also beneeded to generate and use energy moresustainably. And most importantly, I expecttechnological breakthroughs that will resultin better and more efficient health careservices.

Solutions Based on Nanoelectronics

Worldwide, R&D teams work on solu-tions based on nanoelectronics. Withshrinking dimensions of circuits, we canmake ever-more-cost- and energy-efficientsolutions that offer more computingpower. But even more importantly, welearn to make use of new, exciting proper-ties of materials. We use light in ways thatwere impossible until recently. And on thisnanoscale, we can even start communicat-ing with biological systems. This could leadto technology for smart, personalized andefficient health care based on highly com-plex, mass-produced electronics.

But if the past decades are anything togo by, we have learned that any relevantsolutions are becoming more and morecomplex. There is a long, complex andcostly road between an idea and a suc-cessful product, between the drawing

Tackling the GrowingComplexity and ChallengesThrough Worldwide Open InnovationLuc Van den hove imec

PRINTthis article

E-MAILthis article


http://www.future-fab.com/?d4939



board and actual fabrication – a path thatis rife with dead ends and risks.

At imec, we have pioneered a businessmodel that helps overcome these risks andcosts. Any path to a relevant technologyincludes a precompetitive component, aphase where ideas are brought to fruitionuntil they can be further incorporated bycompanies into successful products. Thisphase is crucial, and if not managed well,often kills a technology before it canbecome viable. With our business modeland successes, we have proven that thebest chance of success is to work in anopen-innovation mode, partnering withglobal companies and research institutes,and setting to work the best brains in thebest possible infrastructure.

Strengthening Worldwide Open Innovation

2012 will be a year to prepare for thefuture, for 2020 and beyond. And part ofthat will be to strengthen worldwide open-innovation efforts. In Europe, where we

have our headquarters and conduct themain part of our research, we have anecosystem of world-leading R&D institutes,world-leading equipment and material sup-pliers, and many high-end system compa-nies. I’m convinced that we can, even morethan today, turn that ecosystem into a for-midable innovation engine, offering theworld advanced technology solutions.

For open innovation in nanoelectronicsto be effective, we need the participationof the full industry value chain. Innovationis by nature multidisciplinary, blurring theboundaries of existing disciplines andinvolving experts from many domains. Tocome up with effective solutions, we needthe best brains, but also the best possiblestate-of-the-art infrastructure. In the cur-rent industry context, it will therefore beimperative to set up and work in a 450mm R&D and demonstration facility.

State-of-the-Art 450 mm Facility Today we do our R&D in a world-class

300 mm fab, often on leading and proto-

20/20VISIONS 20/20VISIONSFUTURE VISIONS & CURRENT CONCERNS

type equipment, such as ASML’s latestgeneration of EUV lithography tools. Thisenvironment supports our partners, andtogether we form the largest open-inno-vation effort in the world.

Starting from our current technicalroadmaps, over the next years we willcarefully shift work to 450 mm. We havealready built the clean-room space for thefirst tools. We next endeavor to set up a450 mm R&D and demonstration facilitytogether with key players in the semicon-ductor ecosystem to continue offeringresearch on the most advanced materials,processes and devices.

By 2018, such a 450 mm R&D pilot lineshould be fully operational. From then on,it will be a primary innovation engine – aninnovation engine that will spawn solutionsfor a long time beyond 2020.

Imec has all the assets to make thetransition to 450 mm technology a suc-cess. We have already proven we are up tothe task with the challenging change to

300 mm technology a few years ago. We have the right know-how. We have theright partners and the right people to real-ize this transition. We strive to make achange that will prepare us for the future,that will enable a sure growth path, makingan important impact on the world.

At the same time, R&D on 300 mmprocesses should be further supported.300 mm will remain important for manyyears to come, driving, e.g., importantEuropean industries such as MEMS, auto-motive, power devices, etc.

Health Care: The Next RevolutionIn the past 20 years, the phenomenal

progress in semiconductor technology hasfueled an explosion of applications. This hasresulted in the revolution of, amongst oth-ers, mobile communication and mobilecomputing. But also in the domain of ener-gy, semiconductors and nanotechnology arethe basis of many solutions. Think of photo-voltaic energy generation, power switching,


Future Visions & Current Concerns


Thought Leadership Profile

This piece has been inspired by a ques-tion . . . one that we answer on a regularbasis, but one that we want to relay on agrander scale than is usual for us. Usuallywe hold this sort of conversation withinour part of the engineering world. Oursegment of the industry, just like the entiresemiconductor industry itself, is litteredwith PR catchphrases that entice with theirtechnical phraseology. One of the hardestchallenges faced by many is the explana-tion of the complex issues that arise in thecompletion of any fabrication facility, andfurther to that, the role we at TFS play inthis grand scheme. We hope the followingwill shed as much light as possible on theunknowns.

The phrase that best describes whatTFS is all about is “critical process solu-tions” (CPS), but in light of the previousparagraph, what exactly do we mean bythat? There are three main parts of any fabproject that are broken into many subsec-tions, but in the main, all subsections fitinto these functions: a) design, which hasthe subset of steps 1 to 6 in the graphic; b) construction, which is dealt with in steps3 & 7; c) installation, step 8; and d) startup/

commissioning, before it becomes a fullyworking fab. TFS, simply put, specializes is the eighth step, the most critical part ofthis process. The largest cost in any mod-ern fabrication facility is overwhelminglycapital equipment, with upward of two-thirds of the cost of a fab being that whichthe building contains. The initial installationof such expensive assets presents probablythe single largest threat to a new facility’sestimated ROI.

If anything goes awry and delays a fabramp-up, then it could cost the manufac-turer millions in lost revenues just to trackdown the cause(s). In the fabrication busi-ness, time is quite literally money. Anotherconsideration is that delays have the po-tential to cripple a company if the facilitybecomes live at the wrong time in a busi-ness cycle or a new killer product misses its market window. That is not to mentionthe potential loss of value in the tool itselfshould it be harmed or contaminated inany manner. Handling and installingequipment worth, in some cases, morethan commercial aircraft is a dauntingprospect for any company, large or small,as the complexity of modern processing

Critical Process Solutions:Bringing Life to the Fab

PRINTthis article

E-MAILthis article


battery technology, low-energy lighting,smart metering, sensoring . . . all enablingthe implementation of the smart grid.

Expectations are that the semiconduc-tor technology will repeat this revolution inthe health care sector, As an example, withtoday’s technology, it is possible to readout the genome – the genetic code – of aperson in two weeks’ time and for a costof approximately $10,000. Now imagineyou could microsize a DNA analysis tooland put a million of them on a single chip– a chip you can mass-produce in a factoryat a cost comparable to that of commoditycomputer chips. Then you would be ableto read out a genome in a matter of hours,and for a cost below $100.

For the medical world, this would be a game-changing development. It wouldmake DNA sequencing so easy and afford-able that a whole range of new applica-tions would spring up, almost overnight.

You could, for example, do a prenatalexamination without even touching thefetus. This is because the mother’s bloodwill also contain cells, and thus DNA, of thefetus. So if you sequence DNA in a bloodsample from the mother, you’ll also findthe fetus’ genetic makeup.

The challenge for us is not so much achallenge to find new analysis techniques;there are proven techniques used in labsworldwide. Our challenge is one of systemintegration and managing complexity; ofmicrosizing an analysis circuit, and puttinga million next to each other on a chip – allwith exactly the same specification andpredictable results.

At imec, we’ve started to work on thisand other comparable challenges. Andbased on the first results, I’m convincedthat in 2020, we’ll see some amazing technological advances – advances thatwill be instrumental to solve some of thechallenges our planet and society face.

About the Author

Luc Van den hove Luc Van den hove has been CEO of

imec since July 2009. He joined the com-pany in 1984, starting his research career inthe field of silicide and interconnect tech-nologies. In 1988, Luc became manager ofimec’s micro-patterning group; in 1996,department director of unit process stepR&D; and in 1988, vice president of the sili-con process and device technology divi-sion. In 2007, he was appointed imec’s EVP& COO. Luc received his Ph.D. in electricalengineering from the University of Leuven,Belgium. He has authored/co-authoredmore than 100 publications and confer-ence contributions. �


PRINTthis article

E-MAILthis article

20/20VISIONS




Future Visions & Current Concerns



techniques as well as the tools themselvesmirrors that of the amazing technologiesthey produce, all of which amplifies therisk.

To a manufacturer, the installation processis a major exercise in risk, but one that weview as an opportunity. Our business takesrisk management very seriously; instead ofthe usual contractor relationship, we takeeither shared risk of a new fab or, in the rightenvironment, the full burden of risk onboardby removing it from the manufacturer alto-gether. It is for this reason that TFS generallyrefers to those it serves as partners asopposed to clients – an important distinction.We have a stake in the execution and suc-cess of our installations, and so the relation-

ships built exceed mere trust, becomingsomething new: a symbiotic partnership.

These statements promise much, but asso much is on the line, how can we makethem with the confidence needed toensure success? It may sound simple, butwith every large endeavor, the devil isalways in the detail. Everything within TFS’infrastructure is scrutinized to levels somecompanies would consider over-engineer-ing, but to which we refer internally asstandard practice. It is this attention todetail that has seen us grow from ourinception in 2003 to be a standard bearerin the industry, having completed projectsthat include the most advanced facilities inthe U.S. From our rigorous acquisition of

the best talent in the world, to a safetyrecord that promises project completionwith an incident and injury-free record, ontime and on spec, we claim to be thebenchmark because we have the confi-dence of those we serve. In real terms,their success and survival are in our handsuntil we hand a project over.

This concentration of focus is bornthough our dedication to not diluting ourexpertise; we work exclusively on advancedtechnology facilities. It is in this highlycomplex world that we proclaim the high-est technical expertise, of which we arevery proud. We are relied upon by thosewho cannot afford to lose in the most com-petitive markets, the manufacturing entitiesthat are changing the world that we live inand that are redefining civilization thoughinnovations in products and the way we allwork. We may work in a segment not con-sidered glamorous, and that doesn’t getmuch airtime, but we’re proud of our workand our abilities to help our partners deliv-er the products craved by the world.

Total Facility Solutions’ vision is to bethe preferred, single-source providerof process-critical infrastructure forcustomers in the semiconductor, lifescience, photovoltaic and data centerindustries.

Joe CestariPresident

Mike Anderson Executive Vice President/Chief Operating Officer

Chris Walton Vice President, East Region

Robert Hill Vice President, West Region

Joe MinerVice President, Electrical

Total Facility Solutions 1001 Klein Road Suite 400Plano, Texas 75074Phone [email protected]

PRINTthis article

E-MAILthis article

The Life Cycle of a Fab From Conception Through to Legacy and TFS’ Place in the Ecosystem


http://www.future-fab.com/?TFS42





20/20VISIONSFUTURE VISIONS & CURRENT CONCERNS20/20VISIONS

FUTURE VISIONS & CURRENT CONCERNS

How will technology evolve over the next10 years? What will the industry and technol-ogy look like around the year 2020? Ask adozen industry technologists these ques-tions and you will likely get 12 distinctanswers. However, they would most likelyagree that one thing is certain – the technol-ogy landscape will look considerably differ-ent a decade from now. The coming yearswill be more complex and uncertain thanever before, with fewer device makers andsupply chain participants and innovativetechnologies playing an even greater role in shaping our future. For those companiesand regions that can adapt to thesechanges, the next decade will provideincredible new business and economicgrowth opportunities.

Understanding where technology is head-ing is more than speculating about whatnew and anticipated breakthroughs aremeaningful. Predicting which technologieswill move into the mainstream 10 years fromnow is guesswork, but describing how theywill emerge can contribute to our strategicthinking. By observing what is happening in

the technology introduction trends of todayand how our innovation engines and collabo-rative vehicles are making it happen, one candraw reasonable conclusions about how thetechnological sphere will develop.

Industry in TransitionCollaboration is driven by economics

and scarcity. Confronted by rising costs, constrained resources and a challengingtechnology roadmap, our industry faces diff-icult technology and investment choices. Toremain competitive, we must de-crease thetime to market of new innovations whilecontrolling escalating R&D and capital costs;an inaccurate bet can easily cost millions or even billions of dollars in lost time, re-sources and market share. From a govern-ment policy perspective, developing aunique and consistent economic growthstrategy that encourages the formation ofregional technology clusters will continue to be the focus of leaders in both the publicand private sectors.

The implications for collaborative tech-nology development are evident in several

Fast-Forward 2020:Envisioning the Next Decade in Technology R&D

novel approaches being taken today toaddress the transitions to extreme ultra-violet (EUV) lithography, 3D through sili-con via (TSV) interconnects and 450 mmwafers. For example, collaborative pro-grams such as SEMATECH’s EUV MaskInfrastructure (EMI) Partnership and 3DEnablement Center have been created todrive industry consensus and ensure thatneeds are met by pooling resources tointroduce a new technology in a timely,cost-effective manner. The EMI effort hasconnected multiple segments of the EUVsupply chain in a partnership to acceleratethe introduction of manufacturing inspec-tion capabilities. The 3D EnablementCenter has brought together companiesfrom across the industry to accelerateprogress in 3D IC standards, specificationsand reference flows. Furthermore, themanufacturing and cost pressures of the450 mm transition have created an indus-trywide need for further pre-competitivecollaboration among device makers, con-sortia and equipment and materials manu-facturers. Building on ISMI’s five-year 450mm infrastructure program, the recentlyannounced industry-government-universitypartnership – the Global 450 mmConsortium – will provide new resourcesand funding to collaboratively work withsuppliers to develop 450 mm equipment.

The Move Toward Deeper Collaboration

The competitive landscape is furthercomplicated by the structural changes thathave occurred in our industry, as vertical

integration has given way to increasedsegmentation and specialization. While thismay have solved many business issues, ithas also created new visibility, coordina-tion and affordability challenges. In today’sinterconnected world, the technical evolu-tion has heightened the need for broaderand greater industrial collaboration,expanding more deeply into the supplychain. We have also witnessed the rise ofseveral prominent cooperative technologydevelopment and innovation clusters thathave grown to meet the needs of sharedinvestment and resources at a scale thatwill only increase in time.

To solve the nexus of technical challengesthat will dominate our industry’s attentionand resources over the next decade – includ-ing defects, process variations and stackingin the third dimension – the semiconductorcommunity must move away from a singularinnovation process toward more collabora-tive, joint innovation processes.

Technology Landscape of the Future

As we envision the complexities of 3Dheterogeneous packaging – the potential fornovel and exciting combinations of memory,logic processor, analog, ASIC, MEMS, pho-tonics and sensor components on a singleplatform – our partnerships will need tospan across industry disciplines and regions.We will need several global collaborativeprograms, tightly connected and appropri-ately timed and resourced, to develop therequisite common platforms, prototypingfacilities, standards and reference flows, and

Dan Armbrust SEMATECH

PRINTthis article

E-MAILthis article




design enablement. Clearly, success willrequire a critical mass of participation fromacross the supply chain, including platformand systems companies.

Future 3D device structures will requirea common enabler, 3D metrology, which in turn will depend on a collaborativeapproach. A successful model will buildearly industry consensus on technicalrequirements and roadmap gaps amongleading-edge manufacturers, metrologyproviders and research institutions. At thesame time, it will leverage emerging capa-bilities in fields such as big data analyticsand spacial imaging computation adjacentto the traditional semiconductor ecosys-tem. This wide-ranging collaboration todevelop and deploy a critical industryenabler must address the classic invest-ment dilemma of unproven technology,uncertain timing, limited markets andexpensive upfront investment.

As device sizes continue to shrink, les-sons learned from EUV mask making willguide a new collaborative approach toeliminating nanodefects. We will need topartner more deeply within the supplychain, since defect sources are increasinglyfound in equipment subcomponents andmaterials. Finding those sources willrequire improved infrastructure to detectdefects, identify their root causes and veri-fy solutions. Characterization infrastructurewill likely become common across a widevariety of subcomponents. The creation ofa defect competency center with a criticalmass of process and forensic equipmentand unique simulation and analytical

expertise would provide a new resource forthe industry to investigate generic as wellas company-specific defectivity problems.

Finally, the period following the 450mm startup and transition will most cer-tainly stimulate the need to share a moreexpensive R&D infrastructure that willincreasingly become unaffordable for indi-vidual companies. Differentiation opportu-nities will be selected more carefully andcompanies will rely more on commonresources to maintain affordability. Theindustry will benefit from accessible andflexible “playgrounds” for chip-makers aswell as equipment and materials manufac-turers, where clustered capabilities andactivities will contribute to solving thetechnical challenges inherent in the 450mm generation.

While some of the expected technicalchallenges have been reviewed, perhapsthe most fascinating one of all is the bigpicture. Each of these large transitionsinteracts with one another. How do weplan and coordinate them, as an industry,in such a way that the rate of change isaffordable and delivers the needed bene-fits to electronic systems that ultimatelydetermine the success and drive demands?How can we manage it so that the cumula-tive risk is acceptable? While there are nosimple answers, forums that integrate thesupply chain participants for this dialogueto emerge and become refined are ever-more necessary.

Our industry is facing an importanttransitional period in which change isinevitable. Companies that can focus on

the changing landscape, plan for futureinnovation and collaboration, reinvent tostay relevant and use new R&D strategiesto stay a step ahead will be well positionedto push the envelope of creative collabora-tion, forge new common ground and gen-erate strong economic profits in the yearsto come.

About the Author

Dan Armbrust Dan Armbrust is president and CEO of

SEMATECH. As a member-driven globalconsortium, SEMATECH’s role is to alignroadmaps, R&D and financial investmentson behalf of its members, partners and theindustry. With a focus on both early devel-opment and manufacturability, it drivestechnical consensus, pulls research into the industry mainstream and leads majorprograms to address critical industry transitions. �


PRINTthis article

E-MAILthis article

20/20VISIONS 20/20VISIONSFUTURE VISIONS & CURRENT CONCERNS



NEW TECHNOLOGIES & DEVICE STRUCTURESClick here to return to Table of Contents

“The end of the learning curve is nigh,”as Scott McGregor from Broadcom wasquoted in a recent blog in ElectronicsWeekly (http://www.electronicsweekly.com/blogs/david-manners-semiconductor-blog/2012/05/the-end-of-the-learning-curve.html). Two important features on thelearning curve are performance improve-ment and cost per function reduction. Thestatement of Broadcom’s CEO referred tothe reduction in cost per function of the 28nm node; he sees that as no longer the casefor 28 nm, in contrast to previous-node generations. The same conclusion was alsoreached for the next 20 nm node. Prettybold statements! At these nodes, costreduction is not only impacted by scalingbut by factors such as cost of mask making.Of course, there are other cost-impactingmeasures such as the 450 mm wafer sizeintroduction, but that is constantly post-poned to later nodes. Another cost reduc-tion approach is that of building 3D stack-ing of ICs, which has been discussed in thissection several times in earlier issues.

But it is not only cost per functionproblems that need to be conquered. To

John SchmitzSVP & General Manager, Intellectual Property and Licensing; NXP

overcome performance problems such asdielectric breakdown in advanced CMOSnodes, not only do dimensions need to bescaled down but also signal and supplyvoltages. In addition, increased leakageproblems in the off state demands devicesoperating on different principles than the“classical gated” CMOS devices. It is herewhere devices based on quantum effectssuch as spintronics, nano types of devicessuch as field-programmable nanowires,and carbon-based electronics such asgraphene devices are considered as pos-sible solutions.

Yet another intriguing upcoming tech-nology is that of photonics. The state ofthe technology is now such that it is com-patible with mainstream CMOS fabrication,therefore allowing mass volume production.In the following article by Dr. Bibermanfrom MIT, titled “Silicon Photonic Revo-lution Through Advanced Integration,”more details are described. It will be inter-esting to see in the next 10 years how thistechnology will settle in, and what contri-butions it can provide to the overall learn-ing curve.

PRINTthis article

E-MAILthis article


NEW TECHNOLOGIES & DEVICE STRUCTURES

AbstractSilicon photonics is slated to revolution-

ize short-reach communications betweenprocessor and memory chips, and evenbetween the processor cores of chip multi-processors. This crossover to optical com-munication will be driven by bandwidth,power and latency requirements, as well aseconomic imperatives. Research efforts anddemonstrations at leading academic andindustry organizations are currently pavingthe way for several feasible integrationmethods to emerge between the siliconphotonics and advanced CMOS electronics.

With the advent of optical technology,namely based on optical fiber, the telecom-munications industry has enjoyed exponen-tial growth in bandwidth while maximizingreach and minimizing power. As soon asthe optical fiber technology was made possible, it became clear that transmittinginformation using photons instead of elec-trons offered many advantages. Naturallylow propagation loss of the optical fiberthat does not depend on the data rate,coupled with its low chromatic dispersionand ability to transmit multiple signals atthe same time using wavelength-divisionmultiplexing (WDM), created an opportuni-

ty to methodically increase the bandwidth-distance product beyond what was possi-ble using traditional electrical counterparts.The development of the ubiquitous fiberamplifier based on erbium increased reach,and high-speed transceivers based on lithium niobate and III-V material systemsallowed efficient conversion between theelectrical and optical domains. Currentefforts are going beyond point-to-pointlinks, bringing some of the switching androuting functionalities into the opticaldomain to eliminate existing bandwidth,power and latency bottlenecks associatedwith purely electrical systems.

The bandwidth and distance at which it becomes more efficient to transmit datausing an optical link depends on severaltechnical and economic factors. However,as the bandwidth requirements continue toscale, this distance becomes much shorter.This crossover point has already commer-cially migrated from long-haul telecommu-nication core networks to shorter-reachmetro-area access networks, and is nowfurther penetrating data center intercon-nects. Within the data center, this transfor-mation began as point-to-point opticallinks of aggregated data between serverracks. Now it includes on-server-boardoptics and optical backplanes intercon-

Silicon Photonic RevolutionThrough Advanced IntegrationAleksandr BibermanMassachusetts Institute of Technology

PRINTthis article

E-MAILthis article



http://www.electronicsweekly.com/blogs/david-manners-semiconductor-blog/2012/05/the-end-of-the-learning-curve.html



necting these boards. The key enablingcommercial technology for these opticalapplications within the data center was the vertical-cavity surface-emitting laser(VCSEL), coupled to multi-mode opticalfibers, for shorter-reach applications spanning less than a few hundred meters.Looking into the future, we can see thiscrossover point migrating to even shorterdistances, fostering optically interconnect-ed processor and memory chips, and evenoptically interconnected processor coreson chip. The key enabling technology forthis revolution will be silicon photonics.

Silicon photonics offers many uniqueadvantages that are not present in otherphotonic platforms. Silicon photonics hasan extraordinarily high contrast betweenthe refractive index of the core (as high as3.5 for crystalline silicon) and the surround-ing cladding (about 1.5 for silicon dioxide).This high refractive index contrast enablesoptical modes to be confined and guidedby devices with sub-wavelength dimen-sions. Many silicon photonic devices lever-age the microring resonator to achievehigh-performance operation. Much physicalphenomena being explored in silicon pho-tonics are enhanced by these types of res-onator cavities, leading to much more com-pact and efficient silicon photonic devices.The high refractive index contrast in thesedevices further reduces the necessary sizeof these microring resonators.

In the passive state, the microring res-onator may act as an efficient wavelength-selective switch, filter, multiplexer anddemultiplexer, predetermined to add ordrop a target wavelength channel to orfrom a wavelength-parallel optical datastream. In the active state, the microringresonator may act as an efficient modula-tor or switch, selectively directing an opti-cal signal to its target destination. The

microring resonator may simultaneouslybehave as a passive wavelength-selectiveswitch and an active photodetector, select-ing a single wavelength channel from awavelength-parallel optical data stream tobe detected. Leveraging the versatility ofthe microring resonator, several researchgroups – including those at ColumbiaUniversity, MIT and Oracle – have alreadyenvisioned complex silicon photonic sys-tems such as full-scale photonic intercon-nection networks.

Every silicon photonic link requires pho-todetectors that absorb light at the wave-lengths of interest, usually around 1.55 µm.In the silicon photonic toolbox, germaniumis an indirect-band-gap material whose 0.8-eV direct-band transition enables strongabsorption of optical signals at these wave-lengths, and strain can be used to extendabsorption to longer wavelengths. The pri-mary challenge for germanium integrationis the 4 percent lattice mismatch with sili-con, which makes it challenging to growhigh-quality germanium material. Polycry-stalline germanium can also be used as alower-quality photodetector material that iseasier to integrate. Moreover, lasers basedon doped and strained germanium havealso been recently demonstrated by aresearch group at MIT, rounding out the silicon photonic toolbox.

All the required functionalities of siliconphotonics for photonic interconnectionnetworks – such as waveguides, modula-tors, switches, photodetectors, lasers andcouplers – have already been demonstrat-ed. Importantly, silicon photonics offerscompatibility with standard complementa-ry metal oxide semiconductor (CMOS) fab-rication processes, enabling dense integra-tion with advanced microelectronics. Thecapability of silicon photonic devices to beintegrated in this highly refined platform,

Silicon Photonic Revolution Through Advanced Integration NEW TECHNOLOGIES & DEVICE STRUCTURES

with decades of high-quality developmentdriven by the microprocessor industry,allows us to think in terms of low-costmass-volume production.

The exact method of photonic-electron-ic integration depends on several key fac-tors, including the maximum achievabledensity and yield of the physical connec-tions, as well as the inherent parasiticcapacitance and its resulting power dissi-pation added with the integration. Thereduction of this parasitic capacitancedirectly improves the receiver sensitivity,improving the scalability, robustness andenergy efficiency of the entire system.Several research groups, including those at Sandia National Laboratories and IBM,have already demonstrated proof-of-con-cept wire bonding methods to connectelectrical chips with advanced CMOS cir-cuits to optical chips with silicon photoniclinks. Such integration yields sub-picojoule-per-bit operation of these links, with fur-ther power gains being obtained throughprocess refinement and device design.

Research efforts at Oracle and Koturaare leveraging 3D microbumps to bondchips and wafers to each other, offering a method to integrate these inherently heterogeneous systems. Using thesemicrobumps, wafers with high-speed elec-tronics can be integrated with state-of-the-art silicon photonics, with a moderate-ly low capacitance of 20 fF, a pitch of 25µm and a yield greater than 99.99 percent.This method allows the individual opti-mization of each unique technology beforethe bonding.

Other research efforts at MIT are pro-posing ultralow-capacitance integration ofadvanced electronics with silicon photon-ics using the 3D through oxide vias (TOVs)developed by MIT Lincoln Laboratory. Theprocesses for fabricating these devices

has been developed and refined to achievelow-risk, 99.999 percent-yield, 3-µm-pitch3D integration with 1-fF capacitance. Thisdirectly translates to more-energy-efficientlasers, modulators and switches, as well as high-sensitivity photodetectors.

Being able to independently fabricateand test the electrical and optical chipsbefore the monolithic integration repre-sents a best-of-both-worlds approach,where only the best-performing devicesare merged together. This has the potentialto increase the yield and performance ofthe combined systems. However, thesebenefits are traded off with cost and com-plexity, since they require complex physicalintegration of these inherently heteroge-neous systems.

Research efforts at Luxtera, SandiaNational Laboratories, MIT and IBM areleveraging direct front-end integration ofsilicon photonics with CMOS on the sameexact platform. This direct integration ofadvanced electronics with silicon photon-ics offers a way to integrate both tech-nologies in a single monolithic silicon sys-tem. This method potentially offers record-low capacitances of about 1 fF, high-densi-ty integration with a 1-µm pitch and a near-perfect yield similar to that of transistors inan advanced CMOS integration. Since thisapproach simultaneously fabricates bothtechnologies in a single platform, the sili-con photonics cannot be optimized sepa-rately and brought together with theadvanced electronics.

Single-crystalline silicon consists of aperfect lattice of silicon atoms, and gener-ally offers the best set of electrical andoptical properties for silicon photonics.However, crystalline silicon can only begrown from another silicon crystal, makingit impossible to deposit on non-crystallinesubstrates, typically limiting the optical


DESIGN IMPLEMENTATION & PROCESS INTEGRATIONClick here to return to Table of Contents

In a fabless-foundry business model,transitioning to a new manufacturingprocess is very complex and involvesmultiple teams and iterations. It’s espe-cially true for cutting-edge technologies.

Capabilities and limitations of newsemiconductor processes and devicesare thoroughly characterized by thetechnology teams and encoded intophysical and electrical design rules. Foradvanced process nodes, design rulesare now augmented with DFM rules andmodels to enhance manufacturability andyield. The work inevitably involves CADtools, and hence CAD teams. All theteams need to work in sync to deliver a “universal” process design kit (PDK).Ideally, the PDK would enable designflow to work at any foundry’s customer(design house).

However, foundries and design com-panies may have differences in their toolset infrastructure and methodologies.Foundries would share sensitive processinformation only in specific coded forms.Various EDA vendors/tools have differentformats. The set of EDA tools used bythe foundry doesn’t necessarily corre-spond to the set of tools, coding conven-tions and overall design practices thatthe design house will use. Many leadingdesign companies create additional rules

Peter RabkinDirector of Device & Process Technology, SanDisk Corp.

and cells, introduce constraints andadapt PDKs to address their specificneeds and applications.

Incompatibility, inconsistency or just a small difference in any of the tools, formats, conventions, models, cells, etc.,between foundry and design house willdramatically add to the complexity andcost of creating truly efficient end-pointPDK and design flow.

The following paper by Steven E.Schulz of Si2 makes the case for thenecessity of design/foundry standards toalleviate and potentially solve the aboveissues. Based on industry examples, thepaper claims that adoption of such stan-dards will enable significant cost savingsand time-to-market acceleration.

Meanwhile, cutting-edge technologiesmove from the traditional to a new typeof scaling that involves new materials,devices, processes and chip architectures.Respectively, design rules, process mod-els and design flows will have to reflect,fit into and take advantage of the newtechnology solutions. Therefore, stan-dards also need to evolve quickly to keeppace with very fast changes in advancedprocess technologies and productdesigns that utilize them. To be efficient,the standards have to be ready andadopted by the industry at the right time.

PRINTthis article

E-MAILthis article


devices to a single layer. Polycrystalline silicon is capable of being deposited as anelectrically conductive light-guiding mat-erial. Polycrystalline silicon does not have a homogeneous crystalline structure, butinstead consists of crystalline grains sepa-rated by thin disordered grain boundaries.Although polycrystalline silicon may beused for electrically active devices, itspropagation losses are intolerable overcentimeter-scale distances. Alternatively,silicon nitride is capable of being deposit-ed, with demonstrated low-propagationlosses. Although silicon nitride is not usefulfor making electrically active devices, itsrelatively high refractive index still allowsfor high confinement sub-micrometerwaveguides. These material systems, whichare capable of being deposited together toform three-dimensionally integrated siliconphotonic devices, introduce another axisfor maximizing the performance of thephotonic interconnection networks.

Research efforts at Cornell Universityand Columbia University are envisioningdirect back-end integration of CMOS elec-tronics with these three-dimensionally inte-grated silicon photonics. This vision lever-ages silicon photonic materials that arecapable of being deposited at the relative-ly low temperatures compatible with back-end integration processes.

Just like the optical fiber technology,coupled with ubiquitous amplifiers andtransceivers, has revolutionized the tele-communications industry, silicon photonicsis slated to revolutionize short-reach com-munications between processor and mem-ory chips, and even between the proces-sor cores of chip multiprocessors. Thiscrossover to optical communication will bedriven by bandwidth, power and latencyrequirements, as well as economic impera-tives. Research efforts and demonstrations

at leading academic and industry organi-zations are currently paving the way forseveral feasible integration methods toemerge between the silicon photonics andadvanced CMOS electronics. These sys-tems will attempt to carefully optimizeintegration density, yield, parasitic powerand complexity; all of which will also con-tribute to the overall system feasibility andperformance.

About the Author

Aleksandr BibermanDr. Aleksandr Biberman is currently at

the Massachusetts Institute of Technology,where he is a postdoctoral associate in theResearch Laboratory of Electronics. Hisresearch interests include silicon photonicdevices for chip-scale computing systemsand memory access networks, and opticalinterconnection networks for high-per-formance computing systems and datacenters. �


Silicon Photonic Revolution Through Advanced Integration

PRINTthis article

E-MAILthis article





DESIGN IMPLEMENTATION & PROCESS INTEGRATION DESIGN IMPLEMENTATION & PROCESS INTEGRATION

Abstract The exchange of data between design

team and foundry has become increasinglycomplex, and the lack of interoperabilityacross EDA tool interfaces has a multi-plicative effect on inefficiencies affectingcost and risk. This article explains somekey economic challenges in developing aprocess design kit, introduces several stan-dards efforts targeting solutions and usesactual benchmarking results that indicate a strongly positive economic return oninvestment.

The disaggregation of the supply chainand rise of the fabless-foundry businessmodel has been highly successful – largelybecause it enabled greater specializationof resources and greater competitivechoice. However, the increased range ofchoices has made the data interfacesbetween design teams, foundries and EDAvendors increasingly complex. This is espe-cially true when coupled with the inherentcomplexity of advanced process nodesand leading-edge designs. The result is adramatic increase in cost, and more impor-tantly, risk – for all parties. This articleexamines those data interfaces and thekind of economic impact interoperablestandards can have for the industry.

Overview of Process Design Kit Development

Preparing a manufacturing process for use by design teams is a complex andmessy business, involving multiple teamsand multiple iterations, using a virtualkitchen sink of file formats that mustsomehow be kept in sync.

Let’s briefly review how a new manufac-turing process is enabled for a design team,assuming a fabless-foundry business model(see Figure 1). Initially, given a selectedprocess node, the capabilities and limita-tions of new semiconductor equipment are carefully characterized by the processteam. The analysis includes detailed statis-tical variability mapping of physical andchemical properties into the electricaldomain, layer by layer, as required for even-tual circuit design. That information is thenconverted into (physical) DRC design rulesand (electrical) parasitic rules that arerequired by EDA design tools. Note thatthese rules and parameters will be refined,and iterate many times before ever beingdelivered for production use.

For leading process nodes, a team ofDFM experts will work closely with theprocess team on these design rules toimprove yield. They will incorporate

The Economic Case forDesign/Foundry Standards

requirements provided by chip designteams, as well as imposing restrictions onthem for the sake of yield. Because of theidiosyncrasies of each proprietary EDAvendor format and behavior of each tool,an internal CAD team is almost alwaysinvolved.

Now that we have the design rules and parasitic data for the new process,they must be incorporated into a processdesign kit (PDK) that will enable the fullcapabilities of a design flow to work. APDK team, working with the CAD team,

will use many additional files to add thesymbol set, programmable cells (p-cells),callbacks, SPICE netlists, layout-vs.-schematic rules, layers and constraints, and test harness. A new set of functions,called targeting, may also be required atadvanced process nodes.

Once a foundry has delivered a verifiedPDK, it is not uncommon for large cus-tomers to add their own rules, constraintsand macrocells to the PDK to support theirspecific designs and other businessrequirements. In fact, specific project

Steven E. SchulzSi2

PRINTthis article

E-MAILthis article

Figure 1. Generalized PDK Development Flow

SPICE Netlist

Internal DRM

Conceptual PDK Development Flow

ChipDevel.Team

ProcessTeam

DFMTeam

InternalCADTeam

PDKTeam

DRC/DFM/LVS

Test Harness

Symbol Set,CDF,

Callbacks

Layers &Constraints

Targeting

PEX/LPE

DRC/DFM/LVS

Layers &Constraints

Targeting

Requirements

Tool Flows

Requirements

Rules, Models

PEX/LPE

P-cells




teams may further augment this PDK withtheir own project-specific rules, constraintsand macrocells. Version control can be-come very complex and error-prone, madeworse by so many different files and filetypes.

Pressing Economic ChallengesGiven the complex interdependent

sequence described above, it should notbe surprising to find inefficiencies withinthe flow. To begin with, the foundry mustcode its design rules and parasitic parame-ters in the specific format required by eachvendor. This is costly and inefficient, andthese costs are multiplied with each itera-tion of the design rules. The inefficiency

further repeats itself at all customer siteswhere the received PDK is modified.

In addition to DRC rules and parasiticdata, the PDK also contains other elementsthat are either proprietary or implementeddifferently across industry based uponinternal conventions. For example, at leastfour popular scripting languages are in useacross the industry to perform the samefunctions – but using different syntax. Theproblem is exacerbated by incompletedocumentation and inconsistent imple-mentation of the semantics for the vendorfile formats, resulting in lossy or inaccurateconversion.

While the problems are not new, thecost of these inefficiencies is exploding

due to increasing complexity of leading-edge process nodes and the difficulty inwriting and verifying rules for them. Thenumber of lines of code required for anadvanced DRC deck has quadrupled inrecent years, which also makes it muchharder to understand the DRC/DFM in-tent buried within these “assembly code”instructions. So the true economic impactis not only the 4x cost of developing a newdeck, but repeating that for multiple EDAtool formats. One foundry developing 20nm PDKs expected it would have to hire an additional 75 staff members to supportits next node unless the proposed stan-dards succeeded.

Let’s use some aggregate data providedto Si2 from member companies to esti-mate some of the costs involved. For afoundry that had typically invested three-person-months per kit, and delivers 50kits/year, the annual baseline cost mightapproach $2 million/year (large foundriesproduce over 200 kits per year). Factoringin advanced node complexity, the costwould at least double to $4 million/year –an increase of $2 million/year. Now wemultiply the cost per PDK to match thenumber of redundant formats/languagesinvolved. Typical estimates are a need forat least two formats in p-cells, rule decksand tech files; at least three formats forcallbacks and CDF, and four for SPICEnetlist variations. The resulting analysisshows a net cost increase of $1.4 million/year, or 35 percent unnecessary burdendue to a lack of interoperability.

More importantly, this extra workstretches out the time to delivery as well,and this can mean that a specific PDK fileset might not be delivered until three tosix months behind others, based uponwhich EDA tools are used at the cus-tomer’s site. This can easily create a

time-to-market economic impact in thetens of millions of dollars.

The economics get more difficult overtime because technology needs expand,and this creates more inefficiencies whentrying to support multiple vendors andfoundries. At 32 nm, parasitic formats nowrequire over 150 detailed parameters todescribe one interconnect stack, and itgets worse at 22/20 nm. New require-ments, such as targeting functions or pat-tern-matching technology, are now beingplaced on DRC decks in an attempt to bolster yield.

In one recent real-world example, man-ually translating between vendor parasiticformats resulted in an undetected ambigu-ity that caused a significant timing error in the manufactured silicon vs. simulation.The failed chip forced a re-spin of thedesign including manufacturing delays,costing millions of dollars – due to the lackof a single standard with clear semantics.These problems are only expected to getworse unless a more manageableapproach is deployed.

Standards Can Solve ProblemsIf the costs (and risks) of supporting

multiple foundries with multiple EDA for-mats are getting out of control, whatmethod can be employed by the industryto tackle solutions to these problems?When numerous established formats andmethodologies are well entrenched andhard to change, solving the problem canbe especially difficult. However, companiesacross the supply chain asked Si2 to lead acoordinated approach for DFM, leading toformation of the DFM Coalition, and morerecently did the same for PDKs, leading toformation of the OpenPDK Coalition.

The key insight necessary to solve anentrenched format problem is to rise

The Economic Case for Design/Foundry Standards DESIGN IMPLEMENTATION & PROCESS INTEGRATION

Figure 2. OpenDFM focuses on advanced verification intent.

OpenDFM: 10x Reduction in DRC Rule Count

Parser Implementation Libs Rule Templates

API Socket API Socket API Socket

Source File OpenDFM Rules

3x – 5x Smaller

OpenDFM Parser

Open

Community

Vendor A

Function Library

Vendor A

Implementation

Vendor B

Implementation

Vendor B Format

Function Library OpenDFM rules supply the

verification parameters for 3-5

different DFM engines all

written in their native language

with no loss of verification

accuracy or performance

EDA Vendor

Proprietary

A Encrypted B Encrypted

OpenDFM is a standard metadata

format that describes the circuit

patterns well known in the industry as

Systematic Yield Detractors

OpenDFM describes the

Verification Intent but not

the Verification Implementation

Foundry Encrypted



above the detailed formats: Capture theintent, and let automated generators output the existing detailed formats asrequired by each engine. This is not unlikewriting in C++, allowing the compiler tooutput assembly code for each targetprocessor. The trick to make this approachwork is to properly capture the semanticsof the proprietary formats within a newhigher-level standard, organized aroundthe intent (the “what”), as opposed to theassembly-level operations (the “how”).

The DFM Coalition has just releasedOpenDFM v1.2 for broad industry adoption(see Figure 2). OpenDFM is supported by ajoint contribution of iDRC technology from

TSMC, Mentor Graphics and Synopsys. The DFMC is now working on OpenDFMv2.0, which will include DRC+, a pattern-matching technology contributed byGlobalFoundries. DRC+ patterns enablenew co-optimization capabilities as a complement to traditional design rules.

The DFM Coalition has also releasedOPEX 1.0 (open parasitic exchange), whichmerges the semantics of the vendor para-sitic formats into a single canonical repre-sentation. Rather than defining anotherformat, it is delivered with a SQL-baseddatabase containing the parameters, and aplug-in architecture for queries that can beused by other applications. This makes it

far more useful than any of the file formatsit replaces, and yet OPEX can automati-cally generate the existing formats.

The OpenPDK Coalition has justreleased several standards that are “chap-ters” within the larger overall OpenPDKstructure; namely, the standard symbol set, parameters and callbacks. These stan-dards, along with other “chapters” (includ-ing OpenDFM and OPEX), are wrapped intoan XML-/XSD-based standard database, the“open process specification” (OPS). OPSpulls together all the pieces of a PDK in a consistent way, and the XSD templateensures correct-by-construction input oflegal input units, ranges and data types atthe point of entry. OPS is designed to bethe master repository for all PDK informa-tion, direct from source validation at thefoundry to customer delivery (see Figure3). To support co-existence, OPS genera-tors will automatically output the variousfile formats required by different vendors,foundries and customers across industry.As confidence builds, the extra step of generating the older file formats can beskipped entirely, allowing validation of theDRC/PDK information to occur only oncefor even greater cost savings.

Tangible Economic BenefitsAdoption of these standards will enable

significant savings in terms of cost/effi-ciency, error avoidance and time-to-mar-ket. Si2 member companies have reportedtangible benefits such as a 10-35x reduc-tion in DRC rule count using OpenDFM, a1,000x faster ability to find yield detractorswith targeting functions in OpenDFM, a10,000x speedup in finding yield sensiti-vities using DRC+ (now being integratedwith OpenDFM), and a predicted 400 percent resource savings with adoption of OpenPDK.

ConclusionsWhile standards development requires

extraordinary patience, the resulting valueproposition and economic benefits can faroutweigh the effort required for develop-ment. The value of effective standards,such as those focused in this article,increases not only with adoption but alsowith the complexity of process technologyand the quantity of handoffs involvedacross the supply chain.

About the Author

Steven E. SchulzSee bio on page 10. �


The Economic Case for Design/Foundry Standards DESIGN IMPLEMENTATION & PROCESS INTEGRATION

PRINTthis article

E-MAILthis article

Figure 3. OPS Standard Flow, Native OPS Support

DRM/PDK

OpenPDK Optimized Flow (2013+)

ChipDevel.Team

s DFM

Team

Internal

CAD

Team

OPS

Requirements

Tool Flows

Requirements OpenDFM

Process

Team

PDK

Team

Rules, Models

Any

Vendor

DRC/DFM/LVSTargetingLayers &

ConstraintsPEX/LPE

Symbol SetCDF

CallbacksSPICE NetlistTest HarnessP-cell parms



MANUFACTURING: FABS, SYSTEMS & SOFTWAREClick here to return to Table of Contents

Time ... with his law of relativity,Einstein gave us a different conception of it. More recently, some scientists haveexpressed grave doubts about the veryexistence of time as a physical variable(“The End of Time,” by Julian Barbour).

Apart from these philosophical digres-sions, time is a quantity (natural or not)perceived by common sense, and it's veryimportant not only in everyday life, but alsoin professional and business fields.

In the manufacturing industry, termssuch as lifetime, timely, down/up time,process/step time, cycle time, etc., are onthe agenda, and they direct working andindustrial strategies. In the 2011 ITRSFactory Integration report, the very word“time” is used almost 200 times.

The capacity and productivity of a plantare determined by quantities that dependon time, and special terminology and met-rics have been introduced. One of these

Giuseppe FazioAdvanced Process & Equipment Control Sr. EngineerMicron Semiconductors Italy

methodologies and metrics, which hasbeen introduced and studied in recentyears, is wait time waste (WTW).

The ITRS defines wait time waste as thedifference between the cycle time of a “hotlot” in a factory and one of a normal lot.The ISMI viewpoint is that wait time wasteis the unnecessary time of productionspent waiting.

The article presented in this sectionshows a precise analysis and the supporttools for the monitoring of WTW.

In it, the working group composed bySEMATECH, GLOBALFOUNDRIES, IBM,Intel, Micron and Cimetrix presents their col-laboration project. The authors pay atten-tion to a SEMI standard ballot for industryadoption, and ISMI expects to include theresulting set of time elements in a SEMIstandard proposal to promote the consis-tent measurements of product wait time.

So, take your “time” and enjoy the read.

PRINTthis article

E-MAILthis article


MANUFACTURING: FABS, SYSTEMS & SOFTWARE

Time is the universal measurement bywhich we are all bound. Time is precious –it’s consumed second by second, never toreturn, which drives the need for organi-zations to have a systematic method tomake time waste visible so that it can beeliminated.

Some may insist that their lot dispatchor AMHS systems exhibit no time wasteand that their tool operations are opti-mized. However, systematic measurementand visualization of time consumption canbring examples of time waste to the fore.At IBM, for instance, we have found wasteby systematically identifying and analyzingtime consumption. In one example, a longtool idle time with WIP on a short cycletime tool was identified and reduced by 30 percent. In another, a tool within ameasurement fleet was found to consumesignificantly more time at the end of eachrun. The discovery and elimination of thisissue led to four extra hours of productiontime per day.

From our experience, standard meth-ods are needed to measure time in amodern semiconductor factory to effec-

tively eliminate waste. Measurement stan-dards provide the basis for understand-ing what a time measurement means so it can be discussed among industrial,process, equipment and software engi-neers, as well as with equipment and sys-tem suppliers. A measurement standardprovides a common language, allowingthese groups to collaborate. Otherwise, a tower of time-waste Babel results inengineers and suppliers arguing differentviews of time consumption; the conse-quence is ineffective collaboration andeven more time waste.

In response, ISMI’s Wait Time Wasteproject was initiated to develop metricsand methods to systematically measuretime waste, prototype the metrics andmethods, and then develop a SEMI stan-dard ballot for industry adoption. Anindustry standard will provide a commonlanguage to measure, identify and discusstime waste within a fab and with suppliers.Additionally, a standard will create a mar-ket for software suppliers to provide meas-urement tools and for optimization con-sultants to offer time reduction services.

Wait Time Waste (WTW)Metrics, Methodology and Support Tools

Jackie Ferrell,1 Les Marshall,2 Chris Cartier,3 Jonathan Matthews,4

Toysha Walker,5 Alan Weber,6 Lance Rist7

1ISMI/SEMATECH 2GLOBALFOUNDRIES 3IBM Microelectronics4Intel 5Micron Technology 6Cimetrix Inc. 7Senior Industry Consultant

PRINTthis article

E-MAILthis article





1. Background and HistoryA primary mission of ISMI is to achieve

effective solutions to semiconductor fac-tory productivity challenges and cost opt-imization opportunities for its membercompanies. In July 2007, ISMI announcedthe “Unified 450 mm/300 mm PrimeFactory Guidelines,” a set of 19 guidelinescommunicating ISMI’s vision of the next-generation factory, and held a workshopon them at SEMICON West.

At the same time, the ITRS FactoryIntegration Technical Working Group (FITWG) was investigating the concept ofwaste reduction, and at the ITRS Winter2007 meetings in Kamakura, Japan,Applied Materials presented a WasteReduction Roadmap to the FI TWG thatintroduced the term “wait time waste” forthe first time. The value of this conceptwas immediately recognized by the TWG,

and the concept was subsequently includ-ed in the 2009 ITRS.

From there, other initiatives influencedthe development of the wait time wasteconcept, including an ISMI NGF Small LotManufacturing project that highlighted theneed for wait time waste visualization andvarious SEMI task forces that sought todefine specific metrics for measuring thecomponents of cycle time and relatedequipment performance.

Against this backdrop, the ISMI WaitTime Waste project was formed to alignthese disparate industry efforts into aneffective, common methodology with supporting standards and validation tools.

2. ConceptsProduct-centric Perspective (“Wafer View”)

While many look for waste in the form ofequipment utilization, wait time waste has a

Lot Waiting on Tool

Load Port

Transport to Stocker

Lot Waiting in Stocker Transport

to Tool Setup Lot Processing

Po

st

Pro

cessin

g

End of Prior Operation

Wait Time Wait Time Wait Time Wait Time

Active Time Active Time

Operation Completed

1st Wafer Leaves Carrier

Last Wafer Arrives Back in Carrier

Active Time

Active and Wait Time Elements

Total Time Required for Single Operation – Cycle Time

Figure 1. Active and Wait Time Elements

Wait Time Waste (WTW) Metrics, Methodology and Support Tools MANUFACTURING: FABS, SYSTEMS & SOFTWARE

product focus. The ITRS specified wait timewaste as the difference between the cycletime of a “hot lot” through a factory andthat of a normal lot. ISMI sees wait timewaste as any time the product spendsunnecessarily waiting. Even in a well-run fac-tory, this difference can be 150 percent ormore of the hot lot cycle time; hence, theopportunity is significant and the goal issimple: Improve product cycle times throughthe systematic identification and eliminationof time waste at critical points in the lifecycle of the product within the factory.

Active Time and Wait TimeActive time is defined as the duration of

a physical service or action performed uponthe lot or substrate. Wait time is defined asthe period when no physical service or

action is being performed on the lot or sub-strate. Waste is time that is not spent per-forming a necessary or required action orservice. As such, waste can be found duringboth active time and wait time throughoutthe manufacturing process. As an example,Figure 1 illustrates a number of active andwait time elements that may occur in a single manufacturing operation.

More About Waste The value of time in relation to the prod-

uct can be different from one operationalmodel to the next. For example, the timerequired to actually transport a lot fromequipment A to equipment B might beconsidered active time, but it might alsoinvolve unnecessarily long durations, orwaste. Similarly, the time for the actual

Figure 2. Process Variability at the Substrate Level Source: Micron



measurement of a parameter might be con-sidered necessary (required) active time byone fab but a wasted step that can be elim-inated by another fab. The time a lotspends in a stocker might be considerednecessary wait time, but it may be exces-sive, thereby including waste. Thus, in the final analysis, the user determineswhether wait time is required and whetheror not various wait time and active timeelements include waste.

Throughput VariabilityOne of the most difficult tasks facing

manufacturing engineers is identifying thesources of variability. For process engi-neers, the challenge is maintaining productquality. For equipment engineers, theproblem is tool availability. For industrialengineers, the focus is throughput, both atthe factory level and at an individual pieceof equipment.

The latter case is exhibited clearly inFigure 2, which shows that every fourthwafer requires an additional 60 units ofprocessing time. The chart doesn’t identifythe cause of this systematic delay, but itdoes narrow it down to the first step in the wafer’s flow through the tool. Since all wafers in the lot should be processedwith the same recipe, we can assume that this extra time falls into the category of“unnecessary waiting” (our definition ofwait time waste) and could be eliminated.This would decrease the average through-put time of this tool, saving valuable cycletime at the fab level.

Of course, this level of analysis andvisualization requires either a very atten-tive industrial engineer with knowledge ofthe inner workings of the equipment and a good stopwatch or a robust implement-ation of the SEMI substrate tracking stan-dards. The latter provides explicit events

to chronicle the movement of a waferthrough the various material locations inthe equipment, which can be logged andanalyzed with a variety of tools and tech-niques. Supporting this level of automatedanalysis is another objective of the WaitTime Waste project.

3. WTW MethodologyWait time data must be collected from

various sources, including the productionequipment, the factory AMHS and applica-tions within the factory system (e.g.,scheduling and dispatch).

To begin the process, a product unit isselected. This may be a single substrate ora lot. Wait time is measured at the lot levelin most areas in the factory, but within theequipment, it can also be measured at thesubstrate or wafer level. A time period forobservation or investigation within the lifespan of this product unit is then selected.This period may be long or short; for exa-mple, the span of the entire life cycle of the lot in the factory or one lot processedthrough a single piece of production equip-ment. This time is then divided into con-tiguous time segments, identified by facto-ry and equipment events. For active times,the events tell us which activity has startedor ended. For wait times, the events ulti-mately clarify why the product is waiting.

Each time segment is finally assignedone or more metrics called “time ele-ments.” A time element categorizes thetime segment according to the currentactivity or the action for which the productis waiting. ISMI has defined both an initialset of time elements as a starting pointand standard equipment events thatshould be used to trigger transitions fromone to another. This method produces ananalysis-ready data set from basic event-oriented data collected from the factory.


These metrics and methods will beexercised using actual equipment and fac-tory data as a proof of concept. The firstphase of this work is focused on produc-tion equipment data. Later phases willaddress AMHS and other factory systemevents. Based on lessons learned duringdevelopment and use, the set of time ele-ments will likely be modified as needed toyield the best results. ISMI expects toinclude the resulting set of time elementsin a SEMI standard proposal to promotethe consistent measurement of productwait time.

ChallengesWhile this may appear to be a simple

process, in practice, some challenges mustbe overcome:

• Data format – There is no standard for-mat for the logs of messages amongfactory systems. Because SECS messag-ing has a high degree of uniformity, wedecided to begin with productionequipment.

• Event report content – Messaging tendsto be in a shorthand format to savebandwidth, a throwback to the 2400baud days. SECS event reports aredefined by the user. Each report mes-sage contains only the data values; itdoes not identify the variables. Tounderstand the messages, one mustobtain the report definitions.

• Event/data identity – The report defini-tions contain the variable IDs, but notthe names or descriptions. The suppliermust document the IDs of each eventand variable reported.

• Standard events/data identity – Manyof the events reported by the produc-tion equipment are mandated by widelyused SEMI communication standards.

However, these SECS events and var-iables do not fall under a standard naming convention. One must oftenmap the actual events to the standardevents manually.

• Event availability – The degree of con-formity to SEMI communication stan-dards varies from one equipment toanother. In some cases, certain eventsthat are deemed important to wastetime wait are not available from theequipment. In other cases, the neededevents are available, but the equipmenthas only a few events that can be acti-vated for reporting. If an event is notavailable, an alternative must be select-ed or an approach that excludes theevent must be developed.

The WTW method takes these chal-lenges into account. It identifies the infor-mation needed to create the analysis-ready data set and specifies a way to com-bine it to produce that data set. In prac-tice, however, validating the methodrequires significant amounts of factorydata and software tools to automate itsprocessing whenever possible.

4. Wait Time Waste ReferenceImplementation

To ensure that the ISMI WTW methodis feasible and efficient, ISMI has part-nered with Cimetrix to create a Wait Time Waste Reference Implementation(WTWRI). The WTWRI will demonstratethe process and ways to overcome thechallenges outlined above. The WTWRIwill be demonstrated at SEMICON West2012; it is expected to be publicly avail-able in the third quarter of 2012.

The ISMI WTWRI application isdesigned to input data from a communi-cations application message log and



process that information through asequence of steps into a data set that can be used to analyze product time overa user-determined observation period. The WTWRI will also demonstrate that the final data set is ready for subsequentanalysis by reading it and creating a num-ber of specific visualizations (e.g., graphsand charts) of the data.

This overall flow is shown in Figure 3,which includes references to not only thedata files created by the WTWRI but also

the other information that must be provid-ed for its execution. The latter includes theevent report definitions, which are specificto each factory’s data collection approach;subsets of the equipment data dictionariesthat define the specific event and variableIDs for a particular model of equipment;mappings of those supplier-specific eventsto the SEMI standard events that bracketeach of the WTW time elements; and run-specific configuration information providedby the user of the WTWRI.


Step 2

Step 1

Step 3

Factory

Message

Logs

IF1

IF2

WTW

Data

Event Report

Definitions

Supplier Data

Dictionaries

Standard Event

Mappings

Tool

.config

Execution

.config

Factory Applications

WTW Analysis

WTWRI

Visualization

Charts, Graphs,

Reports

Figure 3. WTWRI Processing Flow

Although the WTWRI is not limited to a specific set of events and time elementdefinitions, its initial use will depend onevents provided by the process and meas-urement equipment. To this end, ISMI iscurrently identifying the common equip-ment events used in fabs. SEMI E90 (sub-strate tracking) and E40 events (processstart and end) will likely be the most sig-nificant events used to capture time ele-ments for equipment. Future developmentwill include some factory and AMHS eventsand messages generated by equipmentdata acquisition (EDA) communications.The initial set of metrics and approachesto WTW data collection will be publishedin an ISMI guideline in July 2012.

5. Future WorkOnce the WTWRI becomes available,

ISMI member companies will demon-strate the metrics and methods usingfactory data. The applicable results willprovide proof of concept for standardsdevelopment in 2013. As the industrygains experience, the WTWRI will beupdated to accommodate the evolvingstandards as well as more advancedoptions for visualizing the WTW datasets that it generates. Moreover, eventsfrom other factory data sources will beadded that enable fab-level WTW andcycle time analysis, as well as finer-grained analysis of tool-level throughputtimes (see Figure 4).

WTWRI

Fab-level WTW/Cycle Time Analysis

Tool-level WTW Analysis

Event/Alarm Analysis

Figure 4. The Rest of the Story…


LITHOGRAPHY LANDSCAPEClick here to return to Table of Contents

Electron-beam (e-beam) lithography isthe process of directing an electron beamacross a resist layer and thereby creatingpatterns that can be etched. The primaryadvantage of e-beam lithography is that itbeats the diffraction limit of light and printsfeatures in the nanometer regime (a struc-ture of <20 nm was demonstrated even inthe early 1990s). Since the pattern is gener-ated by controlled e-beam exposures, maskis not required in e-beam lithography. Thisform of maskless lithography (ML2) has beenwidely used in activities such as photomask-making and research and development.

The key limitation of e-beam lithographyis throughput, as it takes a very long time toexpose an entire silicon wafer. Historical datashow that the throughput deteriorates rapid-ly with improving resolution, i.e., higher reso-lution obtained in e-beam lithography isalways associated with a sacrifice of through-put. A long exposure time leaves the uservulnerable to beam drift or instability, whichmay occur during the exposure. Thus, thisenormous throughput challenge in e-beamlithography inhibits substitution of conven-tional lithography in volume manufacturing.

Although e-beam lithography is less likelyto replace 193 nm immersion lithography(193i) as a mainstream lithographic solutionfor volume semiconductor manufacturing, itsunique capability should not be overlooked.In fact, it can be pursued as a complementa-

Yayi Wei Principal Member of Technical Staff, GLOBALFOUNDRIES, USA

ry solution to 193i, such as patterning thecostly and difficult critical layers. The feasi-bility of complementary lithography using193i and e-beam lithography in a mix-and-match approach has been demonstratedrecently. In this section, researchers fromFraunhofer Institute and Multibeam Corp-oration report on the advancement of e-beam lithography in the scope of comple-mentary technology.

193i will continuously be the solution for32 nm half-pitch node (corresponding to 20nm logic node), and possibly being pushedto 22 nm half-pitch node or 14 nm logicnode (with the assistance of double/triplepatterning). However, patterning at such lowk1 factor involves sensitivities to a myriad ofimaging parameters – including illuminatorsource shape, lens aberrations, process set-tings, and more. These sensitivities make itimperative that all of the scanner’s imaging-related parameters are quickly controlledwith extreme accuracy, and a comprehensiveand efficient solution for optimizing thescanner’s imaging system setup is required.Another paper in this section, written byresearchers from Nikon Corp., reports ontheir achievements on illuminator (lightsource) and mask optimization (SMO),including freeform pupilgram generation,pupilgram adjustment and optical proximityerror (OPE) matching, as well as thermalaberration prediction and control.

PRINTthis article

E-MAILthis article


About the Authors

Jackie Ferrell – Equipment & Factory Pro-ductivity Project Manager, ISMI/SEMATECH

Les Marshall – Principal Member ofTechnical Staff, GLOBALFOUNDRIES

Chris Cartier – 300 mm Advanced Micro-electronics Solutions I/T Manager, IBM

Jonathan Matthews – Staff Technologist,Intel

Toysha Walker – EPT Program Manager,Micron Technology

Alan Weber – Director, Value-AddedProducts, Cimetrix Inc.

Lance Rist – Senior Industry Consultant �


Wait Time Waste (WTW) Metrics, Methodology and Support Tools

PRINTthis article

E-MAILthis article

AMHS – automated material handling system

CEID – collection event ID – in SECS, the identifi-er of a collection event, an occurrence on theequipment that is reported to the factory withassociated data variables

EDA – equipment data acquisition – a collectionof related SEMI standards (E125, E132, E134, etc.)that define an XML/SOAP-based interface fromfactory client applications to the equipment fordata collection; EDA is an alternative to SECS for data collection using mainstream technology

Hot Lot – a lot that has high priority within themanufacturing process such that it is the next lotprocessed upon arrival at any production equip-ment and the first lot moved to the next produc-tion equipment

SECS – SEMI Equipment CommunicationsStandard, a specification for communicationfrom production equipment to factory host;SECS-II, message content, is commonly used,and the messages are transmitted over Ethernetaccording to another SEMI standard, high-speedmessage services (HSMS)

SML – SECS message language, a format fordescribing SECS messages in a text format; SML is commonly used in connection with equipmentautomation software in the semiconductor industry

Time Element – a categorization of a time seg-ment for a unit of product; one or more time elements may be assigned to a time segment toidentify current activities affecting the productand/or activities for which the product unit iswaiting

VID – variable ID, the ID given by the equipmentsupplier to a variable available for data collectionfrom the equipment through the SECS interface

WTW – wait time waste, the time a product unitspends needlessly waiting

WTWRI – wait time waste reference implementa-tion, a software tool customized for the extractionand visualization of events defined for wait timewaste analysis from equipment and factory logs




Lithography Landscape



Next generation lithography techniquescontinue to evolve, but IC makers needsolutions today that will keep them on theiraggressive technology roadmaps. In orderto maintain production timelines, extensionof ArF lithography is vital. To meet thischallenge, Nikon developed two new 193nm scanners – the latest evolutions of the proven Streamlign platform, which isalready adopted in leading-edge facilitiesworldwide. The Nikon NSR-S621D immer-

sion and NSR-S320F dry ArF scanners sat-isfy the increasingly demanding require-ments for overlay accuracy and ultra-highproductivity that are essential for cost-effective 22 nm applications and beyond.

The semiconductor industry is currentlytransitioning to development and high-volume manufacturing of next generationprocess devices, with the most critical lay-ers exposed utilizing ArF immersion (ArFi)scanners and double patterning (DP).

Extending Optical LithographyWith ArF Scanner Evolution

Therefore, in order to minimize costs, pro-ductivity and yield are of essential impor-tance to IC makers. This necessitates scan-ners that deliver ultra-high productivity,superior overlay accuracy, and exceptionalsystem stability.

The NSR-S621D is the most advancedscanner for high volume immersion appli-cations, and fully satisfies the rigorousrequirements of DP manufacturing. TheS621D builds upon the Streamlign platformthat is already employed globally anddelivering optimal cost of ownership forNSR-S620D immersion scanners. TheS621D incorporates further hardware andsoftware developments to provide indus-try-leading overlay accuracy and through-

put. As interferometers alone cannot suf-ficiently measure stage position to satis-fy the most stringent immersion overlayrequirements, the NSR-S621D adopts theproven Bird’s Eye Control system, whichuses laser encoders along with convention-al interferometers to accurately determinewafer position. These innovations enableoverlay accuracy ≤2 nm and superior focuscontrol to deliver maximized yield for lead-ing-edge immersion applications.

While the most critical next generationlayers will be exposed using ArFi scannerswith double patterning, many challenginglayers will still be processed using dry single exposure lithography to minimizecosts. To achieve this, non-immersion ArF

X Y

[nm]

Avg. + 3 σ ( 1 Lot )

NSR-S621D

Overlay Accuracy and Stability Across the Lot

X Y

[nm]

Avg. + 3 σ ( 1 Lot )

NSR-S320F

1.63 1.87 1.62 1.89

-5.0

-4.0

-3.0

-2.0

-1.0

0.0

1.0

2.0

3.0

4.0

5.0

[nm

]

Avg. X

Avg. Y

0.0

1.0

2.0

3.0

4.0

5.0

1 2 3 4 5 6 7 8 9 10

[nm

]

3 σ X

3 σ Y

Wafer No.

-5.0

-4.0

-3.0

-2.0

-1.0

0.0

1.0

2.0

3.0

4.0

5.0

[nm

]

Avg. X

Avg. Y

0.0

1.0

2.0

3.0

4.0

5.0

1 2 3 4 5 6 7 8 9 10

[nm

]

3 σ X

3 σ Y

Wafer No.

Figure 1. The NSR-S621D and NSR-S320F have demonstrated overlay accuracy and stabilitybelow 2 nm across the lot.

-30 -25 -20 -15 -10

-5 0 5

10 15 20 25 30

Day1 Day2 Day3 Day4 Day5 Day6 Day7

Fo

cu

s [n

m]

-30 -25 -20 -15 -10

-5 0 5

10 15 20 25 30

Day1 Day3 Day5 Day7 Day9 Day11

Fo

cu

s [n

m]

Focus Uniformity and Stability

Including edge shot

S621D S320F

3 : 12.2 nm 3 : 12.0 nm

Range: 9.2 nmRange: 10.4 nm

-50 nm +50 nm

Figure 2. The S621D and S320F provide across-wafer focus control of ~12 nm and deliverexceptional focus stability over time.

Overlay Accuracy and Stability Across the LotFocus Uniformity and Stability



Lithography Landscape



Nikon Corporation is a worldwideleader in lithography equipment forthe microelectronics manufacturingindustry with more than 8,000 expo-sure systems installed worldwide.Nikon offers the most extensive selec-tion of production-class steppers andscanners in the industry. These prod-ucts serve the semiconductor, flatpanel display (LCD) and thin-film magnetic head (TFH) industries. NikonPrecision Inc. provides service, training,applications and technical support, aswell as sales and marketing for Nikonlithography equipment in NorthAmerica.

Takao NaitoChief Executive Officer and President

Hamid ZarringhalamExecutive Vice President

Nikon Precision Inc. 1399 Shoreway RoadBelmont, CA 94002Toll-free 800.44.NIKONPhone [email protected]

PRINTthis article

E-MAILthis article

scanners that are able to deliver overlayaccuracy comparable to immersion sys-tems with ultra-high throughput are imper-ative. To meet this need, the NSR-S320Falso employs the proven Streamlign plat-form and Bird’s Eye Control system to sat-isfy the requirements of the most demand-ing dry ArF layers. Here again the hybridcontrol system takes advantage of both therepeatability of the encoders, as well as the linearity and long-term stability of theinterferometers. In comparison to the pre-vious generation scanner, these innovationsenhance focus control and improve over-lay accuracy by more than 50 percent to≤3 nm, which boosts yield for critical dryArF applications.

Another key challenge for immersiondouble patterning is affordability. There-fore, ultra-high throughput for the immer-sion layers, as well as the associated criticaldry ArF layers, is an essential factor inmaking IC manufacturing cost effective.The NSR-S320F and NSR-S621D scanners’wafer stages use optimized scan speedsand acceleration capabilities to reduceexposure times. In addition, their StreamAlignment wafer mapping systems utilizemultiple alignment microscopes (Five-EyeFIA) and a wide-area autofocus sensor(Straight Line Autofocus) that maps theentire wafer surface to dramatically reduceoverhead time and deliver world-classthroughput ≥200 wafers per hour (125

exposures/wafer). Stream Alignment alsoprovides significant accuracy benefits. TheFive-Eye FIA system enables a substantialincrease in alignment sites with minimaleffect on throughput, while Straight LineAutofocus creates a dense map of theentire wafer surface to optimize across-wafer focus control.

Being first to market with new devicescan be the difference between profit andloss. Consequently, the S320F and S621Dalso incorporate the mature Modular

2

Structure used on the NSR-S620D tostreamline system installation and main-tenance to ensure maximum profitabilityfor chip manufacturers.

Next generation lithography methodscontinue to evolve, but chip-makers needsolutions today that will support theirdemanding roadmaps. ArF lithographyextension is required in order to maintainmanufacturing timelines. Therefore, Nikondeveloped two new ArF scanners, the lat-est evolutions of the proven Streamlignplatform, to meet this challenge. The NSR-S621D immersion and NSR-S320F dry 193 nm scanners deliver throughput≥200 wafers per hour with industry-leadingoverlay accuracy (S621D ≤2 nm and S320F≤3 nm) to provide the most cost-effectivelithography solutions for 22 nm applicationsand beyond.

Nikon. Evolution in Action.

0

50

100

150

200

250

S310F S320F

Thro

ughput [W

PH

]

Alignment

Exposure

8 pt. align 16 pt. align

26 x 33 mm 96 shots

142 WPH

233.6 WPH 210.9 WPH/125 shots

+64%

S320F Throughput

Figure 3. S621D and S320F throughput is ≥200 wafers per hour using 125 exposures/waferconditions. S320F throughput was improved by more than 60% compared with the previousgeneration dry ArF scanner.

S320F Throughput


http://www.future-fab.com/?nikon42



http://www.future-fab.com/?nikon42


LITHOGRAPHY LANDSCAPE LITHOGRAPHY LANDSCAPE

AbstractMaskless patterning using e-beam

direct write (EBDW) has been successfullydemonstrated in semiconductor manufac-turing for early device engineering andtechnology learning. The Fraunhofer-Cen-ter Nanoelectronic Technologies (CNT),Dresden, has extended its e-beam pattern-ing competence on 300 mm wafer towardthe 28 nm node requirements making useof the full CMOS integration capability of its 50KV-shaped beam tool (VistecSB3050DW). In addition, the process port-

folio was enlarged for addressing specialtyapplications in the field of master manufac-turing for nano-imprint lithography (NIL)and specific test and calibration pattern.

Device Engineering and Design Verification

The primary application field for EBDWin a state-of-the-art wafer fab is small-vol-ume manufacturing, rapid prototyping aswell as device engineering and design veri-fication. Within the last seven years, a mul-tiplicity of various FEOL and BEOL layers

E-Beam Direct Write on 300 mm Wafers:Maskless Patterning forVarious Applications

and designs has been patterned withEBDW at Fraunhofer CNT addressing dif-ferent nodes and applications. Integrationinto full CMOS manufacturing flows at different IDMs and foundries could bedemonstrated by addressing overlayrequirements and consecutive hardmaskand etch processes. In order to avoidthroughput issues, a conventional mix-and-match flow with optical lithographycan be applied.[1,2]

Figure 1 shows the standard patterningflow, executed at Fraunhofer CNT. A flexi-ble layout provided by customers or set upinternally is corrected for the e-beam-spe-cific proximity effect (PEC) and consecu-tively fractured for variable-shaped beam(VSB) exposure. The DataPrep procedureis carried out on a most advanced 64 bitLinux cluster using the software INSCALE®

from ASELTA Nanographics.[3] As anexample, EBDW patterning of a 22 nmnode M1 SRAM test pattern from GLOBAL-FOUNDRIES, Dresden, is shown.

Direct write lithography at FraunhoferCNT is currently possible on 300 mm and200 mm wafers with full integration cap-ability. In addition, wafer sizes down to 100 mm can be handled for additionalniche applications enabling cost-effectiveand flexible direct writing for many R&Dscenarios.

Nano-Imprint MasterManufacturing

In 2011, Fraunhofer CNT started activi-ties in the field of manufacturing of nano-imprint masters in close collaborationwith various customers. Implementationof suitable processes for short reaction

Christoph Hohle Fraunhofer-Center Nanoelectronic Technologies (CNT)

PRINTthis article

E-MAILthis article

Figure 1. EBDW patterning of a 22 nm node SRAM test pattern from GLOBALFOUNDRIES, Dresden: (a) original layout; (b) pattern after e-beam DataPrep using dose modulation and geometric proximityeffect correction (DMG); (c) e-beam exposure using a VSB tool (source/picture courtesy of VistecElectron Beam GmbH); (d) SEM picture of the final exposure result (resist on bare silicon).

Figure 2. Examples of nano-imprint masters transferred into silicon: (top) various grating pattern; (bottom) multi-layer master for optical coupling as designed (left) and as manufactured (right)




times to layout changes and fast produc-tion for consecutive processing wereestablished. Experiments with a simplehardmask and resist stack yielded promis-ing results for a wide range of featuressuch as line space structures and largemesh or pillar arrays. Example SEMs offinished master structures are shown inFigure 2 (top).This process takes advan-tage of existing CMOS know-how atFraunhofer CNT, especially theunmatched flexibility of the VistecSB3050DW variable-shaped electronbeam lithography tool that allows almostany feature to be written directly into theresist on the same wafer. After the litho-graphic patterning, the structures aretransferred into the silicon using a RIE

hardmask process. This allows precisedepth tuning for the imprint master withvery good depth uniformity and steepsidewall angles. This in turn ensures ahigh structure quality with superior dura-bility over the entire master area.

The production of multi-layer imprintmasters eliminates overlay limitations forconsecutive litho steps such as for stan-dard dual damascene processing. We suc-cessfully integrated a two-layer master for optical waveguides with our partnersFraunhofer Institute for Photonic Micro-systems (IPMS) and Technical UniversityDresden. Waveguides and couplings wereprinted in a wide range of sizes to allowfine-tuning of wavelengths and to be ableto characterize the waveguide behavior.

For this, a first EBDW litho step struc-tured a waveguide into the silicon, where-as a second layer patterned a coupling ontop of the waveguide in order to allowsignals of a certain wavelength to be cou-pled into the substrate. An example ofthe produced pattern is shown in Figure 2(bottom). It shows the layout of the cou-pling on the left and the final imprintmaster on the right. This feature containsa curved shape that was easily patternedvia a GDS layout provided by our partnerswith high flexibility in designing the mas-ter. In case of layout problems, adjust-ments and changes can be implementedon-site within minutes to ensure only cor-rect patterns are printed.

Complementary LithographyUsing electron beam direct write as a

complementary approach together withstandard optical lithography at 193 nm orEUV wavelength has been proposed onlylately.[4,5] This might be a reasonablesolution for low-volume CMOS manufactur-ing and special applications as well asdesign rule restrictions. Here, the highthroughput of the optical litho can becombined with the high resolution and thehigh flexibility of the e-beam by using amix-and-match approach (litho-etch-litho-etch – LELE). Complementary lithographyis mainly driven by special design require-ments for unidirectional (1D-gridded)Manhattan-type design layouts that enablescaling of advanced logic chips. Thisrequires significant data prep efforts suchas layout splitting.

Fraunhofer CNT, GLOBALFOUNDRIESDresden and IMS Nanofabrication, Vienna,successfully demonstrated the feasibility ofcomplementary lithography using 193 nmimmersion lithography and single-/multi-e-beam direct write in a mix-and-match

approach (Figure 3).[6] Regular 50 nmline/space arrays from GLOBALFOUNDRIESDresden addressing the 32 nm logic tech-nology node have been cut in predefinedareas using the shaped e-beam tool atFraunhofer CNT, Dresden, as well as on thePML2 Alpha Tool at IMS Nanofabrication.Several e-beam resist types with high etchresistance were used for the cut exposure,covering the lines/space arrays as etch maskfor the second cut etch step. Integrationschemes as well as overlay requirementsnecessary for this mix-and-match approachwere shown to be addressable for the 32nm node and below.

ConclusionE-beam direct write in a state-of-the art

wafer fab has been proven to be a highlyflexible and viable technology solution forvarious niche applications, where the useof costly mask sets is not pursued. Theaccess to a fully integrated variable-shaped (VSB) e-beam tool in a 300 mmmanufacturing environment offers signifi-cant advantages compared to opticallithography or conventional slow Gaussiane-beam tools. The constantly monitoredprocesses at Fraunhofer CNT enable aquick and precise integration of multiplelayers on silicon substrates. Direct writelithography at Fraunhofer CNT offers mul-tiple rapid prototyping applications bycost-effective and flexible patterning formany industrial and R&D scenarios.

References1. Kretz, J. et al. “Integration of EBDW of

one entire metal layer as substitutionfor optical lithography in 220 nm nodemicrocontrollers,” Microelectr. Eng. 85,792 (2008)

2. Keil, K. et al. “Design verification of sub70 nm DRAM nodes via metal fix using

E-Beam Direct Write on 300 mm Wafers: Maskless Patterning for Various Applications LITHOGRAPHY LANDSCAPE

Figure 3. Complementary exposure results using 193 nm immersion (50 nm lines/spaces) cut with EBDW in predefined locations.



e-beam direct write,” Proc. SPIE 7470,747017-1~6 (2009)

3. www.aselta.com4. Borodovsky, Y., “ArF lithography exten-

sion for critical layer patterning,”LithoVision 2010, San Jose, California(2010)

5. Lam, D.K. et al. “E-Beam Direct Write(EBDW) as ComplementaryLithography,” Proc. SPIE 7823, 78231C(2010)

6. Hohle, C. et al. “Feasibility Study ofOptical/E-Beam ComplementaryLithography,” Proc. SPIE 8323 (2012)

About the Author

Christoph HohleChristoph Hohle heads the Patterning/

E-Beam Litho department at FraunhoferCenter Nanoelectronic Technologies (CNT),Dresden, Germany. He previously workedfor Infineon Technologies and Qimonda,focusing on design, synthesis and process-ing of photoresists for various wavelengthsas well as e-beam direct write lithography.Dr. Hohle received his Ph.D. in 2000 fromthe University of Bayreuth, Germany, in thefield of macromolecular chemistry. He hasco-authored more than 35 papers andnumerous patents in the field of photoli-thography and has served as member ofthe SPIE Advanced Lithography conferenceprogram committee for several years. �


E-Beam Direct Write on 300 mm Wafers: MasklessPatterning for Various Applications

PRINTthis article

E-MAILthis article

LITHOGRAPHY LANDSCAPE

Leading logic manufacturers haveadopted the 1D layout style for critical lay-ers (poly and 1x metal). Mainstream fabsappear to have settled on the choice oflithography down to the 14 nm–16 nmnode: 193 nm ArF immersion lithography(193i) to print the lines; spacer technologyto increase line density; and 193i multiplepatterning for line-cuts. Electron-beamlithography (EBL), also called e-beamdirect write (EBDW), is not part of thesolution. In fact, EBL is highly unlikely tobe the next-generation lithography (NGL)for high-volume manufacturing (HVM) inthe foreseeable future. However, EBL doeshave an important role to play. In this arti-cle, we will show that EBL is a key andcomplementary enabler for NGL.

EBL Throughput ChallengeDonald Tennant studied a number of

direct-write-like lithographic methods,including e-beam. Using available datacirca 1995, he plotted the relationship overa wide range between areal throughput(writing speed) and resolution (featuresize). Quite remarkably, the empiricalobservation, published in 1999 and nowknown as Tennant’s Law, follows a power-law relationship:[1]

where At is the areal throughput in nm2/s,R is the resolution in nm, with a proportion-ality constant (not shown here) reflectingthe technology capability of the time.

Tennant’s Law shows that historically fordirect-write lithography, throughput deteri-orates rapidly with improving resolution.This underscores the enormous throughputchallenge facing EBL in conventionallithography for volume manufacturing.

Conventional E-Beam Pixel Writing

Chris Mack sought to explain the devas-tating effect of the 5th-power relationshipon direct pixel writing with e-beam.[2] LikeTimothy Brunner, Mack separates R5 into R2 and R3.[3] Assuming the pixel has thesame dimension as the resolution, thewafer area written by one pixel is R2 and Atis proportional to the pixel writing-speedtimes R2. (Note: The pixel can be smallerthan the resolution, or minimum feature,but not larger.)

R3 essentially represents the combinedtotal impact on throughput of a multitudeof independent and interacting parame-ters. For example:

At R5

E-Beam LithographyRevisited David K. Lam Multibeam Corporation

PRINTthis article

E-MAILthis article


http://www.futurepv.com/




• Higher-energy e-beam can improve resolution, but it also lowers resist sensitivity and reduces throughput.

• Higher-current e-beam can boost writing speed, but it also broadens thebeam, impacting resolution.

• At higher resolution, there are more pix-els to write; the time to write each pixelalso increases because greater precisionis required to write a small pixel.

“Writing one pixel at a time does notscale well, even when using multiplebeams,” concludes Mack.

EBL must also meet other lithographicrequirements such as critical-dimensionuniformity (CDU), overlay accuracy andline-edge roughness (LER). E-beam writingwith massively parallel pixels has uniqueconstraints in implementing these features.A few examples of the difficulties follow: • Wafer heating. Higher-energy e-beam

can improve resolution because of lessblurring in the resist; some EBL devel-opers push beam energy to 50 keV or100 keV. However, hitting a pixel-sizearea of the resist-coated wafer withsuch energetic electrons at current levels of milliamps can cause resistheating and potentially device damageas well.[4]

• Shot noise. As resolution gets finer,pixel size gets smaller, with each pixelcontaining fewer and fewer electrons.This can lead to a marked increase inshot noise non-uniformity, worseningline-edge roughness.

• Resist sensitivity. The more sensitivethe resist, the shorter the e-beam expo-sure time and the faster the writingspeed. Highly sensitive resist requiresvery few electrons to write, but resultsin pronounced shot noise and worse

line-edge roughness. Chemically ampli-fied resists also can improve e-beamwrite time, but the longer diffusionlength of the reactive species (to ampli-fy sensitivity) worsens resolution.

• Data volume. Pixel writing of 2D shapesin conventional design layout requires ahuge volume of data: >10 TB per layer.Whether data prep is done offline oronline, the costs of data storage, datatransfer and/or CPU processing areextremely high. This bottleneck remainsunresolved.[5]

Given all these seemingly insurmount-able challenges, it comes as no surprisethat some have declared, “EBL is doomed.”

Or, is it?

Recent Developments in EBLDespite the challenges, several com-

panies are actively developing EBL toolswith different technologies; among themare Advantest, KLA-Tencor, Mapper andMultibeam. Following is a brief summaryof these activities garnered from variouspublications. • Mapper and KLA-Tencor choose to split

the primary beam from an electronsource into massively parallel smallbeams, each small beam being a pixel.Mapper has 13,000 parallel beams; KLA-Tencor has 1 million. Advantest andMultibeam choose not to split the beambut to pattern with a shaped beam.

• Mapper’s e-beam column is cantileveredover a stationary wafer and traversesacross the entire wafer in serpentinemotions while a proprietary device con-trols pixel on/off. The pattern data canbe prepared offline prior to writing-startand fed to the column at pixel-writingspeed; alternatively, pattern data can be

E-Beam Lithography Revisited LITHOGRAPHY LANDSCAPE

transferred to the column, which thenparses the data for blanking/unblankingall of the pixels simultaneously.

• KLA-Tencor’s system employs 36columns patterning six wafers at thesame time. Two high-speed maglevcounterbalanced stages moving inopposite directions carry three waferseach. A proprietary device with dynami-cally changing patterns reflects the massively parallel beams onto the wafer,with all pixels writing at the same time.

• Advantest shrinks the physical size ofthe magnetic coil in the traditional e-beam column, enabling four columns toarray over the wafer and write simulta-neously. The e-beam in each column isdeflected to a template with cutouts ofvarious shapes so that a specific shapeis projected on the wafer – a technolo-gy known as character projection –without writing individual pixels.

• Multibeam eliminates the magnetic coil,enabling several tens of small columnsto array over a wafer. Each column hasan electron source, blanking/deflec-tion/focus control, an electron detectorfor local alignment and one beam. Eachbeam is vector-scanned (i.e., directed)to pattern line-cuts and holes, inde-pendently and in parallel, one shot foreach cut or hole with no pixel writing.

• KLA-Tencor expects its EBL system to deliver 36 wafers per hour (wph).Advantest has indicated further red-uction of column size to enable 16columns over a 300 mm wafer;throughput data is unavailable. Mapperand Multibeam plan to cluster multiplewriting modules for HVM; a Mappermodule is expected to pattern 10 wphand a Multibeam module five wph. Although advances have been made

in each approach, production systems are

years away, while throughput issues linger:Can EBL reach throughput levels highenough to replace 193i for HVM?

A Different Way to Look at EBLThe semiconductor industry often

expects a new, “next generation” technolo-gy to solve all the problems, meet all main-stream performance metrics and replacethe old technology instantly and complete-ly when making its debut.

Historically, there were indeed “plugand play” new technologies in front-endprocessing. The following are just a few of these techniques: proximity printing(replacing contact printing); 4x reductionoptics for lithography (replacing 1x); plas-ma etching (replacing liquid chemicaletching); and copper interconnect (replac-ing aluminum).

While technology obsolescence is a factof life in our industry, some new technolo-gies co-exist with and complement the oldrather than replace it right away – or ever.The best-known case in semiconductordevices is the complementary metal oxidesemiconductor, or CMOS, which takesadvantage of both p-type and n-type tran-sistors. In chip manufacturing, atomic layerdeposition (ALD), developed in the mid-to-late 1990s, is a good example. ALD is excel-lent in thickness uniformity and step cover-age, but very slow in deposition rate. It hasnot replaced any of the existing, older tech-nologies: thermal oxidation, CVD, PVD.Rather, it complements them with its uniquecapabilities to meet essential processingrequirements. In data storage, hard diskdrive, DRAM and flash drive, commerciallyadopted in the 1950s, 1970s and 2000s,respectively, have performed complementa-ry memory functions in all kinds of comput-ing devices and systems. In the automobileindustry, the gas-electric hybrid car comes



to mind. When multiple technologies worktogether, the end-users benefit.

Thus, it is confining to assess EBL mere-ly in the winner-take-all NGL context. Thisrestrictive view implies EBL is unworthy ofpursuit unless it replaces 193i immediatelyand totally; it also overlooks the uniquecapability of EBL to complement 193i forpatterning the costly and difficult criticallayers. EBL is not NGL, but with the rightapproach, EBL can be an important part of the lithography solution.

1D Layout, ComplementaryLithography and CEBL

To enable manufacture of advancedlogic devices, mainstream fabs are movingfrom conventional 2D layout style to thehighly regular 1D layout style. The 1D layoutpattern is manufacturable today andextendable into the future. It is the ulti-mate form of proactive DFM.

Intel and TSMC have implemented 1Dpoly layers in recent years; other fabs areadopting. Fabricating a 1D layer requiresthe following sequential steps:1. 193i to pattern 1D layout. 193i can print

these grating-like patterns with a singlepass, i.e., single patterning.

2. Spacer technology to increase linedensity. Also known as pitch division,the self-aligned spacer technologydivides the pitch to double, triple orquadruple line density. The process ismature and is implemented with equip-ment in common use in mainstreamfabs and materials compatible withCMOS processes.

3. 193i to print line-cuts with multiplepatterning and multiple cut-masks.Multiple patterning requires multiplecostly cut-masks and complicates thelithography process. The problem willget worse with shrinking features.

Multiple patterning also impacts product development. Developing anadvanced logic chip often involves designre-spins; hence multiple mask sets withcut-masks; and it takes months to proveout a new chip due to design revisions,mask procurement, and chip fabricationand verification. However, more and morechips are used in mobile computingdevices such as smartphones and tablets,and consumer products have short lifecycles and need to drive cost down. Theproblem of high cost and long cycle inchip development is very serious andbecoming more acute.

For economic and technical reasons,and for product development as well asvolume production, another lithographytechnology should be considered for pat-terning line-cuts to complement 193i thatprints the lines – an idea advanced in 2009by Yan Borodovsky, who also coined theterm “complementary lithography.”[6] Ithas since been demonstrated that 193i iscapable of patterning line-cuts down to 16nm, while e-beam is capable of patterningline-cuts at below 14 nm.[7-9]

EBL in complementary use is known ascomplementary e-beam lithography, orCEBL.[10] With the right approach, CEBLcan eliminate all cut-masks, simplify thelitho-graphy process and shorten chipdevelopment time.

CEBL Can Pattern Line-Cuts at High Speed

CEBL can pattern line-cuts quicklybecause in the “lines and cuts” approach,the “lines” and the “cuts” have very differ-ent requirements and tolerances.

The lines define the CD in FEOL andBEOL patterns. The CD is the conductorline width and is important as it may be atransistor gate length (for lines in the gate

E-Beam Lithography Revisited LITHOGRAPHY LANDSCAPE

layer) or the metal line width (for lines inthe BEOL). The cuts have much-simplifiedrequirements, since cuts only have to sepa-rate line segments while providing suffi-cient overlaps for vias and transistor gates.

The lines are patterned with 193i, and193i is a mature technology proven capa-ble of printing lines within tight errorbudgets in line-width control, CDU, overlayaccuracy and LER. In contrast, the end-gapbetween lines and the end-overlap of thevias by the lines are not control parame-ters in a fab. Compared to gate CD control,line-end placement control is much easier.

The cut shape and location are not socritical, either.[11] Figure 1 shows a typicalline pattern (the horizontal rectangles),with a contact or via near the end-gap.The solid green shape shows the nominalsize and location of the cut, but the larger

and smaller dashed shapes denote therange of sizes allowed. In other words, cutshave much larger process latitude thanlines – in shape control and uniformity,placement accuracy and edge roughness.

Further, the pattern density of line-cuts islow, typically 5 to 8 percent. A sparse cut-layer enables highly efficient EBL cutting when shaped beams are vector-scanned to pattern each cut with a singleexposure, i.e., one shot per cut with no pixelwriting, thus skipping more than 90 percentof the wafer where there are no cuts.

By taking advantage of the large toler-ances and sparse patterns, with cut-opti-mized column design and system architec-ture, EBL can pattern line-cuts at highspeed, regardless of the dire throughputprediction extrapolated from historicaldata and observed in Tennant’s Law.

Contact

or via

CD

Figure 1. A ‘Lines and Cuts’ Pattern Illustrating EBL Line-Cutting Having a Wide Process Window



ConclusionWhile EBL development is making

progress, EBL tools are far from being ableto replace 193i for patterning advancedlogic devices with conventional 2D designlayout in production. However, for 1D-lay-out logic devices, with the right design andarchitecture, EBL can pattern line-cuts atthroughput levels compatible with volumeproduction.

EBL line cutting complements opticalline printing, extends optical lithographyand preserves all the advantages of 193i.The 193i-EBL hybrid approach leverages themature capability of 193i and the relaxedtolerances and low pattern-density for e-beam cutting. It is a viable way to scalelogic devices, reduce lithography cost andshorten time-to-market for new products.

The value of EBL lies in its being a keyand complementary enabler for NGL.

AcknowledgmentsThe author wishes to thank Mike Smay-

ling of Tela Innovations; Kevin Monahan of Quantgain Strategies; and E.D. Liu andCong Tran of Multibeam for their contribu-tions.

References 1. D.M. Tennant, Chapter 4, “Limits of

Conventional Lithography,” in Nano-technology, G. Timp, ed., Springer(1999), 164.

2. Chris Mack blog on website www.litho-guru.com, Jan/Feb 2012

3. Timothy A. Brunner, “Why OpticalLithography Will Live Forever,” J. Vac.Sci. Technol. B 21 (2003), 2632-2637.

4. Rius Gemma et al. “Electron- and ion-beam lithography for the fabrication ofnanomechanical devices integrated onCMOS circuits,” MicroelectronicEngineering 86 (2009) 1046-1049.

5. Dan Hung, et al. “Bottlenecks in DataPreparation for Multi-Beam Direct Write,” SPIE Photomask (2011) 8166-76.

6. Yan Borodovsky, “Lithography 2009:Overview of Opportunities,” SEMICONWest, 2009.

7. Michael C. Smayling et al. “Sub-20 nmlogic lithography optimization with sim-ple OPC and multiple pitch division,”SPIE Adv. Lithography (2012) 8326-39.

8. Hideaki Komami et al. “Complementarypatterning demonstration with e-beamdirect writer and spacer DP process of11 nm node,” SPIE Adv. Lithography(2012) 8323-38.

9. Hidetami Yaegashi et al. “Overview:continuous evolution of double-pattern-ing process,” SPIE Adv. Lithography(2012) 8325-11.

10. David K. Lam et al. “E-beam toComplement Optical Lithography for 1DLayout,” SPIE Adv. Lithography (2011).

11. Michael Fritze et al. “High-ThroughputHybrid Optical Maskless Lithography:All-Optical 32- nm Node Imaging,” SPIEAdv. Lithography (2005) 5751.

About the Author

David K. LamDr. David K. Lam is chairman and CEO

of Multibeam Corporation. He is bestknown as the founder and former CEO ofLam Research; he is an investor and advi-sor to high-tech companies. Lam receivedhis Ph.D. from MIT. �


E-Beam Lithography Revisited

PRINTthis article

E-MAILthis article

A roundup of the industry’s topstories in one place

Be notified about our partnerdevelopments and partner events

Sign up NOW

click here

Don’t Miss OutSign up NOW for our FREE newsletter




LITHOGRAPHY LANDSCAPE LITHOGRAPHY LANDSCAPE

IntroductionNext generation lithography techniques

continue to evolve. Therefore, to maintainproduction timelines, extension of ArFimmersion (ArFi) lithography is vital, andsource mask optimization[1] (SMO) is anessential factor in extending ArFi. k1 factorscontinue to be driven downward, evenbeyond the theoretical limit of 0.25 in orderto enable the 22 nm half-pitch (hp) genera-tion. As a result of the extremely smallprocess windows available under thesechallenging conditions, it will be necessaryto implement active techniques that canexpand the process window and increaseimaging robustness; SMO is one such can-didate technique for this. However, pattern-ing at such a low k1 factor involves sensitiv-ities to a myriad of imaging parameters –including illuminator source shape, lensaberrations, process settings and more.

These sensitivities make it imperativethat all of the scanner’s imaging-relatedparameters are quickly controlled withextreme accuracy to make the SMO solu-tions viable on the scanner. A comprehen-sive and efficient solution for optimizingthe scanner’s imaging system setup isrequired.[2,3] The vital elements of thismethod must include freeform pupilgramgeneration, pupilgram adjustment and

optical proximity error (OPE) match-ing,[4-6] as well as thermal aberrationprediction and control.

Freeform Pupilgram GenerationThe results of a source mask optimiza-

tion are usually categorized in a freeformpupilgram, which is more complicatedthan a conventional parametric pupilgram.It is then necessary to generate a pupil-gram on the scanner that is as close tothe SMO solution “target” pupilgram aspossible. Freeform pupilgrams can begenerated using optical elements calledsPUREs, or with an intelligent illumina-tor[7] unit (IIU). The intelligent illuminatoris an actual illumination unit that is config-ured to generate various pupilgrams withan extremely high degree of pupilgramfreedom (DPF), as defined by the numberof grids available in the pupil and the graylevels available for each. The Nikon IIU cansupport 10,000 to 100,000 DPF (Figure 1).The IIU provides a high degree of pupil-gram modulation freedom. This is becauseits high degree of pupilgram freedom cor-responds to heightened pupilgram modu-lation freedom, and therefore increasedaccuracy and homogeneity in the generat-ed pupilgram, which leads to patternsmuch closer to the designed target.

Practical Implementation ofSMO in a Production Scanner

In the case of both the sPURE-based illuminator and the intelligent illuminator,the expected pupilgrams on the scanner are predicted by a pupilgram predictor,[8]which describes the point spread function inthe pupil as a function of the pupil coordi-nates and illumination adjustment parame-ters – including the optical zoom parame-ters in the illumination system. The illumina-tion system optical parameters are opti-mized to make the predicted pupilgramclosely match the target pupilgram. Fur-thermore, the illuminator predictor can alsobe used to determine more robust SMOsolutions by incorporating the predictorresults in the SMO process. In other words,by taking the actual illuminator constraintsinto account, the SMO solutions becomemore robust against them.[9]

Using the IIU, parametric pupilgrams aredefined by parametric values that are input

into the intelligent illuminator, and para-metrically defined illumination intensitydistributions such as x/y pole intensity bal-ance and the open angle of fan-shapedpupilgrams can be modified and demon-strated. Freeform pupilgrams are definedusing grid-based data that is input to theintelligent illuminator. Although the intelli-gent illuminator can generate many kindsof pupilgrams, there are some restrictions.Pupil blur size and pupil fill ratio are themain constraints. These constraints some-times impact imaging performance –including process window. However, bytaking into account the constraints withinthe source (and mask) optimizationprocess, their impact can be minimized.

Pupilgram PredictorTo use pupilgram modulations in a

calculation, it is necessary to predict the

Tomoyuki Matsuyama,1 Martin McCallum,2 Holly H. Magoon3

1Nikon Corporation 2Nikon Precision Europe 3Nikon Precision Inc. PRINTthis article

E-MAILthis article

Figure 1. The Nikon IIU can support 10,000 to 100,000 DPF. Its high degree of pupilgram freedom corresponds to heightened pupilgram modulation freedom, and therefore increased accuracy and homogeneity in the generated pupilgram.




behavior of the physical illuminator underinput adjustments. The most accuratemethod for predicting a pupil distributionwould include ray tracing a model of theillumination system. However, sufficientaccuracy could require millions to billions of rays, and consume tens of hours of calculation time using currently availabledesktop computers. Therefore, an approachthat maintains the accuracy of ray tracing(as judged by imaging fidelity) while reduc-ing the computation time to mere secondswas developed.

This method uses a pupilgram predictor,where the predicted pupil Areticle, describedas a function of the pupil coordinate r, iswritten in terms of an overlap integralbetween the far-field sPURE distributionAsPURE, expressed in the far-field coordi-nate ρ, and the illuminator point spreadfunction, PSF, which depends on both setsof coordinates as well as the illuminator set-tings. The illuminator settings can actuallyrefer to different things for different illumi-nation systems. For example, this may referto the pupil magnification or to some annu-lar ratio adjustment. Since the shape of thepoint spread function changes dramaticallyacross the pupil and through illuminatorsettings, it is generally shift variant. For thisreason, many of the mathematical toolsnormally used to describe linear shift invar-iant systems are not applicable. The NikonPupilgram Predictor provides a solution that is not only accurate, but also quick and computationally inexpensive.

An effective pupil predictor must alsopredict how illuminator-setting changesinfluence the illumination pupil and theresulting images at the wafer, to thereby

enable OPE matching. A study of thechange in OPE with annular ratio that com-pared the illumination pupils described bythe traditional ideal top-hat pupil prescrip-tion, the predicted pupil and the actualmeasured illumination pupil showed thatthe changes in OPE were represented farmore accurately by the pupil predictor thanthe top-hat pupilgram. Figure 2 shows OPEmatching results using the pupilgram mod-ulation freedom of the intelligent illumina-tor. Though this was only a preliminary testof OPE matching using the intelligent illu-minator, the effects of pupilgram modula-tions using the IIU are evident. (Note: Thepupilgrams for this experiment utilizedSMO results assuming a typical SRAM cell pattern.)

Imaging Parameter Optimization for OPE Matching

To utilize the freedom of the intelligentilluminator effectively, application softwarefor OPE matching using a high degree ofpupilgram modulation freedom was alsodeveloped. OPE Master software providesthe following four key functions: OPEmatching; resist calibration; sensitivity cal-culation; and imaging diagnosis. This workwill focus on OPE matching wherein theOPE Master optimizes imaging parametersto minimize the OPE error between a refer-ence scanner and the one to be adjusted.With OPE Master, the user can input pat-tern information, exposed OPE results andoptimizing parameters for the OPE match-ing. A critical component of this software is the use of accurate scanner data. OPEMaster retrieves tool-to-match imaging-related data for more accurate modelingand then sends optimization results back tothe scanner automatically. OPE Master canoptimize pupilgram modulations generatedby the IIU that include Zernike distortion

modulation[10] (ZDM), Zernike intensitymodulation[10] (ZIM), pupil blur size, andbackground flare.

OPE Master provides two calculationmodes. One is a rigorous mode, suitable foroptimization with a relatively small numberof parameters, and is recommended forOPE matching using conventional illumina-tor adjustments. The other is a sensitivitymode, suitable for optimization with a rela-tively large number of parameters and isrecommended for OPE matching using anintelligent (freeform) illuminator. Validationresults using sensitivity mode are shown in Figure 3 with pattern size and pitch innm units identified. Using the same pupil-grams as in Figure 2, the OPE error can bereduced from 2 nm RMS to 0.7 nm RMS. Inthis optimization, ZIM 4, 5, 9, 12, 16, 17, 21,25 and ZDM 3, 5, 13 were modulated, andOPE residuals were markedly improved.

Thermal Aberration Prediction and Control

The remaining key element in makingSMO solutions viable on the scanner is a quick method for thermal aberrationprediction and control.[11] An offlinethermal aberration prediction methodwas developed that begins with pupil-gram measurement using an in-situ toollocated on the wafer table (iPot-inte-grated projection optics tester). Sincethe iPot is located on the wafer side, thepupilgram including reticle diffractioncan be measured directly – thereby tak-ing lens effects into account. Thermalaberration prediction is then performedin seconds using a newly developedhigh-accuracy thermal aberration predic-tor. This is followed by a Zernike sensi-tivity analysis of the thermal aberrationoptimization process for any specific

Practical Implementation of SMO in a Production Scanner LITHOGRAPHY LANDSCAPE

Figure 2. OPE matching results using intelligent illuminator pupilgram modulation freedom. OPE errorsbefore and after adjustment are shown. Notation on horizontal axis indicates pattern dimension (2D,1D), pattern size in nm, pattern orientation (horizontal, vertical), pattern gap in nm for 2D patterns andpattern pitch in nm for 1D pattern.



pattern of mask and illumination pupil-gram, which allows its unique thermalaberration optimization to then be avail-able using the Zernike sensitivity table.The lens controller (LC) parameters aresubsequently optimized based upon theZernike sensitivities obtained earlier inthe process or from the aberrations seton the scanner.

The final phase of this procedure is tofine-tune the thermal aberration controlparameters using the intelligent LC. Oncethe thermal aberration control parame-ters are set on the scanner, a product lotis exposed. During the lot, the intelligentLC measures thermal aberrations includ-ing focus, curvature, magnification, dis-tortion and wavefront aberrations everyfew wafers. Thermal calibration is per-formed and the scanner parameters arefine-tuned based on the measurementresults. Those tuned parameters are then

used for the second and subsequent lots. As a result, the thermal aberrationparameters are automatically optimizedand set on the scanner without requiringdummy heat testing, which takes signifi-cant tool time. Figure 4 shows the bene-fits of the intelligent LC function – usingfocus and spherical aberration parameterfine-tuning as examples.

SummaryNext generation lithography tech-

niques continue to evolve. Therefore, tomaintain production timelines, extensionof ArF immersion lithography is vital,with source mask optimization beingimperative in extending ArFi. Further-more, fast and accurate imaging parame-ter prediction and optimization areessential in realizing the benefits of com-putational lithography. The key technicalelements of success for the scanner

include freeform pupilgram generation,pupilgram adjustment and OPE match-ing, as well as thermal aberration predic-tion and control. This work has demon-strated solutions that meet these require-ments – delivering very high accuracywhile needing significantly less time andcomputational capabilities than tradition-ally employed methods.

References1. A. Rosenbluth et al. “Optimum mask

and source patterns to print a givenshape,” Proc. SPIE vol. 4346 (2001)

2. T. Matusyama et al. “Imaging opticssetup and optimization on scanner for

SMO generation process,” Proc. SPIEvol. 8236 (2012)

3. T. Matsuyama et al. “Application of illumination pupilgram control methodwith freeform illumination,” Proc. SPIEvol. 8326 (2012)

4. S.P. Renwick et al. “Characterizing ascanner illuminator for prediction of OPEeffects,” Proc. SPIE vol. 6154 (2006)

5. J.K. Tyminski and S.R. Renwick, “Theimpact of illuminator signatures onoptical proximity effects,” Proc. SPIEvol. 7140 (2008)

6. Van Look, L. et al. “Tool-to-tool opticalproximity effect matching,” Proc. SPIEvol. 6924 (2008)

Practical Implementation of SMO in a Production Scanner LITHOGRAPHY LANDSCAPE

Focus Drift

Ther

mal

Foc

us D

rift [

µm]

Ther

mal

SA

Drift

[µm

]

Exposure (Heat) Time Exposure (Heat) Time

0.0800.0700.0600.0500.0400.0300.0200.0100.000

Ther

mal

Foc

us D

rift [

µm]

0.0800.0700.0600.0500.0400.0300.0200.0100.000

-0.005

0.000

0.005

0.010

0.015

0.020

0.025

0:00 0:02 0:05 0:08 0:11

Exposure (Heat) Time0:00 0:02 0:05 0:08 0:11

0:00 0:02 0:05 0:08 0:11 0:14

1st Lot

2nd Lot

Spherical Aberration Drift(Pattern-dependent focus difference)

Without LC(Estimation)

Correction Applied by LC

Without LC(Estimation)

Residual

Residual

Residual

Correction Applied by LC

Ther

mal

SA

Drift

[µm

]

Exposure (Heat) Time

-0.005

0.000

0.005

0.010

0.015

0.020

0.025

0:00 0:02 0:05 0:08 0:11 0:14

Residual

Automatic LC Parameter Tuning

Figure 4. A demonstration of intelligent LC tuning capabilities confirms residual thermal aberrations are significantly reduced.

Figure 3. OPE matching results obtained using OPE Master with intelligent illuminator pupilgram modulation capabilities show that OPE error can be reduced from 2.0 nm to 0.7 nm RMS.


FRONT END OF LINEClick here to return to Table of Contents

2012 is a very interesting year so far, astechnologies move forward, with III-V, FinFETand FDSOI showing better performances andadditional functionalities. Variability and con-trols are now essential criteria to move furtherto high-volume manufacturing.

Recently there have been significantannouncements about FDSOI adoption, e.g.,ST-Ericsson describing a new approach regard-ing its next-generation “NovaThor” platform:FDSOI brings extra speed and exhibits best-class leakage, already at 28 nm node. The tech-nical feedback has been further shared withinthe community when such technology hasbeen demonstrated being integrated in arecent tablet: a low-power, high-value proces-sor clocked at up to 1.85 GHz.

At the recent ITRS European meeting heldin Netherlands, FDSOI progresses have alsobeen recognized, and a pull-in by one year isimminent (this technology is supposed to“advance” in 2012 within ITRS tables).

That said, I’m pleased to introduce a dedi-cated tribune to the 28 nm FDSOI-UTBB tech-nology settled by STMicroelectronics and LETIin France. In the Thomas Skotnicki et al. paper,ultra thin body and box (UTBB) technology isdetailed. This is a follow-up story from theFDSOI point of view given by IBM (Bruce Doriset al.) in vol. 41 of Future Fab, which centeredon the thick box approach (145 nm). Then, thetechnical focus was on the UTBB SOI stackallowing unique dynamic Vt modulation with

Yannick LeTiecTechnical Expert, CEA-Leti, MINATEC Campus

an optimized body bias due to the thin buriedoxide (25 nm only). Further, different integra-tion schemes are then possible allowing simul-taneous devices co-integration (hybrid ap-proach on both UTBB-SOI area and on a bulk-like dedicated area). The total power saving ofthe SoC circuits and the circuit speed enhance-ment are well described. The future lookspromising, as the extension of that UTBB tech-nology down to 10 nm looks quite reasonable.

This planar UTBB option seems a very effi-cient way to go compared to the multi-gate(FinFET-like) integration complexity.

ITRS also has significant discussion withinfront-end, yield and metrology working teams.For years, the contribution of airborne molecu-lar contamination (AMC) has been studied, andinvolved mechanisms have been suggested.The project has reached a certain momentumand it’s a good time to spotlight the subjectsince a decent maturity is now recognized.

In the Entegris/LETI paper, the cross-con-tamination transfer phenomena betweenwafers and FOUPs is described, with specificfocus on HF. Contaminant outgassing, the roleof the FOUP atmosphere, adsorption and diffu-sion are discussed, and a comparative study of different FOUP platforms and polymers isreported. Intentional HF contamination is gen-erated to allow a careful study. Very interesting!

I assume follow-up stories of that AMC sub-ject will soon appear relevant, as this is becom-ing a hot topic …

PRINTthis article

E-MAILthis article


7. Y. Mizuno and T. Matsuyama, “Illumina-tion optics for source mask optimiza-tion,” Proc. SPIE vol. 7640 (2010)

8. D.G. Smith et al. “Illuminator predictorfor effective SMO solutions,” Proc. SPIEvol. 7973 (2011)

9. D.G. Flagello et al. “The development of a fast physical photoresist model for OPE and SMO applications from an optical engineering perspective,”Proc. SPIE vol. 8326 (2012)

10. T. Matsuyama and N. Kita, “Tolerancinganalysis of customized illumination forpractical applications of source & maskoptimization,” Proc. SPIE vol. 7640(2010)

11. Y. Ohmura et al. “An aberration controlof projection optics for multi-pattern-ing lithography,” Proc. SPIE vol. 7973(2011)

About the Authors

Tomoyuki Matsuyama Tomoyuki Matsuyama received his

degree in applied physics from the Univer-sity of Electro-Communications in Japan in 1989, and joined Nikon Corporation thatsame year. He has been working in thearea of optical design and manufacturingfor microlithographic lenses, and is cur-rently a manager of the Strategic Imaging

Solutions section for Nikon PrecisionEquipment Company. Matsuyama’s maininterests include aberration analysis meth-ods, system design and optical design of lithographic lenses.

Martin McCallumMartin McCallum is program manager

for the Advanced Lithography and Tech-nology department in Nikon PrecisionEurope, responsible for technologies rang-ing from i-line to EUV lithography. Prior to joining Nikon, he worked on opticalextensions at SEMATECH, and before thatheld a variety of R&D and production rolesat Motorola and NEC. McCallum holds aPh.D. from the University of Edinburgh.

Holly H. MagoonHolly H. Magoon joined Nikon Precision

Inc. in 1995 and has held both technicaland supervisory positions in the Appli-cations department. In 2003, she joinedthe company’s Sales and Marketingdepartment as marketing manager.Magoon received her B.S. in chemistryfrom St. Michael’s College in Colchester,Vermont. �


Practical Implementation of SMO in a Production Scanner

PRINTthis article

E-MAILthis article




Front End of Line



Hitachi High Technologies, Inc. (HHT) is proud to introduce the semiconductorindustry’s highest-volume production etchtool for critical and non-critical etch layers.

The HHT M-9000XT Lynx is a linear pro-duction platform that offers best-in-classthroughput per footprint of any etch clus-ter available to the market. The Lynx plat-form offers a significant advancement inextendibility by integrating from one tonine process chambers, thus allowing theM-9000XT to be configured to meet theexact needs of SC manufacturers. The abi-lity to add process chambers allows the M-9000XT to grow with production capac-ity requirements. Manufacturers can takeadvantage of a small R&D investment byinstalling a single-transport unit module to support one to three process chambers. As the development moves toward prod-uction, the SC manufacturer can add up to two additional transport unit modules,allowing a maximum of nine process cham-bers to support high-volume manufactur-ing (HVM). Flexibility and extendibility arethe advantages to the new Hitachi HighTechnologies M-9000XT.

The HHT M-9000XT is capable of integ-rating different chamber types but the HHTMicrowave ECR or M-XT chamber is the pri-mary chamber for today’s state-of-the-artetch processes. The M-XT plasma etch cham-ber delivers the best etch uniformity, tightestprocess control and highest productivity ofany etch system available to the SC market.

Etch uniformity is the key design concept for the M-XT. HHT retained theMicrowave ECR plasma source and all itsadvantages while redesigning the gasdelivery and evacuation of the chamber to provide superior uniformity of reactivegases reaching the wafer surface andbyproducts being removed from theprocess chamber.

Combining the highest-capability etchchamber with the new ultra-high-through-put platform allows HHT to offer the mostsignificant new etch tool to the SC market.When your fab is ready to shift into highgear, contact Hitachi High Technologies,Inc. to learn more about the possibilities to improve your process and increase yourproductivity with the HHT M-9000XT.

Hitachi High Technololgies suppliesplasma etch systems to the world’sleading SC and HDD manufacturers.HHT customers rely on Hitachi’s tech-nology, innovation and reliability tohelp them succeed in creating today’smost advanced microprocessors, DSPs,memory devices and HDDs. Hitachietch systems are renowned for theirsuperior technology and production-proven reliability in the most demand-ing SC and HDD manufacturing envi-ronments.

Hitachi High Technologies America 1375 N. 28th Ave.Dallas, Texas 75261-22081.877.ECR.ETCHEtch.Sales@Hitachi-HTA.comwww.Hitachi-hta.com

This Future Fab chapter is

sponsored by Hitachi

PRINTthis article

E-MAILthis articleHitachi High Technologies Introduces

the New M-9000XT Lynx Etch System


http://www.future-fab.com/?hitachi42





FRONT END OF LINE FRONT END OF LINE

IntroductionAlready in the early 2000s, due to growing

intensity of short-channel effects (SCE), thescaling down of transistor dimensions turnedout to be less and less productive in drivingCMOS performance. All leading IC manufactur-ers then introduced strain silicon technologiesto boost mobility and thus continue the per-formance growth rate. In the late 2000s, thestrain technologies started to run out of steam,and in addition to lacking performance, otherbottlenecks came into play. Leakage was oneof those, and variability another. Playing withchannel doping had turned out to be difficult,as increased doping reduces leakage but leadsto increased variability. The response the ICmanufacturers put forward was very eous –the untouchable had been touched! Thesacred SiO2 as gate dielectric had beenreplaced by the so-called HK dielectric, andthe polysilicon gate material replaced by ametal. This move was a strong and full of asense of riposte, as it allowed much bettercontrol of the channel by the gate that is ben-eficial for both: leakage and variability.

These are historical wins but, regardless ofhow proud of them we are, they will not helpus now in 2012. Why? Because the continuousscaling down has again led to stagnating per-formance, and to intensification of leakage andvariability. The IC industry has once again

responded efficiently and courageously. Thistime two innovations are simultaneously putforward, both addressing the geometricalstructure of the transistor. One is FinFET andthe second is UTBB SOI. Please note that inaddition to once-again improved SCE and variability, both FinFET and UTBB SOI presentsome specific extra features that no knownbulk technology can match. This point is veryimportant to understand, so let us illustrate itwith the following example.

Suppose we have a magic stick and thusgrant to bulk CMOS the same improved SCE,the same subthreshold slope and the samevariability as those of FinFET or UTBB SOI.Would then bulk match performance of thosetwo? Unfortunately, no, it would not, since inaddition to those improvements, FinFET pro-vides a 3D development of the inversion layerwidth (larger width of the transistor leading toincreased transistor current). UTBB SOI pro-vides a formidable possibility of forward bodybias (FBB). The latter is only possible when the BOX is ultra thin, and then enables a verystrong threshold voltage (VT) reduction that,of course, produces huge transistor currentincrease. Let us have a deeper insight intothese specific features that differentiate Fin-FET and UTBB SOI from all other CMOS tech-nologies, including the conventional FD SOItechnology with thick BOX. But at the first

UTBB SOI: A Wolf in Sheep’s Clothing

step, we will assess the scalability improve-ment due to reduced SCE with FinFET andUTBB SOI, since the magic stick is not there to do so with bulk.

Improved ScalabilityMOSFET scalability is often monitored with

the intensity of drain-induced barrier lowering(DIBL) rather than SCE. Both are given byalmost the same expression,[1] making it easyto understand why FinFET and UTBB SOIshow better scalability. As sown in Figure 1,DIBL depends on simple ratios of transistor geometrical parameters, and two of them,junction depth Xj and depletion depth Tdep,are greatly improved in these structures. TheBOX thickness (Tbox) contributes to the effec-tive depletion depth (Tdep) together with the

silicon thickness (Tsi). It is thus very importantto thin both, if we wish to ensure good scala-bility of any SOI technology. This is why UTBBSOI shows so much improved DIBL and thusscalability in comparison with bulk as well as in comparison with the conventional FD SOI. If the conventional FD SOI works with 145 nmBOX, we can still reduce its DIBL X2 just bythinning the BOX to 10-15 nm (see the insert in Figure 1).

With a particular pride, we would like toemphasis the advantages of thin BOX werefirst seen by ST, FT and Leti R&D teams backin late 1990.[2,3] As thin BOX was not availableon SOI wafers at that time, we developed theSON (silicon on nothing) technology for thispurpose,[2] but continued to enhance the SOI wafer makers to develop and offer UTBB

Thomas Skotnicki,1 Franck Arnaud,1 Olivier Faynot2

1STMicroelectronics, Crolles, France 2CEA-Leti, Grenoble, FrancePRINTthis article

E-MAILthis article

Xj

Tdep Tdep

XjTbox

Xj

Tdep=Tsi+ Tboxwhere <1

Xj 2Tdep

BULK PD SOI FD SOI UTBB SOI FinFET(top view)

Tsi Tsi

Tbox

Tdep=Tsi+ Tboxwhere <1

DSel

dep

el

ox

el

j

ox

Si VLT

LT

LX

DIBL += 2

2

180.0

Xj too largeTdep too largeTyp DIBL

150 mV/V

Xj sameTdep sameTyp DIBL

150 mV/V

Xj betterTdep worseTyp DIBL

110 mV/V

Xj betterTdep betterTyp DIBL

80 mV/V

Xj betterTdep much betterTyp DIBL

60 mV/V

Xj

0

10

20

30

40

50

60

70

80

90

0 20 40 60 80 100 120 140 160

Tbox (nm)

DIB

L (

mV

)

NMOS FDSOI

Tox 1 nm Vdd

1V

Tsi 5 nm Lg 30 nm

Lg 40 nm

Closed symbol: TCAD simulation

Open symbol: MASTAR

Figure 1. Understanding Electrostatics of Different Transistor Structures




wafers. Today we can buy UTBB wafers with Si and BOX thicknesses equal to or even moreaggressive than the SON standards from thelate 1990s.

It is also very important to understand thatin UTBB SOI (also in FinFET), Xj and Tdep areno longer results of doping and thermal pro-cessing, as is the case with bulk. They areexclusively determined by geometry, preciselyby the thicknesses of the SOI film and BOX.Consequently, UTBB SOI can work with un-doped channels (excellent electrostatics isensured by geometry without the need forchannel doping), which is a fundamentaladvantage from the point of view of variability.Indeed, matching factors Avt as small as 1mV.µm have been demonstrated with UTBBSOI, whereas with bulk, the best values read at2 mV.µm. Such a big difference in the matchingfactor may lead to SRAM Vmin difference of150 mV and even more, depending on the sizeof the transistors used (the smaller transistors,

the bigger the Vmin difference). Taking intoaccount that SRAM constitutes a still-growingportion of the SOC ICs, the overall power con-sumption may be greatly reduced thanks tothe reduced Vmin.

These are the true advantages resultingfrom the passage from the conventional FDSOI technology to the UTBB SOI. The mostimportant one resides in the fact that due tobetter coupling through the thin BOX, UTBBSOI enables VT modulation with the body bias,whereas the conventional FD SOI does not.We will discuss this in the next section.

Importance of FBBBoth UTBB SOI and FinFET have their

specific “battle horses” that elevate these twotechnologies above the level of all other ones.FinFET permits more transistor width fromthe unit width of silicon due to developmentof the silicon surface in the 3rd dimension(Fins). UTBB SOI remains flat (constant

width), but thanks to the BOX isolation of thechannel and the junctions from the substrate,it enables large amplitude substrate biasing(forward as well as reverse). In this case, sub-strate is doped under BOX and plays the roleof a second gate that can be independentlybiased. This principle is known from bulk, butthere it was not so efficient. This is becauseon bulk, the substrate bias can merely attain300 mV, otherwise menacing diode-forwardbiasing (or GIDL if reverse BB is considered).On UTBB SOI, we can go up to +/-Vdd andeven beyond with no danger thanks to theBOX isolation. The principles of FBB withUTBB SOI and W development with FinFETare illustrated in Figure 2.

Due to improved electrostatics, the bodyfactor with UTBB SOI is also much better thanwith bulk. The accumulation of the increasedamplitude and improved body factor leads toVT modulation going up to +/-200 mV (seeFigure 3), whereas on bulk, no more than 60mV can be attained.[4]

In the next section, we will show how theFBB boosts the technology speed. Such astrong reduction of VT will lead to a large transistor current increase and thus improvedspeed. But the VT modulation can also beused by designers for additional purposes, e.g., they can use BB in the direction of reversebody biasing RBB, thus enabling huge reduc-tion in the standby power. An example of suchusage is shown in Figure 4, demonstrating upto 99 percent reduction in leakage thanks toRBB with UTBB SOI. Designers can also useRBB permanently as replacement of implanta-tion for adjusting some flavors of thresholdvoltage (e.g., RVT or HVT). The latter is a pre-cious feature, since other FD transistor struc-tures (FD SOI and FinFET) have difficultieswith multiple VT flavor offering.

Preface of the 28 nm UTBB FD SOI Technology

UTBB SOI technology has been put inplace for 28 nm CMOS node for an extra per-

UTBB SOI: A Wolf in Sheep’s Clothing FRONT END OF LINE

WFinFET

>Wsilicon W

FinFET>>>W

silicon

FinFET: Fins

ID

ID FinFET

>ID

ID FinFET

>>>ID

WFinFET

Wsilicon

ID I

D UTBB SOI>I

DI

D UTBB SOI>>>I

D

UTBB FD SOI:BOX

FBB: VT

FBB: VT

const

FBB: VT

Figure 2. Principles of Current Boosting due to VT Reduction by FBB (UTBB SOI), and due to 3D Development of the Transistor Width (FinFET) Figure 3. Measured VT Modulation With Body Bias +/-Vdd on UTBB SOI Transistors



formance boost especially at low operatingvoltage. UTBB technology has been pluggedon the basis of bulk architecture. High-K/metalgate based on gate first architecture is used by adapting metal work function to serve bothN and P type devices. Tow series of VT flavorshave been proposed: a regular-VT to sustainthe low leakage parts and a low-VT for high-speed critical path, so-called RVT and LVT,respectively. To be compliant with already-existing designs developed in bulk technology,a hybrid technology is proposed mixing SOIareas with bulk ones. Regular logic blocks, dig-ital critical paths and SRAM are usually kept on SOI side. Bulk devices as bipolar and diodeshave been implemented on bulk side for ana-log and ESD subcircuits.

Recent silicon data exhibit a significantspeed boost when migrating circuits from bulk

to UTBB SOI. Delay measurement perform-ed on a specific test circuit called LDPC evi-denced a speed increase by more than 90 percent at 1 V (nominal voltage of the node)and more than 450 percent at 0.6 V (seeFigure 5). It is worth pointing out that UTBBtechnology allows an extra speed bumpthanks to the capability of a wide range ofFBB. This dramatic speed improvement at lowvoltage is clearly the main advantage of theUTBB technology. It will help to reduce thepower supply consumption and thus preservethe battery lifetime, so critical for nomad sys-tem as smartphone, tablets and digital camera.

Besides the pure performance boost, thelatest silicon measurements have demonstrat-ed promising functionality for both SRAMarray and logic blocks as standard cells library.More than 30 percent and 50 percent of prime

yield has been observed on high-density cells(0.120 µm2 area) and standard cells, respec-tively. The first review of the Vmin analysishighlighted a gain of more than 100 mV withthe UTBB technology versus the bulk one. Thisbenefit is most likely related to the mismatchfactor improvement coming from the undop-ed thin film channel architecture. This Vmindecreasing will also contribute to the totalpower saving of the system-on-chip circuits.

V. Looking AheadAs UTBB SOI technology provides a signi-

ficant boost in performance for circuits at 28nm, it is mandatory to look ahead in terms ofdevice scaling for 20 nm and below. Scalingrules have been built for these devices, usingcalibrated TCAD tools and already-existing sili-con data. It is seen that by scaling both the sili-

con and the BOX thicknesses, it is possible tomeet the 100 mV/V DIBL targets for CMOSnodes down to 14 nm. Required thicknessesare summarized in Table 1. Thanks to the use of UTBB, it is seen that scaling the BOX signi-ficantly aids the overall scalability of the tech-nology, enabling its extension even down to 10 nm.

Scalability is the necessary condition, butperformance growth is the acceptance con-dition for any future technology. If we haveused improved SCE and moderate FBBalready at 20 nm node, we will need new per-formance boosters at 14 nm and beyond. Amore aggressive FBB usage will certainly beone, but the second one will be incorporationof specific strain boosters. A unique feature of SOI is the possibility of using biaxiallystrained SOI material, which is well known


Standby LeakageBULK LP, LPG vs. UTBB SOI

LVT FF temp 30 @ 0.6VRef

LP B

B -0.3

V

LPG B

B -0.3

V

UTBB S

OI BB -0

.3V

UTBB S

OI BB -0

.5V

UTBB S

OI BB -1

V

UTBB S

OI BB -1

.5V

UTBB S

OI BB -2

V

-51%

-80%-87%

-95%-98% -99%

Standby LeakageBULK LP, LPG vs. UTBB SOI

LVT FF temp 30 @ 0.6VRef

LP B

B -0.3

V

LPG B

B -0.3

V

UTBB S

OI BB -0

.3V

UTBB S

OI BB -0

.5V

UTBB S

OI BB -1

V

UTBB S

OI BB -1

.5V

UTBB S

OI BB -2

V

-51%

-80%-87%

-95%-98% -99%

Figure 4. Leakage Reduction With RBB on UTBB SOI Technology

Freq

uenc

y, A

U0.4 0.6 0.8 1.0

Vdd, V

+450%

Bulk

Vdd FBB

No FBB

+91%

1.2 1.4 1.6

Vdd/2 FBB

UTBB

Figure 5. LDPC Circuit Speed Enhancement Thanks to UTBB Technology (silicon measurement)



for its capacity to boost the electron mobili-ty.[5] Gains from 35 percent to 100 percent on the NMOS drive current have already beenreported on wide and narrow devices, respec-tively (Figure 6).

ConclusionsBoth UTBB SOI and FinFET have excel-

lent prospects for providing CMOS platforms

enabling Moore’s Law continuation through-out several future nodes and most likelydimension scaling beyond the 10 nm limit.We think they will co-exist as CMOS leadingtechnologies, as due to the course of scaling,their geometrical structures converge. If we consider the UTBB SOI substrate (belowBOX) as the second gate, a bird’s-eye viewon FinFET makes one see something veryclose to the cross-sectional view of UTBBSOI (see Figure 1). In addition, the differencewill diminish more and more in the course ofscaling along with the BOX thickness reduc-tion. This ultimately means hat both shouldhave similar scalability limits.

Regarding the UTBB SOI that is the ST choice, we can conclude by saying thistechnology is particularly suited for LP SOC

products for mobile multimedia applications.We have demonstrated its scalability for atleast three technological nodes, and have a roadmap guaranteeing its performancegrowth (at low consumed power) more rapidly and being beyond reach of any conventional technology. At the same time,UTBB remains planar and requires fewerprocess steps than any bulk technology(fewer implantations, fewer isolation prob-lems to be coped with, etc.). This is why webelieve UTBB SOI is like “a wolf in sheep’sclothing” and thus will provide a high-per-forming and cost-effective platform for ourcustomers’ LP mobile multimedia productsas well as other digital and mixed-signalproducts.

References1. T. Skotnicki et al. “Innovative materials,

devices, and CMOS technologies for low-power mobile multimedia,” IEEE,Transaction on Electron Devices, pp. 96-130, vol. 55, January 2008

2. M. Jurczak et al. “SON (Silicon OnNothing) – an innovative process foradvanced CMOS,” IEEE, TED, pp. 2179-2187, November 2000

3. C. Fenouillet-Beranger et al. “Require-ments for ultra-thin-film devices and newmaterials for the CMOS roadmap,” Solid-State Electronics, vol. 48, No. 6 pp. 961-7,Elsevier, UK, June 2004

4. F. Andrieu et al. “Low Leakage and LowVariability Ultra-Thin Body and BuriedOxide (UT2B) SOI Technology for 20nmLow Power CMOS and Beyond,” VLSI conference 2010

5. J. Mazurier et al. “High Performance andLow Variability Fully-Depleted Strained-SOI MOSFETs,” Proceedings of IEEE SOI Conference, pp. 46-47, 2010

About the Authors

Thomas Skotnicki – Prof. Dr. Skotnicki is the STMicroelectronics and IEEE Fellow and director of Disruptive Technologies atSTMicroelectronics, Crolles. He has madesignificant contributions to UTBB SOI tech-nology, thermal energy harvesting andnumerous other technologies (SON, TOSI, 1T DRAM, NDR devices, etc.). Prof. Dr. Skot-nicki’s MASTAR models have served for ITRSRoadmap calculations. He has supervisedmore than 25 Ph.D. theses, holds about 60patents and has published more than 350scientific papers.

Franck Arnaud – Mr. Arnaud received hisMaster diploma from the Superior School of Electricity of Paris University in 1994. Hestarted his career at STM in 1995 with CMOS0.35 µm technology as a device expert, andbecame a technical manager in 0.12 µm and65 nm technologies. He spent two years inFishkill as part of the IBM Alliance as a 32nm device manager. Mr. Arnaud is now the28 nm program manager for STM in Crolles,France.

Olivier Faynot – Dr. Faynot received his M.Sc and Ph.D. from the Institut NationalPolytechnique de Grenoble, France in 1991and 1995, respectively. He joined CEA-Leti in 1995, working on simulation and modelingof deep micron fully and partially depletedSOI devices. Since 2011, Dr. Faynot has been responsible for Leti’s Microelectronic component section. He has authored or co-authored over 140 scientific publicationsin journals and international conferences. �



PRINTthis article

E-MAILthis article

-11

-10

-9

-8

-7

-6

0 250 500 750 1000 1250

+100%

sSOI

+35%

SOIClose: W = 0.5 µm

Open: W = 80 nm

I OF

F (

A/µ

m)

(VD=

0.9

V)

ION

(µA/µm) (VD= V

G= 0.9V)

Figure 6. NMOS Device Performance Improvement With Strained SOI Material

28 nm 20 nm 14 nm 10 nm

TSOI (nm) 7 6 5 5

TBOX (nm) 25 18-20 15 7-10

Table 1. Silicon and buried oxide thicknesses for28, 20 and 14 nm nodes are required to keepDIBL below 100 mV/V.




FRONT END OF LINE FRONT END OF LINE

AbstractCritical dimension of a microelectronics

chip shrinking to nano-scale renders AMCscross-contamination transfer phenomenabetween wafers and FOUPs a bigger issue.So it has become imperative to understandthe physics and chemistry behind the con-tamination mechanism in order to developthe appropriate methodologies and solu-tions. In this context, Entegris & CEA-Letihave established a joint collaboration to per-form molecular contamination studies underrealistic production conditions. First resultsregarding a comparison between differentEntegris FOUP platforms are presented inthe case of a critical contaminant: the HF.

IntroductionWith the development of IC technolo-

gies, new materials are introduced andprocesses become more complex. Clearly,new materials imply new contaminationissues to manage and to avoid. On theother hand, new methodologies in waferproduction lead to new types of containers(i.e., FOUP, FOSB) and new approaches ofcleaning and managing them. In particular,airborne molecular contamination (AMC)as well as the cross-contamination issuesemerging from the interaction between the

clean-room environment, the process toolmini-environment and the FOUP-wafer sys-tem need to be addressed due to defectiv-ity occurrences and yield losses generated.

The AMC cross-contamination schemefrom FOUP to wafer has been clearly evidenced for organics[1] and volatileacids[2-4] by works developed at CEA-Letithese last years. The contamination chaincan be described as follows: 1) Contaminants are outgassed from just

processed wafers (etching, stripping,wet cleaning processes ... ) in the FOUPatmosphere and then sorbed by theFOUP materials, which behave as con-taminants traps. This sorption is gov-erned by the surface adsorption of mol-ecules followed by their diffusion intopolymer bulk.

2) With wafer removing, the FOUP atmos-phere is suddenly changed, and reversediffusion and outgassing from FOUPmaterials to FOUP atmosphere occursin order to reach steady concentrationsbetween FOUP’s surface and atmos-phere. In the same way, the storage ofnew wafers sensitive to outgassed con-taminants by FOUP leads to contamina-tion transfer from FOUP to air, and fromair to wafers.

FOUPs Polymers AgainstAMCs: The HF Case

These sorption processes (i.e., adsorp-tion and diffusion) and reversible out-gassing (i.e., reverse diffusion and release)are long-term phenomena (several days/weeks) kinetically limited by the moleculardiffusion.

As the materials science and contami-nation control expert, Entegris knows how the advance in the manufacturingtechnologies renders water and oxygen in the air detrimental (causing i.e., corro-sion) and has worked in water and/or oxy-gen permeation resistance of the carrier’spolymer materials,[5] looking for the nextgeneration of microenvironments suita-bility.

Today one consideration in the selec-tion of an AMC control system should bean assessment of the type and quantitiesof AMC to be controlled. SEMI Standard F-21-11023 classifies AMC in clean rooms bytheir chemical properties, providing a wayto characterize the environment by groupsof molecules that could have similareffects on an exposed wafer.

In recent years, one AMC, the HF, hasgarnered more and more attention. TheHF cross-contamination was clearly iden-

tified as one major root cause of Cu, Al or poly-Si corrosion or TiFx crystalgrowth on TiN layers.[3,4,6] To reducewafer losses resulting from airborne con-tamination, the yield enhancement com-mittee of the International TechnologyRoadmap for Semiconductors (ITRS)annually publishes a guideline to detailthe tolerable concentrations for variousairborne contaminants in each technol-ogy node.[7] For example, in its yieldenhancement roadmap, there is a strin-gent specification for the HF levels in Cu-or Al-exposed wafers inside FOUPs of 5ppbv (corresponding to <1 x 1014 of fluo-ride ions/cm2 on the wafer over 24 hours).

In this work, Entegris and CEA-Leti hasshared its high-level technical compe-tences in the study of the contaminationprocess. We carried out a comparativestudy of different FOUP platforms andpolymers in order to quantify their abilityto be contaminated by HF and to subse-quently release this molecule. To reach thispurpose, FOUPs were intentionally con-taminated by HF vapors and then the sub-sequent desorption of HF concentrationswas monitored inside FOUPs.

Paola González-Aguirre,1,2 Hervé Fontaine,1 Carlos Beitia,1

Jim Ohlsen,2 Jorgen Lundgren2

1CEA-Leti, MINATEC Campus 2Entegris Inc., France

PRINTthis article

E-MAILthis article

FOUP FOUP Shell Wafer Side Inner Door Wafer Tested Platform Material Capacity Columns Material Planes Material Material

“EBM/CNT” A300TM EBM/CNT 25 EBM/CNT EBM/CNT EBM/CNT

“EBM” Spectra™ EBM 25+1 EBM EBM/CNT EBM/CNT

“PC” Spectra™ PC 25+1 PC PC/CP PEEK/CF

“PC/CP” Spectra-S™ PC/CP 25+1 PC/CP PC/CP PEEK/CF

“PEI” Spectra™ PEI 25+1 PEI/CNT PEI/CNT PEEK/CF

“PEI/CNT” Spectra™ PEI/CNT 25+1 PEI/CNT PEI/CNT PEEK/CF

EBM: Entegris Barrier Material PC/CP: STAT PRO® 500 carbon-filled PCCNT: carbon-nanotubes PEI: polyetherimidePC: ultrapure polycarbonate PEEK/CF: carbon fiber polyetheretherketone

Table 1. FOUP’s Materials




ExperimentalFOUPs and Polymers Materials Tested

The containers tested were new com-mercial Entegris FOUPs. Six differentFOUPs platforms/materials from Entegriswere tested. These FOUPs are presented inTable 1.

FOUP’s Intentional Contamination of HF, Purge and Outgassing Stages

All FOUPs were first conditioned atclean-room conditions (21 °C, 40 percentRH). To study FOUP contamination by HF, a 10 µL droplet of HF 2 percent is deposedin a PTFE cup, then placed into the FOUPand allowed to evaporate for 24 hours.Considering the FOUP volume (28 liters),the full evaporation of the droplet leads,theoretically, without sorption or leak, to9.2 ppmv of HF in air. Then, a purge step isperformed with a nitrogen gun for five min-utes followed by an “outgassing stage” forone week. All through the contamination

and outgassing phase, the airborne concen-tration was monitored via impinger-IC (ionchromatography). Each kind of FOUP wastested in duplicate. Figure 1 describes thegeneral experimental procedure.

Results & DiscussionDuring the contamination event, meas-

urements of airborne HF concentrationspresented in Figure 2 shows levels quitelower than the 9.2 ppmv maximal theoreti-cal HF level (corresponding to the totaldroplet evaporation). As we can reasonablyconsider that leaks are not a major contri-bution, this characterizes the effectivesorption of the contaminant. Moreover, sig-nificant differences of HF concentrationsare observed at short contamination time(from ~2,000 to ~50 ppbv after four hours)depending on the different constitutivematerials, and it is possible to establish theHF affinity for different FOUP polymers atshort contamination time (four hours afterthe intentional contamination). This HFsorption can be ranked as: PEI/CNT ~ PEI >PC/CP > PC > EBM > EBM/CNT. Neverthe-less, after 24 hours of the contaminationevent, all materials present a quasi-totalsorption (HF levels <33 ppbv).

Once the FOUP atmosphere is purged,a reverse molecular diffusion and out-gassing is promoted. Indeed, one canconsider that purge “desorbs” moleculesat the polymer surface, and this leads toa strong inverse concentration gradientof contaminants into the polymer materi-al that promotes molecular diffusionfrom the core to the surface and there-fore contaminant outgassing. Just afterpurge, an expected increase of HF levelsin FOUPs is observed, showing the out-gassing from FOUP materials asdescribed before. Second, a slowdecrease of HF levels follows, correspon-

ding to a slow balance between materialand airborne concentrations. In fact, itcan be assumed that the diffusionprocess continues in all the thickness ofthe polymer wall until the concentrationgradient near the surface becomes verylow, allowing it therefore to reach relativesteady HF levels both at the surface andin the atmosphere of FOUP.

As can be seen in Figure 2, the FOUPin PC material presents a strong out-gassing just after the purge step and sig-nificant levels of HF for short outgassingtimes (few tens ppbv during the first 72hours). One can notice that such levels

are quite representative of HF concentra-tions already measured in FOUPs used inmicroelectronic fabs.[4] On the otherhand, EBM and PC/CP materials presentlow outgassing rates at short times.Finally, in the case of PEI, EBM/CNT andPEI/CNT FOUPs, little to no detectablelevel (<0.6 ppbv) of HF outgassing wasobserved.

These results lead us to foresee that the HF cross-contamination and then itspotential impact is strongly dependent onthe FOUP polymer considered; namely, PC >> PC/CP ≥ EBM >> PEI ≥ PEI/CNT ≥EBM/CNT.

FOUPs Polymers Against AMCs: The HF Case FRONT END OF LINE

Figure 1. Description of the Intentional HF con-tamination, purge & impinger monitoring Figure 2. Sorption/Outgassing Profiles Observed in Entegris FOUPs


Front End of Line



Semiconductor manufacturing process-es require a contamination-free fab envi-ronment for process optimization and opti-mum yield. Particles generated duringwafer processing by tool actuation, waferhandling or process irregularities contributeto wafer defects. Reducing or eliminatingthe presence of particle contaminants is animportant step in tool qualification.

Handheld particle counters offer limitedreach inside equipment and little or no infor-mation about the location of contaminationin the tool. Although capable of real-timeparticle detection, they cannot operate underactual wafer conditions or measure the entirewafer path. Other popular particle-countingmethodologies require partitioning, with indi-vidual units sent to each individual chamberand/or tool location to isolate the source ofthe particle contamination.

Addressing these issues, CyberOpticsSemiconductor developed the WaferSense®

Airborne Particle Sensor (APS) that candetect particles down to 0.1 micron withoutopening the tool and automatically reportthe presence of airborne particles.

Representing a significant change inparticle-detection methodology, the APS

enables engineers to really monitor andcontrol contaminations in their tools andprotect die yield – with real-time views ofparticle conditions to address areas of concern instead of the whole tool.

Follows Wafer PathWith a waferlike shape, the sensor can

move through semiconductor processequipment and automated material-han-dling systems to monitor airborne particleinside the systems under actual productionconditions. And the APS can go deepinside a tool and communicate data unlikehandheld particle counters whose range islimited by hand reach and require openingthe tool.

Faster Monitoring of Process Chambers

When fabs must qualify multiple toolswithin process chambers, the APS canprove faster and less laborious in operationthan other particle monitoring methods,which can result in reduced qualificationtime. One APS can travel to multiple areasin a process chamber and more quicklymeasure numerous combinations of poten-

WaferSense® Airborne Particle SensorRepresents Significant Change in FabParticle Detection Methodology

PRINTthis article

E-MAILthis article


ConclusionA comparative study of Entegris FOUP

platforms/materials to sorb and to subse-quently outgas HF have been carried outby intentional controlled contaminationexperiments. Results show the differentability of the polymer materials to sorband desorb the HF molecule. In the case ofHF sorption at short contamination times,we can rank the sorption capacity asPEI/CNT ~ PEI > PC/CP > PC > EBM >EBM/CNT. Regarding the outgassing abilityof different Entegris FOUP polymers, threedifferent behaviors are well identified. First,high outgassing is showed in PC FOUP.Then, medium outgassing characterizesEBM and PC/CP FOUPs. Finally, little to nodetectable outgassing is observed for PEI,EBM/CNT and PEI/CNT FOUPs.

These results will be very useful toassess the relevance of preventive orremedial strategies in fabs for the FOUPchoice. In particular, regarding the impactof this outgassing in storage wafers, wecan assume that PEI/CNT and EBM/CNTwill easily follow the ITRS statements forthe HF levels in Cu- or Al-exposed wafersinside FOUPs, while PC/CP and EBM mustreach the limit levels. To confirm theseexpected results, further work is ongoingon exposed wafers in terms of contamina-tion transfer, and it will be published in afuture communication.

References1. H. Fontaine et al. “Study of the volatile

organic contaminants absorption andtheir reversible outgassing by FOUPs,”Solid State Phenomena, vols. 145-146,pp. 143-146 (2009)

2. H. Fontaine and M. Veillerot, “Plasticcontainers contamination by volatileacids: accumulation, release and trans-fer to Cu-surfaces during wafers stor-

age,” Solid State Phenomena, vol. 134,pp. 251-254 (2008)

3. H. Fontaine et al. “Impact of the volatileacid contaminants on Cu interconnectselectrical performances,” ECS Transac-tions, vol. 25 (5), pp. 79-86 (2009)

4. T.Q. Nguyen et al. MicroelectronicEngineering, in press (2012)

5. C.W. Extrand, Semiconductor Fabtech,vol. 3, No. 43 (2008)

6. Cabuil N. et al. Solid State Technology,pp. 48-51 (2007)

7. International Technology Roadmap forSemiconductors (ITRS), YieldEnhancement, 2011, www.itrs.net.

About the Authors

Dr. Paola González-Aguirre – Entegrisengineer application developmentassignee to CEA-Leti

Dr. Hervé Fontaine – leads metallic andmolecular contamination characterizationand its impact study, Silicon Technologydepartment; CEA-Leti

Dr. Carlos Beitia – metrology manager,Silicon Technology department; CEA-Leti

Dr. Jim Ohlsen – director, MaterialsCharacterization group, Entegris Inc.

Jorgen Lundgren – application engineer,Microenvironment BU; Entegris GmbH �


FOUPs Polymers Against AMCs: The HF Case

PRINTthis article

E-MAILthis article




Front End of Line



tial particle source elements. There is noneed to open chambers. And just one tech-nician is required to operate the airborneparticle sensor.

Isolation of Particle Contaminate Sources

Sometimes, a fab has difficulty deter-mining “when” and “where” monitor wafersbecame contaminated. By following thepath of a wafer – as it is transferred, slitvalves actuate and chambers cycle – theAPS can identify particle counts at eachstation and along connecting paths to helpequipment engineers quickly locate whenand where the source of particles originate.The APS is also ideal for some new particlequalification protocols that require theentire path of the wafer be monitored

rather than just performing spot checks ineasily accessible tool locations.

Real-Time Feedback and Corrective Action

Using a Bluetooth wireless radio link toupload measurements in real time, the APSallows users to see what is happening withthe in-tool air contamination, second bysecond, as it is happening. Companionsoftware collects and display particle datawirelessly to see the effect of adjustmentsin real time, speeding equipment qualifica-tion and setup.

Diverse Front-End Tool Applications

While the APS cannot be used undervacuum conditions for final qualification,the wireless sensor can be used to quicklyqualify atmospheric front-end tools such ascoater/developer tracks, thermal diffusion,deposition, etch equipment and material-handling systems, to speed their release to production.

To see how the WaferSense® productsfit into your processes, click here or con-tact the company at [email protected] or 800.366.9131.

CyberOptics offers on-site evaluationsof its WaferSense® metrology sensors –within your fab and using your equipment –to show how our technology can improvethe productivity and cost efficiency of yourelectronic assembly operations.

Mark HannafordDirector of Sales

Business Contact

Lindsey DietzInside Sales and Marketing

Phone 503.495.22171.800.366.9131Fax [email protected]

CyberOptics Semiconductor, Inc. 9130 SW Pioneer Ct., Ste. DWilsonville, OR 970701.503.495.2200www.CyberOpticsSemi.comCSsales@CyberOptics.com

Our Commitment to Innovation

Manufacturers across the globe use the advanced measurement toolsoffered by CyberOptics Semiconductorto reach their semiconductor yield andequipment uptime goals.

Our wireless set of advanced meas-urement solutions for leveling, gap-ping, vibration/particle detection andteaching semiconductor equipmentcan be used separately or together toincreases fab effectiveness, fine-tuneexisting equipment and reduce overallprocess costs.

CyberOptics Semiconductor keepsyou ahead of the curve with cutting-edge technology that addresses thelimitations of today while preparing forfuture process requirements.

CyberOptics Will Discuss ToolQualification Capabilities ofWaferSense® Airborne ParticleSensor at Semicon West 2012 in Booth No. 2406

PRINTthis article

E-MAILthis article


http://www.future-fab.com/?Cyber42



http://www.future-fab.com/?Cyber42

BACK END OF LINEClick here to return to Table of Contents

In the first paper of this section, Uhlig et al. describe the collaboration between the Fraunhofer Center for NanoelectronicTechnologies and GLOBALFOUNDRIES tobridge the gap between university researchand mainstream production. They point outthat accomplishing the integration of allsteps within a given processing module iskey to addressing this gap.

They describe two examples of their col-laboration. In the first, they successfully devel-oped a process to restore the effective k-value for ULK materials affected by post-dep-osition processing. Their second describes anew CVD cobalt barrier process developed asa replacement for conventional PVD Ta andTaN processes. The new process addressesthe film conformality issues associated withPVD barriers for sub-28 nm CMOS nodeswhile maintaining the reliability required.

In the second paper, Zimmerman et al.discuss another collaboration betweenFraunhofer CNT and GLOBALFOUNDRIESthat developed a new etch process that minimizes the damage caused to ultra-low-kSiCOH films within an integrated dama-scene process module, plus a post-process-ing clean and k-value repair step.

Jon CandelariaDirector, Interconnect and Packaging Sciences; SRC

They begin by discussing the metrologytechniques they used (quantum cascadelaser absorption spectroscopy) to correlatetrench sidewall damage to varying process-ing conditions.

They continue by describing a detailedanalysis of the surface wetting behavior for deeply scaled damascene dielectric sur-faces. The difficulties in obtaining sufficientwetting at such patterned dimensions withnanoscale dielectric pores were addressedwith non-ionic surfactants, and an opti-mized process was developed and trans-ferred to 12” production equipment.

Finally, a promising low-temperature,remote plasma technique is described asan alternative to wet chemical silylation.Such wet processes have shown limitedeffectiveness because of their inability to penetrate deeply enough within thenanoporous films to avoid repairing onlythin surface layers, and therefore achievelimited repair capabilities. The ability topenetrate sufficiently deep as well as main-tain low temperatures and optimum ambi-ent conditions differentiates this new in-situremote plasma repair process from allother alternatives.

PRINTthis article

E-MAILthis article


BACK END OF LINE

Abstract With further miniaturization, new

materials and ever-increasing complexitydemands consideration of adjacentprocess steps. Furthermore, research hasto be as close as possible to productionrequirements. The BEOL module at theFraunhofer CNT enables this special kindof applied research. Examples for two keytopics are presented. Important parame-ters such as RC delay and leakage couldbe improved by low-k restoration andcobalt barrier layers of high-quality weredeposited by a CVD process.

IntroductionUpon looking at research in the semi-

conductor technology area, two differenttypes can be classified. On the one hand,there is basic research mainly done at uni-versities or research institutes, where manyinteresting approaches and ideas emerge.New materials are studied and basicunderlying mechanisms and parameterdependencies can be obtained. However,results are not transferable to productionand only a fraction of these new develop-ments is later used in future technologies.

On the other hand, directly at the IC man-ufacturers and foundries, there is the more

direct, result-oriented approach, where fac-tors like process time and cost play a crucialrole. Production-relevant issues like contami-nation risks, defectivity, yield, repeatabilityand process stability, uniformity and queue-time are especially important. Often, thiscomes with a lack of time, manpower or toolavailability for research topics; usually, “pro-duction comes first.”

The concept of applied research tries tobridge this gap. The goal is to take ideasof processes and materials from basicresearch to a productionlike environment.Issues like tool design, contamination,clean-room quality and productivity-relat-ed factors (cost, time, yield, defects, etc.)are addressed.

At Fraunhofer CNT, this is realized onstate-of-the-art 300 mm tools at leading-edge critical dimension node of 28 nmtechnology. Fast short loops and learningcycles with an established foundry (GLOB-ALFOUNDRIES) enable high-value data onnew processes and process improvements.Preprocessed wafers come directly fromthe foundry, and single processes or wholeintegration modules are developed in an industrylike environment at the CNT.Extensive in-line metrology and PFA analysis can be done very fast in-house.

The Bigger Picture: FraunhoferCNT’s BEOL Applied Research

Benjamin Uhlig, Lukas Gerlich, Romy LiskeFraunhofer Center Nanoelectronic Technologies

PRINTthis article

E-MAILthis article





Afterward, the post-processing and furthercharacterization (e.g., electrical data) iscarried out at the foundry. Then, a compar-ison regarding the final device perform-ance can be done with the existingfoundry-only POR.

For many process steps, such as inBEOL, it is no longer sufficient to look atsingle-process development and optimiza-tion. Instead, the whole integration flow ofone metal layer, starting from the ILD dep-osition, over the patterning, liner and bar-rier deposition and metal plating up tochemical mechanical polishing needs to be addressed. For example, etch processesthat might produce less ULK damage alsoneed to be checked against removal of anysidewall-protecting polymers afterward,adhesion and barrier integrity of the TaNliner or possible resist poisoning throughnitrogen species. Similarly, changes in thepost-etch clean step influence the subse-quent liner deposition, e.g., in the case ofdilute HF clean, which may lead to a hardmask undercut and therefore complicatesthe resulting TaN liner deposition. Changesfor the electrochemical copper deposition,such as different additives, might influencethe CMP dishing and erosion, and so on.

Therefore, it is important to have theaccessibility to multiple process steps –

ideally a whole module – for integratingcomplete metal layers. Additionally, impor-tant queue-time effects – e.g., any barrieroxidation right before the copper plating –show the need of broadening the numberof attributed processes.

K-Restoration for Electrical Improvement

Etching and ashing of ULK materialsresults in the degradation of trench and viasidewalls by removing methyl groups anddensifying the porous material. Currentapproaches to this involve a selectiveremoval of these SiO2-like layers by dilutedHF. While this improves the effective k-value, it introduces other effects such asCD changes or hard mask undercuts,which in turn affect later process steps.

Wafers processed up to metal 2 litho-graphy have been prepared at GLOBAL-FOUNDRIES. Etching was done at CNT andthe trenches and vias have been treatedpost etch by a silylation process to restorethe k-value. First, an annealing step securesremoval of adsorbed water. The silylation,done on a Semitool Raider platform, follows,and is enhanced by a subsequent UV andheat treatment step. Finally, a wet clean toremove any residues ensures clean trenchand via sidewalls and bottoms.

Figure 1. The BEOL Module at Fraunhofer CNT for Applied Production-Related Research

The Bigger Picture: Fraunhofer CNT’s BEOL Applied Research BACK END OF LINE

Wafers were further processed in theCNT up to the copper plating and thensent to GLOBALFOUNDRIES for the finalmetal layers and electrical characteriza-tion. Figures 2 and 3 show key electricaldata of the wafers processed with therepair step in comparison to wafers run-ning through the fab with the POR. TheRC delay clearly shifts to lower values; atotal improvement of about 14 percent in

RC reduction could be achieved. Similar-ly, the leakage of the metal lines can belowered in comparison to the POR.

Cobalt CVD as an Alternative Barrier Process

Due to feature shrinking for futurenodes, traditional barrier deposition of Taand TaN by PVD will face more and moreproblems in terms of conformality issues

Figure 2. RC Plot of Metal 2 Layer FromConventional Fab POR and Low-K RepairProcess at CNT

Figure 4. Cobalt 2p XPS Spectra: Oxidation ofCobalt Barrier Under Cleanroom Atmosphereand Reduction Back to Metallic Cobalt by H2Degas Treatment

Figure 5. Carbon 1s XPS Spectra: Reduction inCarbon Content of Cobalt Barrier by AnnealingTreatment

Figure 3. Nominal Via Leakage of Metal 2 LayerFrom Conventional Fab POR and Low-K RepairProcess at CNT



and process reliability. A promisingapproach is barrier deposition by CVD.At Fraunhofer CNT, a cobalt precursor(CTTBA) was selected to develop acobalt CVD process. Porous SiCOHwafers were used and a thin TaN layerwas deposited by PVD as dielectric barri-er in an Applied Materials Endura clustertool. Afterward, thin cobalt layers weredeposited in a CVD chamber and the elemental composition was measured inan in-situ XPS system. Comparison withwafers exposed to clean-room atmos-phere showed that there is formation of a cobalt oxide layer, which can bereduced back to metallic Co by an addi-tional H2 degas treatment (see Figure 4).The issue of carbon contamination inher-ent to organic precursors can be greatlyreduced by a post-deposition annealstep, as is seen in Figure 5.

ConclusionResearch for future technology nodes

requires more and more focus on multi-ple process steps and whole integrationmodules. For ever-increasing processcomplexity and new materials, it is nec-essary to take a more critical look atpossible innovations.

Hence, a binding link between basicresearch and the actual consideration ofin-fab process-of-record change is need-ed. Important issues like contaminationrisks, defectivity or process complexitymust be considered. At Fraunhofer CNT,such an environment exists, and the concept of applied, production-relevantresearch in the back end of line is shownfor two exemplary cases.

First, it is presented that it is possible toreduce key parameters like RC delay andleakage by introducing a silylation step forrestoration of the k-value post-ULK etch.

Results could be shown in comparison toan in-fab POR to yield a reduction of 14percent for the RC product.

Secondly, it could be demonstratedthat novel cobalt barriers can be deposit-ed with high conformality by CVD. Pro-cess improvements to obtain high-qualitymetallic cobalt layers are proposed. Thedeposition by CVD enables thin, smoothlayers in narrow high aspect ratio trenchstructures, which may not be achievableby the traditional Ta/TaN PVD approachfor future nodes <28nm.

Acknowledgments The authors wish to thank GLOBAL-

FOUNDRIES for their support, wafer supply and electrical characterization.The work described in this article wasdone within the projects Structure andNoLimit, which have been funded in linewith the technology funding for regionaldevelopment (ERDF) of the EuropeanUnion, and by funds of the Free State of Saxony, Germany.

About the Authors

Benjamin UhligBenjamin Uhlig received his Ph.D.

in 2010 during his work at QimondaDresden about laterally resolved stressmeasurements. Since then he has beenworking in the Back End of Line group atFraunhofer CNT, with special emphasizeon ULK etch, clean and restorationprocesses.

Lukas GerlichLukas Gerlich received his diploma

degree in chemical engineering forEFTEM tomography studies at AMD,

The Bigger Picture: Fraunhofer CNT’s BEOL Applied Research

Dresden in 2006. He has been working in the field of barrier films for Cu-metal-ization and in-situ XPS analysis since2007 at Fraunhofer CNT, and submittedhis Ph.D. thesis in 2012 at BTU Cottbus.

Romy LiskeRomy Liske received her Master of

Science degree from Michigan StateUniversity in 2005. With her work on kin-etics in the electrochemical copper dep-osition process, she received her Ph.D.from Dresden University of Technology in 2011. She has been working at theFraunhofer society since 2001, and iscurrently heading the Back-End of LineTechnologies group at Fraunhofer CNT in Dresden. �


PRINTthis article

E-MAILthis article




BACK END OF LINE BACK END OF LINE

Abstract This paper describes the development

of a multi-step process regime for the inte-gration of porous SiCOH in existing copperdamascene technologies down to the 28nm technology node. It focuses on a less-er-damaged etch process followed by aresidual-free cleaning step and an effectivek-value repair method. The work demon-strates at a glance the current state ofultra-low-k integration in the semiconduc-tor industry and delivers some startingpoints for further developments.

IntroductionThe integration of the porous ultra-

low-k material SiCOH results in specialchallenges concerning the further scalingof interconnects dimensions. Generally,such materials will be patterned usingreactive ion etching (RIE) with fluorocar-bon plasmas.[1] During RIE integrationprocesses the SiCOH material will be dam-aged resulting in an undesirable increase inits k-value.[2] Regarding the etch trenches(Figure 1), this effect causes a seriousincrease of the line-to-line capacitancesand also an enhanced cross talk.

Protection of the sensitive sidewalls canbe achieved by using fluorocarbon-basedetch plasmas that provide PTFE-like side-wall polymer. Those polymers mainly con-sist of organic CFx species and inorganicslike silicon or back-sputtered copper. Toavoid high contact resistivity and to ensurecritical feature dimensions, the residualpolymers have to be removed after pat-terning. With plasma cleaning, organicresidue species can be removed, but forinorganic components, a wet cleaning step

A Low-Damage PatterningScheme for Ultra-Low-kDielectrics

is necessary. To avoid additional damageof the dielectric by plasma cleaning, wetchemical plasma etch residue removal(PERR) is a promising alternative.

Finally, the repair of the damagedregions becomes more and more impor-tant, because the acceptable damagedepth decreases rapidly with further scal-ing of interconnect dimensions. So it ismore or less impossible to reach an ade-quate solution by optimizing the etchprocess alone.

For a successful SiCOH integration, thedevelopment of etching, cleaning and k-restore processes that meet the specialrequirements of those sensible materialsare essential and actually in the focus ofBEOL research and development.

Etch of Porous Ultra-Low-K Materials

Plasma damage by RIE processingmainly results from ion bombardment,aggressive radicals and plasma UV radia-tion.[1] Damage mechanisms include the

removal of nonpolar -CH3 species and theirreplacement by highly polar -OH groups,surface densification and photochemicalmodifications.[3] Common etch chemis-tries include a fluorocarbon gas (e.g., CF4),polymerizing additives (e.g., CHF3 or C4F8)and argon, which is needed to improveetch profile quality by introducing direc-tional kinetic energy. Figure 2 shows thedependency of sidewall damage on poly-merizing additives and argon.

Argon enhances the sidewall damagecaused by concomitant sputter effects. Inthe case of C4F8, the increased concentra-tion of free fluorine also provokes a side-wall damage enhancement.[4] The goal ofdeveloping low-damage plasma processesis to identify the few and narrow optimaexisting in the process parameter fields.

In this purpose, plasma diagnosticmethods become more and more impor-tant in the field of process optimization.Quadrupole mass spectrometry to identifymolecules and ions within the residual gas,as well as Langmuir probes to measure

S. Zimmermann,1 N. Ahner,1 T. Fischer,2 T. Oszinda,3

B. Uhlig,4 S.E. Schulz,1,2 T. Gessner1,2

1Fraunhofer ENAS 2Chemnitz University of Technology 3GLOBALFOUNDRIES 4Fraunhofer CNT

PRINTthis article

E-MAILthis article

Figure 1. Visualization of the Sidewall Damage after Trench RIE Using Diluted HF Solution

0 sccm Ar15 sccm Ar

30 sccm Ar

0

0.5

1

1.5

2

2.5

0 sccm CHF3

5 sccm CHF3

10 sccm CHF3

1.31.0

0.3

0.8

1.9

1.4

1.4

2.4

1.5

Side

wal

l Dam

age

[nm

]

0 sccm Ar15 sccm Ar

30 sccm Ar

0

0.5

1

1.5

2

2.5

0 sccm C4F8

5 sccm C4F8

10 sccm C4F8

1.3

1.5

1.7

0.8

0.3

2.0

1.4

1.8

2.1

Side

wal

l Dam

age

[nm

]

Figure 2. Evaluation of the Sidewall Damage by the Use of Different Additives to a CF4 Plasma in the 28 nm Technology Node




important electron parameters (e.g., densi-ty and temperature), are frequently usedmethods but limited by sensitivity andtime resolution. Quantum cascade laserabsorption spectroscopy offers the possi-bility of measuring with excellent detectionlimit and high time resolution.[4] Usingthis method, the detection of the exact COconcentration in the etch plasma was real-ized, which allows a correlation betweensidewall damage, determined by CH3extraction, and CO concentration (Figure3a). Finally, statistical data evaluationmethods allow a correlation of sidewalldamage and spectra of the optical emis-sion spectroscopy. In this way, information

about plasma species that promote orhamper plasma damage of porous low-kdielectrics can be obtained (Figure 3b).

Post-Etch-Cleaning ProcessesWet cleaning solutions for PERR must

ensure effective removal of residues andcompatibility to Cu/low-k technology. Withdecreasing feature sizes, additional wettingconcerns come into focus. Due to the sur-face energy/surface tension of the clean-ing liquid, the solution may not be able toenter very small structures like via holes, or it may also have effects like pattern collapse, that are already well known fromphotolithography. Pattern collapse has

recently been observed for porous low-kdielectric structures, and this effect, evi-dent during the drying step, may lead tothe destruction of narrow low-k trenches(Figure 4a).[5]

The surface energies of solid and liquid,as well as their polar and dispersive contri-butions, are the key to understanding wet-ting phenomena. To ensure good wetting,the total surface energies of both phasesand their polar/dispersive character shouldbe in a comparable range. By contactangle analysis, the surface energetic char-

acter of solid and liquid can easily bedetermined.[6] Besides the evaluation ofthe wetting behavior, this method turnedout to be a very fast and sensible analytictool for process control, e.g., for plasmaprocessing, k-recovery or CMP.

Analysis of differently etched or poly-merized low-k dielectrics as well as copperand diffusion barrier surfaces have beenshown to have a huge variety of surfaceenergetic characters, and a strong depend-ency on processing parameters has beenobserved. Low-k dielectric layers that have

A Low-Damage Patterning Scheme for Ultra-Low-k Dielectrics BACK END OF LINE

0.0E+00

1.0E-03

2.0E-03

3.0E-03

4.0E-03

5.0E-03

6.0E-03

7.0E-03

8.0E-03

9.0E-03

1.0E-02

0

0.005

0.01

0.015

0.02

0.025

0.03

1 2 3 4

(a) (b)

5 6

CO

/SiF

4 C

on

ce

ntr

ati

on

Sid

ew

all D

am

ag

e/L

ine W

idth

Wafer Number

SD/LW

CO/SiF4

Destroying Species Protecting Species

Formula Correlation Formula Correlation [%] [%]

F2+ 64.91 C2+ -62.60

C3F7NO 62.73 C2 -62.60

F+ 60.10 CHO -59.34

O+ 57.77 CH2O -53.35

N2+ 45.84 Ti+ -53.35

O2+ 45.84 CO2

+ -50.06

O2 45.84 Ti2+ -50.06

OH 43.62 Ar2+ -49.60

SiF 37.44 HNO2 -49.60

H2 31.22 N2O+ -49.60

CO 24.34 CO+ -23.42

NO 23.08 N2 -23.42

N+ 20.94

O2+ 20.87

Si2+ 20.87

Figure 3. (a) The CO/SiF4 ratio inside the etch plasma shows a partial dependence on the ratio of sidewall damage and line width; (b) Plasma species that promote or hamper the sidewall damage,identified by correlation analysis

Figure 4. (a) Wetting concerns in small features: non-wetting of via holes (left) and pattern collapse oftrench structures (right); (b) Surface energy values of differently processed porous SiCOH dielectrics,Cu and diffusion barriers: due to its low surface energy, especially polymerized surfaces are difficult to wet by water-based cleaning solutions; above c) Nonionic surfactant molecules TMDD (base ofSurfynol™ 2502) and Tetronic™ 701; d) Surface energy of a water-based cleaning solution (water con-tent >80%) before and after surfactant addition: 0.1 wt.% of surfactant is enough to distinctly reducethe surface energy of the solution; this led to an improved wetting behavior on polymerized low-k surfaces as shown by the contact angle values in this figure



been processed using a polymerizing etchregime, e.g., by adding C4F8 to a CF4 etch-ing gas, in particular turned out to have a very low surface energy of around 30mN/m (Figure 4c). This makes them diffi-cult to wet by high-energetic water-basedcleaning solutions, whose surface energyusually is in a range of about 70 mN/m,while low-energy solutions on a solventbase will show a good wetting behavior.

Although their wetting behavior is notoptimal on polymeric residue surfaces,water-based cleaning solutions have sev-eral advantages, such as low toxicity,

reduced disposal costs, safe handling andan environmentally friendly character. Onepromising strategy to enable aqueoussolutions to be applied in wet chemicalPERR in 28 nm technology and beyond isthe reduction of their surface energy bythe addition of surfactants.

For the selection of the appropriatesurfactant, especially for single-waferprocessing, several characteristics shouldbe considered: environmental friendlybehavior; low foaming; non-toxicity; com-patibility to acidic or alkaline solutions;stability in aqueous solutions; good

dynamic character. Besides the ability ofthe surfactant to decrease the liquid’ssurface energy, its dynamic characteris-tics, especially the time it needs toadsorb on a surface, is essential if thesolution is applied in single-wafer pro-cessing. Processes such as spin-on orspraying are highly dynamic, and newsurfaces are formed and destroyed rapid-ly. For this reason, the surfactant mole-cule must be able to diffuse to andadsorb at the newly formed surface asfast as possible. By using the maximumbubble pressure measuring method, thisdynamic character of a surfactant solu-tion can be easily analyzed.

Nonionic surfactants especially havebeen shown to meet most of the previousrequirements. Two promising candidatesrecently evaluated are Surfynol™ 2502 (air products) and Tetronic™ 701 (BASF)(Figure 4b). Both are able to reduce thesurface energy of a water-based cleaningsolution from 72 mN/m down to 37 mN/mto 40 mN/m at concentrations of only 0.1wt. percent. The analysis showed goodcompatibility to copper and diffusion barri-er materials. For the application on porouslow-k dielectrics, the cleaning step usingSurfynol™ 2505 must be followed by anIPA rinse due to the fact that FTIR spectrashowed the presence of residual surfactantspecies within the porous network if onlywater is used for rinsing.[6]

Both surfactant-aided aqueous clean-ing solutions showed a distinct improve-ment of their wetting behavior as seenby contact angle measurement on apolymerized surface (Figure 4d). Thisprocessing regime allows aqueous solu-tions to be applied in PERR in futuretechnology nodes, and currently thetransfer to 12” production equipmenthas started.

K-Value Repair ProcessesApproaches to restore the material’s

properties actually focus on silylation reac-tions using organic precursors such asHMDS or OMCTS, which contain silyl (e.g.,alkyl or phenyl moiety) and functionalgroups (e.g., silazane or amino moieties).By silylation, the hydrogen of the silanolgroups within the material is substitutedby Si(CHx)y, which increases the carboncontent of the material and lowers polar-izability (Figure 5a).[7]

One of the biggest challenges in k-restore by silylation is the large size of theprecursor molecules, which leads to sterichindrance. Therefore, the molecules maynot be able to diffuse deep into the porousnetwork of the dielectric and tend to forma surface layer. Due to this effect, only theuppermost parts of the damaged dielectriccan be repaired effectively.

Several approaches to optimize k-recovery by silylation include thermallyassisted processes and UV curing steps.Increased processing temperatures maylead to the fragmentation of the precur-sor molecules, which decreases steric hindrance and supports diffusion into thebulk of the material. Simulations, as well asexperiments, have shown that the optimaltemperature range for silylation is between120 °C and 150 °C (Figure 5b).[8]

For thermally assisted k-recoveryprocesses, the application of the precur-sor (e.g., OMCTS) in a gaseous phase ledto the deposition of a SiCOH-like layer.This can be explained by the fact thatOMCTS is a precursor that is also used forlow-k dielectric deposition, and increasedtemperature may have driven the processinto a CVD regime. Nevertheless, electricalmeasurements have shown a distinctrepair effect for this processing regime(Figure 6).

Figure 5. (a) Silylation reaction mechanism using HMDS as precursor; (b) FTIR transmission spectra of a porous SiCOH after thermal pretreatment (TPT) and immersion in OMCTS precursor: Thermal assis-tance supports the formation of SiMex bonds; best results are achieved using temperatures between100 °C and 150 °C; (c) Silylation mechanism of the in-situ k-recovery process: Without vacuum interruption, no silanol groups are formed and hydrogen is directly substituted by CH3

A Low-Damage Patterning Scheme for Ultra-Low-k Dielectrics BACK END OF LINE



More promising processing schemesinclude the application of the k-recoveryprecursor in a liquid phase, mostly dilutedin an organic solvent (e.g., HMDS in IPA toensure wetting). In particular, a three-steprecovery process consisting of a thermalpretreatment to remove water from theporous dielectric, the silylation reactionwhere the sample is immersed into theprecursor solution and a UV-assisted cur-ing step has been shown to improve theproperties of a plasma-damaged low-kdielectric. The temperature for pretreat-ment is limited to 170 °C, because in higher

temperature regimes, –OH species start to desorb, but they are needed for the sily-lation reaction. UV curing for about twominutes supports the incorporation of theSi(CHx)y species into the dielectric’s net-work. Optimally, the wavelengths have tostay in the range of 222 nm up to 254 nm.Wavelengths below 200 nm have beenshown to lead to the destruction of Si-Cbonds and cause additional material dam-age due to formation of Si-O-Sicrosslinks.[7]

Although the wet chemical recoveryprocess improves the structural and elec-

trical properties of the dielectric, the repaireffect only occurs in the uppermost areaof the damaged layers. New recoveryapproaches include the fragmentation ofthe precursor molecules using a low-tem-perature remote plasma. Ideally, the recov-ery directly follows the etching of thedielectric without vacuum break. Due tothis, dangling Si-bonds after patterning are only saturated by hydrogen, but theformation of silanol is inhibited. Radicalscarrying methyl species (R-CH3) can easilyreact at these sites and substitute thehydrogen by O-Si-(CHx)y and leave themas R-H (Figure 5c).

References 1. M.R. Baklanov et al. Proceedings of the

8th International Conference on Solid-State and Integrated Circuit TechnologyICSICT 2006, pp. 291 (2006)

2. T. Tatsumi, Applied Surface Science, vol. 253, pp. 6716-6737 (2007)

3. S. Uchida et. al. Journal of AppliedPhysics, vol. 103, pp. 073303-1 (2008)

4. S. Zimmermann et al. MicroelectronicEngineering, vol. 87, pp. 337 (2010)

5. C.C. Yang et al. Solid State Phenomena,vol. 187, pp. 253-256 (2012)

6. N. Ahner et al. Solid State Phenomena,vol. 187, pp. 201-205 (2012)

7. T. Oszinda et al. J. Electrochem. Soc.vol. 157, pp. H1140-H1147 (2010)

8. T. Fischer et al. MicroelectronicEngineering vol. 92, pp. 53-58 (2012)

About the Authors

Dr. Sven Zimmermann – Senior Scientist,Fraunhofer ENAS

Dr. Nicole Ahner – Member of ScientificStaff, Fraunhofer ENAS

Tobias Fischer – Process Engineer,Chemnitz University of Technology

Dr. Thomas Oszinda – Senior Engineer,GLOBALFOUNDRIES

Dr. Benjamin Uhlig – Member of ScientificStaff, Fraunhofer CNT

Prof. Dr. Stefan E. Schulz – Head ofdepartment BEOL, Fraunhofer ENAS;Honorary Professor for NanoelectronicsTechnologies, Faculty of ElectricalEngineering and Information Technology,Chemnitz University of Technology

Prof. Dr. Thomas Gessner – Director,Center for Microtechnologies andProfessor for Microtechnology, Faculty ofElectrical Engineering and InformationTechnology, Chemnitz University ofTechnology; Director, Fraunhofer ENAS �


A Low-Damage Patterning Scheme for Ultra-Low-k Dielectrics

total RC improvement (measured)

35

30

25

20

15

10

5

0100 150 200 250 300

lateral RC improvement (measured)

total RC improvement (extrapolated)

lateral RC improvement (extrapolated)

Metal pitch [nm]

RC im

prov

emen

t [%

]

Figure 6. Dependence of the Repair Effect on the Line Width

PRINTthis article

E-MAILthis article

BACK END OF LINE





One of the most recent trends in the“philosophy” of metrology – be it randomdefect analysis or metrology strictly speak-ing (and one of the subjects that I myselfam currently more involved with) – is theoptimization of sampling plans in order toachieve a substantial reduction of the fabcycle time while keeping unvaried the abili-ty to timely detect, and possibly correct,process excursions. To tell the truth, sam-pling plan optimization is not as recent atopic, but these days the number of “exter-nal circumstances” concurrent with theoverall critical situation forces the attentionof silicon manufacturers toward a generalreview of costs, and starting from bigspending down to the single cent, we arefacing a renewed focus on maximizing thereturn on investment in metrology steps(i.e., minimizing the number of very expen-sive equipment, improving the excursion

detection capability, avoiding increasedcycle time of part of the WIP).

There is extensive literature on samplingplans, which generally represents the theo-retical environment of a risk assessmentbetween the number of wafers that mightbe affected by an excursion and the abilityto catch the excursion at soonest. Pfefferand his co-authors, within the frame of theIMPROVE-funded project, describe the the-oretical background in which they embedtheir proposed sampling strategy, and sup-port their findings with a number of exam-ples whereby they show how the adoptedalgorithms reduce the number of wafers atrisk (number of wafers processed by equip-ment between two consecutive inspections,i.e., the number of wafers that might beaffected by an undetected excursion), andoptimize the number of inspected wafers,thus reducing the overall inspection effort.

Davide LodiBaseline Defectivity & Metrology Engineering Manager Micron Semiconductors Italy

PRINTthis article

E-MAILthis article



AbstractSemiconductor manufacturing is facing

an extreme cost pressure. A manufacturingcost reduction of 15 percent per year has tobe achieved by improved productivity. Onecontribution for achieving a cost reductionis to reduce the effort for defect densitycontrol operations. In this article, the basicconcept and the main functionality of apredictive sampling concept are describedand exemplary results are shown.

IntroductionSemiconductor manufacturing is a high-

ly complex value-adding process that isfacing an extreme cost pressure due tofast-changing markets combined with veryhigh capital investments. Currently, a man-ufacturing cost reduction of 15 percent per year has to be achieved by increasedequipment productivity and fab product-ivity in order to compete successfully inthe global market.

One contribution for achieving a costreduction in semiconductor manufacturingis to reduce the effort for defect densitycontrol operations. Nevertheless, thereduction of control measurements has

to be done without increasing the risk ofnot detecting any process abnormality asearly as possible. The challenge is to devel-op effective sampling strategies that needminimized control measurements and thatare capable of rapidly finding defectiveproducts or tools before out-of-specifica-tion lots are processed.

Development ApproachOn the process sequence level, investi-

gations regarding sampling strategies wereperformed and an innovative predictivesampling strategy (PdS) was developed.The predictive sampling strategy is basedon a metrology chain concept, whichmeans that several consecutive processoperations (up to 50) are validated by asingle metrology operation coming down-stream. This concept is shown in principlein Figure 1. The decision regarding whichlots will be the best to be measured shouldbe done after the last process operation(process operation n in the given exam-ple). In reality, this decision is in generalmade at the beginning of the wholeprocess chain, using pre-specified rules.Therefore, no latest information about tool

Predictive Sampling forDefect Density ControlOperationsM. Pfeffer,1 R. Oechsner,1 L.Pfitzner,1 S. Eckert,2 A. Hartmann,2

H. Gold,3 G. Biebl,4 J. Kaspar4

1Fraunhofer IISB, Erlangen 2Infineon Technologies, Dresden 3Infineon Technologies, Regensburg 4Infineon Technologies, Villach

PRINTthis article

E-MAILthis article





status, lot status, product status, etc., isused for the sampling decision, whichleads to partial non-optimized samplingdecisions.

The developed predictive samplingstrategy dynamically adapts the samplingto the current fab situation. In principle, it is a threshold-based algorithm, but thedecision is based on a prediction of theW@R in the future to respect definedwarning limits (thresholds) instead of usingcurrent W@R values. The W@R is thenumber of wafers processed on a processtool since the latest defectivity control ofthis tool. In other words, the W@R is thenumber of wafers showing some risk, due

to a missing control.[1] In the literature(e.g., [2,3]), other sampling strategies arebeing discussed.

Key Performance Indicators for the Evaluation of theSampling Strategies

The PdS algorithm has been implement-ed in a software prototype to simulate andevaluate the predictive sampling strategyagainst existing sampling strategies, whichare implemented at the IC manufacturingsites. The simulation results include W@Rdiagrams at tool and process operationlevels as well as several key performanceindicators, which are listed in Table 1.

Indicator Description

Number of processed lots Number of total lots that have been processed in the analyzed time period

Number of measured lots Number of total lots that have been measured in the analyzed time period

Number of lots above the Number of total lots that have been processed on a tool with a W@R warning limit higher than the defined warning limit

Average W@R Average value of W@R during analyzed time period

Table 1. Indicators to Evaluate the Performance of Fab Sampling and Predictive Sampling Strategies

Figure 1. Principle of an Analyzed Metrology Chain

Predictive Sampling for Defect Density Control Operations METROLOGY, INSPECTION & FAILURE ANALYSIS

Definitions and Notations for thePredictive Sampling Algorithm

With PdS, the W@R is calculated bytool and by operation for each individualchain. A warning limit is defined by tool.The number of available metrology toolsand the required time for the metrologystep are input parameters. The queuesize for the metrology tool(s) is not lim-ited. The following notations are beingused:

• W@R: Number of wafers processed bythe tool without being controlled by asubsequent measurement operation(calculated on tool level)

• WL: Warning limit (defined on toollevel), a limit for the W@R that shouldnot be exceeded

• DR: Mean delivery rate in lots per day(calculated on tool level)

• TtWL: Remaining time before reachingwarning limit (calculated on tool level)

Figure 2. Concept of Predictive Sampling Algorithm



• TtMR: Time until the next metrologyresult will be available (calculated ontool level)

The Predictive Sampling Algorithm

The developed predictive samplingalgorithm overcomes the problem ofredundant measurements or informationgaps, because the sampling decision ismade after the last process operation(n) of the individual metrology chain(see Figure 1) and uses latest availableinformation regarding tool control,which is monitored by the W@R indica-tor. The sampling decision is based on a prediction, if it is possible to keep theW@R below a given warning limit, evenwithout performing a control of the cur-rent lot until the next measurable lotcould be measured. If the prediction ispositive, the lot will skip the metrology

operation (m). If the prediction is nega-tive, the lot will be measured and theW@R could be reduced. This decisionprocess is performed with every measur-able lot, leaving the last process opera-tion (n). The algorithm uses a four-stepcalculation on tool level as shown inFigure 2:• First step: The current W@R of the

individual tool is calculated• Second step: A mean delivery rate

(e.g., lots per day) is calculated usingthe time interval between two lotdeliveries (DR = 1 / mean time inter-val between two lot deliveries)

• Third step: The remaining time beforereaching the warning limit is calculat-ed. This is the first prediction that is made (TtWL = (WL – W@R)/DR)

• Fourth step: Using the time intervalbetween lots that are measurable and needed time for the metrology


Figure 3. W@R Analysis of Two Tools (TC_106 & TC_206) Using Historical Fab Sampling Strategy

(including transport and real meas-urement time), a prediction for thetime until the next metrology resultsmight be available is made. This is thesecond prediction (TtMR = mean timeto next metrology lot + time neededfor metrology operation).

At the end of the process sequence,the TtWL is compared to TtMR. If TtWLis smaller or equal to TtMR, the currentlot is sampled; otherwise, the lot skipsthe metrology operation. The sampled

lot is directly moved to the metrologyoperation, if a metrology resource isavailable. If no metrology resource isavailable, the lot is queued. The dis-patching rule of the metrology queue iscurrently FIFO (first in, first out) and thelength of the queue is not limited. Otherdispatching rules,[4] like critical ratio,etc., might be implemented.

Exemplary ResultsThe first example shows the results

of the investigations of a metrologychain with a 20-process and 1-metrologyoperation. Figure 3 shows the W@R his-tory for the fab sampling and for predic-tive sampling. For fab sampling, warninglimit excursions could be seen for onetool. Using the predictive sampling strat-egy, this could be nearly avoided. Itcould be demonstrated that, even withfewer measured lots, the PdS strategy is capable of reducing the amount ofexcursions of the defined warning limit.

Figure 4. Processed Lots and Lots Above Warning Limit for Fab and Predictive Sampling for the Whole Process Sequence (49 process operations)

Fab Sampling PdS

Processed Lots 2,646 2,646

Measured Lots 774 624

Lots above WL 2,874 2,148

Table 2. Performance Indicators for the WholeProcess Sequence and Relative Improvements



Regarding PdS strategy, the amount ofnecessary measurements was reduced bynearly 40 percent. Furthermore, warninglimit excursions were reduced and theaverage W@R is comparable to the fabsampling.

Table 2 shows the performance indica-tors for the whole process sequence. Thenumber of measurements was decreasedby 20 percent. Therefore, the number of warning limit excursions could bereduced by 25 percent.

The next example covers data for aprocess sequence of 49 process oper-ations, which will be controlled by 1metrology operation. The warning limitwas globally defined as 1,000 wafers.Figure 4 shows the number of processedlots and lots above the warning limit forthe fab sampling and PdS strategy foreach of the 49 process operations. In fabsampling, only 29 lots were measured;this leads to 8,737 warning level excur-sions. Using PdS strategy, the warning

limit excursions could be reduced by 82percent to 1,579, but 230 measurementswere required.

The PdS concept has also a significantinfluence on the average values of theW@R. Figure 5 shows the average W@Rfor all process operations.

The achieved results showed that thePdS is capable of controlling the givenprocess sequence. Nevertheless, thedefined warning limit of 1,000 wafersdoes not seem to be reasonable. There-fore, additional simulations were per-formed to analyze the performance of the PdS with varying warning limits (seeTable 3).

For the given process sequence, awarning limit of 2,500 wafers seems fea-sible in order to achieve an efficient con-trol by predictive sampling. PdS needs83 measurements to reduce the warninglimits excursions by 95 percent to 180lots and to achieve a W@R average of718 wafers.


Figure 5. Average W@R for Fab and Predictive Sampling for the Whole Process Sequence (49 process operations)

Summary and ConclusionThe application of the developed pre-

dictive sampling strategy provides an opt-imized tool or technology control (lessW@R excursions) and a reduced effort for defect density control operations. PdSoffers a great potential to reduce manufac-turing costs by reducing the amount ofrequired defect density control measure-ments. Furthermore, the risk of uncon-trolled manufacturing equipment could bealso decreased. The developed predictivesampling strategy was evaluated using realhistorical fab data from different manu-facturing sites.

AcknowledgmentsThe IMPROVE project is funded by

the ENIAC Joint Undertaking (project ID:12005) and by the public authorities of thecountries involved: Austria (Österreichis-che ForschungsförderungsgesellschaftmbH); France (Direction Générale de la Compétitivité, de l’Industrie et des

Services); Germany (Bundesministerium für Bildung und Forschung); Ireland (TheIndustrial Development Authority); Italy(Ministero dell’Istruzione, dell’Università e della Ricera) and Portugal (Fundaçãopara a Ciência e a Tecnologia).

References[1] Sahnoun, M. et al. “Optimizing return

on inspection trough defectivity smartsampling,” International Symposium on Semiconductor Manufacturing(ISSM) 2010, pp. 1-4, Oct. 18-20, 2010

[2] Dauzere-Peres, S. et al. “A smart sampling algorithm to minimize riskdynamically,” Advanced Semiconduc-tor Manufacturing Conference (ASMC),2010 IEEE/SEMI , pp. 307-310, July 11-13, 2010

[3] Tirkel, I. et al. “In-line InspectionImpact on Cycle Time and Yield,”Transactions on SemiconductorManufacturing IEEE, vol. 22, no. 4, pp. 491-498, November 2009

WL 1,000 1,500 2,000 2,500 3,000

Processed Lots 13,509 13,509 13,509 13,509 13,509

Fab Sampling

Measured Lots 29 29 29 29 29

Lots above WL 8,737 6,892 5,439 4,332 3,436

Max WAR 13,410 13,410 13,410 13,410 13,410

Avg WAR 2,299 2,299 2,299 2,299 2,299

PdS

Measured Lots 230 160 125 83 36

Lots above WL 1,579 783 277 180 26

Max WAR 3,100 3,100 3,100 3,300 3,388

Avg WAR 454 518 575 718 911

Table 3. Fab and PDS Sampling for Various Warning Limits




As new products continue to requirenewer innovations to solve their chal-lenges, the electronics manufacturersare constantly pushing the envelope oftechnology to find better, faster, cheap-er and more reliable methods of pro-cessing materials.

One of those methods is outlined in thissection in the paper titled “Thermal LaserSeparation and Its Applications.” In it, anew technology for kerf-free dicing is pre-sented. This technology, called TLS (ther-mal laser separation), shows exciting capa-bility when dicing very hard to processmaterials – like silicon carbide (SiC). Theauthors discuss the standard dicing tech-nologies and some of the inherent prob-lems, then give good examples of why TLSis a superior solution for brittle and hard-to-process wafer materials. It is sure to findapplications in other areas that have beennotoriously hard to dice or singulate.

Steve Greathouse Global Process Owner for MicroelectronicsPlexus Corporation; Nampa, Idaho

The paper titled “Interconnect Test for Wide-IO Memory-on-Logic Stacks”addresses a new innovation to teststacked die products. A new acronymis being used to identify this type ofproduct – 3D stacked ICs (3D-SICs).These products can have connectionsby the use of through silicon vias(TSVs), wire bonding or other meansthat are interconnected through thesubstrate to the final product board.The technique of testing is outlined inthe paper and can be evaluated in thesoftware programs discussed.

These papers are good examples ofthe way the industry’s leading engi-neers are continuing to extend Moore’sLaw and find new methods to solve theincreasingly complex problems encoun-tered with the newest technologies.Remember, the first one down a newpath finds where the bumps are.

PRINTthis article

E-MAILthis article


[4] Tsung-Che Chiang et al. “A Simula-tion Study on Dispatching Rules inSemiconductor Wafer FabricationFacilities with Due Date-basedObjectives,” International Conferenceon Systems, Man and Cybernetics2006, SMC ’06, IEEE, vol. 6, pp. 4660-4665, Oct. 8-11, 2006

About the Authors

Fraunhofer IISB – Erlangen Germany

Dr. M. Pfeffer – Group LeaderR. Oechsner – Deputy Head of DepartmentProf. Dr. L. Pfitzner – Head of Department

Infineon Technologies – Dresden, Germany

S. Eckert – Senior EngineerA. Hartmann – Senior Engineer

Infineon Technologies – Regensburg, Germany

Dr. H. Gold – Senior Staff Engineer,Simulation

Infineon Technologies – Villach, Austria

G. Biebl – Senior Engineer, AutomationDr. J. Kaspar – Principal �


Predictive Sampling for Defect Density Control Operations

PRINTthis article

E-MAILthis article






ASSEMBLY, TEST & PACKAGING TECHNOLOGIES ASSEMBLY, TEST & PACKAGING TECHNOLOGIES

Three-dimensional die stacks with inter-die connections based on fine-pitch micro-bumps and through-silicon vias offer thepromise of heterogeneous integration withdense high-performance low-power inter-dieconnections. These 3D stacked ICs (3D-SICs)come in a variety of form factors. The inter-poser-based 3D-SIC has multiple active diesplaced side-by-side on top of and intercon-nected through a silicon interposer base.Such products are attractive for high-per-formance computation and communicationapplications, as they offer high-bandwidthinterconnect between the various active diesand good cooling opportunities. Anothertype is the tower of stacked active dies.Offering a small footprint, this type is partic-ularly attractive for handheld and portableconsumer electronics. For the future, we canalso expect hybrid combinations of the twoform factors, i.e., multiple towers of activedies stacked onto a silicon interposer base.

Like all microelectronics products, 3D-SICs need to be tested for manufacturingdefects. Especially for post-bond testing,this requires a test access architecture thatoperates in a concerted way across theentire die stack. Test access (through aprobe card for unpackaged devices or atest socket for packaged products) isthrough the external I/Os only, which aretypically located in the bottom die of the

stack. This implies that if we want to test a middle or top die in the stack, the diesbelow it need to cooperate in order topropagate test stimuli up to and testresponses down from the die-under-test.Testing inter-die interconnects requires an even more orchestrated cooperationbetween the multiple dies in the stack.

3D DfT Architecture for Logic-on-Logic Stacks

In the recent past, we have defined,[1-3]automated,[4] and used[5] a 3D design-for-test (DfT) architecture for logic-on-logicstacks. The main component of that archi-tecture is a die-level DfT wrapper that pro-vides test control and test access function-ality at each die in the stack. The 3D diewrapper is an extended version of the IEEEStd 1500 wrapper, originally developed forembedded IP cores. The 3D wrapper has aprimary test interface at the die’s bottomside, and one (or k, in case of k towers)compatible secondary test interface(s) atthe die’s top side, such that the primarytest interface of die x+1 can be stacked ontop of the secondary test interface of die x.Each interface consists of test control sig-nals, a serial (one-bit) test access mecha-nism (TAM), and an optional scalable (n-bit,with n user-defined) parallel TAM. The serialTAM is used to transport test mode instruc-

Interconnect Test for Wide-IO Memory-on-Logic Stacks

Our 3D DfT architecture leveragesexisting intra-die DfT features such asinternal scan, test data compression(TDC), built-in self-test (BIST), and core-based wrappers and TAMs, as well asboundary scan at the 3D-SIC’s PCB inter-face, and requires no additional product-level pins. The architecture serves the testneeds for die maker(s), stack maker andstack user alike, by providing support for(1) pre-bond die testing; (2) mid-bondtesting for partial stacks; (3) post-bondtesting for complete stacks; (4) board-level interconnect testing; and (5) (low-bandwidth) in-field test and debug. Thearchitecture supports a modular testapproach, in which dies and their embed-ded cores, as well as inter-die intercon-

E.J. Marinissen,1 S. Deutsch,2 B. Keller,2

V. Chickermane,2 S. Mukherjee,2 N. Sood2

1imec 2Cadence Design Systems

tions and low-bandwidth test data. Theparallel TAM is meant for high-bandwidthvolume-production test data. A schematicview of our 3D DfT architecture is depictedin Figure 1. The figure shows a single-towervertical die stack consisting of N dies; forlayout reasons, the stack in the figure isrotated 90° clockwise, such that the bot-tom and top dies are left and right, respec-tively. The functional die designs are repre-sented by gray boxes, of which only theinternal scan chains are shown. The die-level wrapper is the rose circuitry aroundthe functional die design; because we focushere on the wrapper design, it is shownenlarged in Figure 1, but in reality it is negli-gibly small compared to the functional die-internal circuitry.

PRINTthis article

E-MAILthis article

Figure 1. Schematic View of the Logic-on-Logic 3D DfT Architecture




nects, can be tested separately. The archi-tecture provides maximum freedom withrespect to inclusion or exclusion of certaintests at a particular stage of the test flow,and allows for flexible (re-)scheduling ofthose tests in order to optimize the testflow and minimize the associated testcosts. We have shown that the area costsfor medium and large industrial SOCs arenegligible.[2-5] The 3D DfT architecture iscurrently considered for standardizationby the IEEE P1838 Working Group.[6]

JEDEC Wide-IO Mobile DRAMsGiven the ever-growing hunger for

more memory bandwidth and the need to reduce memory power in many appli-cations, it is no surprise that memory-on-logic stacks are among the first stacked-die applications that are appearing on themarket.[7,8] JEDEC, an industry associa-tion that develops and maintains openstandards for the microelectronics indus-try, has recently released its first standardfor stackable Wide-IO DRAMs (JESD-229).[9] This standard widens the conven-tional 32-bit DRAM interface to 512 bits.

The main benefit of wide-IO DRAM over its predecessors (such as LPDDR2 DRAM)is that it offers more bandwidth at lowerpower. Being the first interface standardfor 3D die stacks and offering a compellingbandwidth/power benefit, this standard is expected to gain quite some traction inthe marketplace.

The standard defines the functional andmechanical aspects of the wide-IO logic-memory interface. The functional aspectsinclude the electrical specification, usageprotocols and ball-out. JEDEC’s wide-IOlogic-memory interface defines four inde-pendent memory channels (a, b, c and d)of 128 bidirectional DQ data bits each,totaling 512 data bits over all four chan-nels. The maximum data rate is 266 Mbps(single data rate), which offers a totallogic-memory bandwidth of 512 x 0.266/8= 17 GBs. Next to the data bits, each chan-nel includes independent control andclock, and shared power and ground. The mechanical aspects of the standardinclude the pad locations, dimensions andtolerances. The interface consists of 300(micro-bump) pads per channel, making

1,200 connections for all four channels. Thepad locations are symmetrical between thefour channels. Each channel consists of sixrows by 50 columns of (micro-bump) padsat a pitch of 40 µm in the short axis and50 µm in the long axis.

JEDEC’s wide-IO interface allows forstacking of up to four DRAM dies (“ranks” in JEDEC jargon) on top of each other. Eachrank has four memory blocks, as depicted inFigure 2(a); the logic-memory micro-bumpinterface is located symmetrically in thecenter of the die. A complete stack with abottom logic die and four stacked DRAMranks is shown in Figure 2(b). Such a four-rank stack consists of 16 memory blocks, ofwhich only four blocks (i.e., one per chan-nel) can be accessed at a time. The JEDECwide-IO DRAM allows for a variety of stackconfigurations; the industry has reported onprototype chips where a logic die and a

stack of four wide-IO DRAMs are stackedside by side on a passive silicon interposer,as well as on a single-tower 3D-SIC consist-ing of two logic dies and a single wide-IODRAM rank.[8]

3D DfT Architecture ExtensionSupporting Wide-IO DRAMBoundary Scan

Our original 3D DfT architecturefocused on logic-on-logic stacks, motiv-ated by the fact that DfT can be freelydefined and inserted in CMOS logicdesigns. Due to technology, design andperformance constraints, free definitionand insertion of DfT in DRAMs is typicallynot possible. Fortunately, unlike many pre-vious DRAMs, JEDEC’s wide-IO standardcontains boundary scan features to facili-tate interconnect testing.[9] This boundaryscan implementation, which by the way is

Interconnect Test for Wide-IO Memory-on-Logic Stacks ASSEMBLY, TEST & PACKAGING TECHNOLOGIES

Figure 2 (a) JEDEC wide-IO rank; (b) an example of 3D-SIC containing a logic die and four stackedwide-IO ranks Figure 3. JEDEC Wide-IO DRAM Boundary Scan Implementation per Memory Block



not compliant with the well-known IEEE1149.1 boundary scan standard, is depictedin Figure 3. Next to a functional (transpar-ent non-test) mode, it supports serial scanaccess and “parallel in” (= capture in theDRAM) and “parallel out” (= capture in the logic die) test modes.

We have extended our logic-on-logic3D DfT architecture with support for post-bond testing of the interconnects betweenthe logic stack and wide-IO DRAMs, whichcan be stacked on top or next to the logicstack by means of a silicon interposer. Theextension includes the generation in thetop logic die of DRAM test control signals,and the inclusion of the DRAM boundaryscan registers in the serial and parallelTAMs of the 3D test access architecture.Figure 4 highlights the DfT extensions tothe original architecture in green. They

include 13 new bits in the wrapper instruc-tion register (WIR) for enabling the DRAMboundary scan, selecting the DRAM chan-nel(s), and selecting the DRAM rank(s).This implementation allows us to test inter-connects between the top logic die andany combination of DRAM blocks.

We have set up flows for automaticinsertion of the required 3D DfT in a givendesign with Cadence’s Encounter RTLCompiler, and for automatic generation ofinterconnect test patterns with Cadence’sEncounter Test. Our interconnect ATPGapproach covers static stuck-at faults,slow-to-rise and slow-to-fall faults, andshorted nets. For realistic test cases, theATPG run time is only a handful of min-utes, while yielding high fault coverage(>99.9 percent of all test objectives) with only a few dozen test patterns.

Interconnect Test for Wide-IO Memory-on-Logic Stacks

Figure 4. 3D DfT Wrapper Extension for Wide-IO DRAM Control

The tool flow was put to first use on an industrial design consisting of a siliconinterposer base, a logic SOC die and awide-IO DRAM stack. The DfT was auto-matically inserted into the logic die usingthe tool flow mentioned above. In 40 nmtechnology, the 3D wrapper with wide-IODRAM support occupied 0.025mm2, negli-gibly small for a realistically sized SOC.The tool flow is available in alpha releasefor selected customers from CadenceDesign Systems.

References1. E.J. Marinissen et al. “A Structured and

Scalable Test Access Architecture forTSV-Based 3D Stacked ICs,” IEEE VLSITest Symposium, April 2010, Santa Cruz,California, pp. 269-274.

2. E.J. Marinissen et al. “3D DfTArchitecture for Pre-Bond and Post-Bond Testing,” Proceedings of IEEEInternational 3D Systems IntegrationConference, November 2010, Munich.

3. E.J. Marinissen et al. “A DfT Architecturefor 3D-SICs Based on a StandardizableDie Wrapper,” Journal of ElectronicTesting: Theory and Applications, vol.28, No. 1, February 2012, pp. 73-92.

4. E.J. Marinissen et al. “Automated Design-for-Test for 2.5D and 3D SICs., ChipScale Review, September-October 2011,pp. 18-22.

5. S. Deutsch et al. “Automation of 3D DfTInsertion,” Proceedings of IEEE AsianTest Symposium, November 2011, NewDelhi, pp. 395-400.

6. IEEE 3D-Test P1838 Working Group,http://grouper.ieee.org/groups/3Dtest/

7. R. Goering, “Three Die Stack – A BigStep ‘Up’ for 3D-ICs with TSVs,” inCadence Community Blogs, December2011 (see http://www.cadence.com/Community/blogs/ii/archive/2011/12/13

/three-die-stack-a-big-step-up-for-3d-ics-with-tsvs.aspx).

8. “ST-Ericsson and CEA-Leti’s WIOMINGPrototype Shows How To Combine WideIO Memory and Logic SoC for Future 3DMulti-Processor Architectures,” YoleDéveloppement 3D PackagingNewsletter, (22):16–18, February 2012(see http://www.imicronews.com/upload%5Cnewsletter%5C3DPackaging_Feb2012_iMN.pdf).

9. Wide I/O Single Data Rate (JEDECStandard JESD229). JEDEC Solid StateTechnology Association, December 2011.http://www.jedec.org.

About the Authors

imecErik Jan Marinissen – Principal Scientist;Leuven, Belgium

Cadence Design SystemsSergej Deutsch – former Cadence residentat imec; currently Ph.D. student at DukeUniversity, Durham, N.C.

Brion Keller – Senior Architect; Endicott, N.Y.

Vivek Chickermane – DistinguishedEngineer/R&D Director; Endicott, N.Y.

Subhasish Mukherjee – Senior Member ofConsulting Staff; Noida, India

Navdeep Sood – Senior ApplicationEngineer; Noida, India �


PRINTthis article

E-MAILthis article





ASSEMBLY, TEST & PACKAGING TECHNOLOGIES ASSEMBLY, TEST & PACKAGING TECHNOLOGIES

AbstractThe novel thermal laser separation (TLS)

technology allows for kerf-free dicing ofbrittle materials by crack guiding throughthermally induced mechanical stress. Severalbenefits such as a zero kerf and a high edgequality make it a promising technology forspecial applications: dicing of silicon carbide(SiC) with feed rates up to 200 mm/s; resiz-ing of silicon wafers; and dicing through pn-junctions of silicon diodes.

Introduction and MotivationBesides the virtuous cycle of transistor

scaling as described in Moore’s Law,[1] the functional diversification of integrateddevices, known as “More than Moore”(MtM), is gaining momentum.[2] Addedvalue to integrated devices is provided bycombining electrical, mechanical and chem-ical functionalities that do not necessarilyscale according to Moore’s Law. Incorpor-ating additional functions demands novelmaterial (e.g., wide band gap materials), and novel processes (e.g., clean back endprocesses), as well. Clean dicing withoutdamaging the separated dies is a must forincreasing the bending strength of novelMtM products[3] like smart chip cards. Withcurrent state-of-the-art dicing technologies,

it is often not possible to meet the require-ments of the diverse devices without addi-tional process steps, which leads to a nec-essity of novel dicing technologies.

This article sketches exemplarily threespecial applications of the novel dicingtechnology thermal laser separation (TLS)that go beyond the traditional chip separ-ation: fast dicing of silicon carbide (SiC);damage-free dicing through the pn-junc-tion of silicon (Si) diodes; and resizing oflarge crystalline Si wafers. In comparison,current state-of-the-art dicing technolo-gies – mechanical wafer sawing and laserbased separation – are discussed regard-ing these applications.

State-of-the-ArtAbrasive mechanical wafer dicing is

well established as the most commontechnique for separating dies out of semi-conductor wafers. In doing so, a fast-rotat-ing circular diamond-coated dicing blade isguided along each dicing street of a wafer.Resizing of large wafers can be done bymoving the dicing blade on a tangent linefrom the edge into the wafer until the tar-get diameter is reached. At that point, thechuck is rotated by 360° and a circularwafer is generated.

Thermal Laser Separationand Its Applications

remove the protection layer extend theoverall process time.

Another laser-based separation technol-ogy is stealth dicing (SD), in which modi-fication layers are produced by focusing apulsed laser beam inside a semitransparentmaterial. After the production of thesemodification layers, a mechanical processstep is necessary to separate the devicescompletely.[8]

The SD technology is a fast, kerf-freedicing process especially for thin sub-strates up to a thickness of approximately200 µm. Mechanical stress and microc-racks occur in the modified layer, which is necessary for the dicing process. Afterseparation, these modifications remain atthe sidewalls of the separated dice. Withincreasing wafer thickness, more modifica-tion layers are needed for the separationprocess, and the street width must beenlarged by up to 50 percent of thewafer’s thickness. Separation of waferswith back-side metal is not possible.

Principle and Benefits of TLSTLS is a two-step process[6,9]: A dia-

mond tip or an ablation laser is used toproduce a punctiform initial scribe as apredetermined cleaving point. One puncti-form initial scribe is needed at every partto be cleaved to define the starting pointof the TLS process. Laser-based heatingand subsequent cooling locally inducemechanical stress inside the wafer. Thismechanical stress is capable of guiding a crack through the wafer starting at theinitial scribe following the path of the heat-ing/cooling spot (Figure 1). The propaga-tion of the crack is not bound to the crys-tal plane of the semiconductor material. In fact, it is possible to guide a crack in acircular shape.

Dirk Lewke,1 Matthias Koitzsch,1 Martin Schellenberger,1

Lothar Pfitzner,1 Heiner Ryssel,1 Hans-Ulrich Zühlke2

1Fraunhofer Institute for Integrated Systems and Device Technology IISB 2Jenoptik Automatisierungstechnik GmbH

Blade dicing is an abrasive technique,which requires water for process coolingand for removing particles generated during the process. Because of the highmechanical load at the edges of the kerf,chipping occurs at the front side and backside of the wafer.[4,5] The dicing streetwidth has to be at least the width of thedicing blade plus the width of the chippingon both edges. Throughput and resultingedge quality of the mechanical wafer dic-ing depend on wafer characteristics suchas hardness and thickness. For example,very hard materials like SiC can only beseparated at low feed rates and with lowedge quality.[6]

Beyond that, several laser-based sepa-ration technologies are available, such aspulsed laser ablation, in which material is removed along the desired contour.[7]Pulsed laser ablation results in low edgequality, a broad heat-affected zone (HAZ)and recast of molten silicon on the wafersurface. To avoid recast or residues on thewafer surface, a protection layer is neces-sary. Additional steps to deposit and

PRINTthis article

E-MAILthis article

Figure 1. Principle of TLS[9]




The main advantage of TLS is the ablation-free and hence kerf-free separa-tion principle, which allows for reducingthe dicing street width resulting in moredevices per wafer. Furthermore, TLS gen-erates edges of high quality, which resultsin excellent bending strengths of the sep-arated dies.

Exemplary Applications of TLSThree special applications are presented

in this section to describe the broad fieldof potential applications for thermal laserseparation.

Fast SiC DicingAs mentioned in the introduction, dic-

ing SiC with the mechanical dicing blade

is only possible at low feed rates and withexcessive tool wear. This results in dieswith low edge quality because of the hard-ness and brittleness of SiC. Despite thesechallenges, all SiC devices are currentlyseparated by mechanical blade dicing.With 3103 K, SiC has also a very high melt-ing point; hence, posing a tough challengefor state-of-the-art laser-based separationtechnologies.

Throughput plays an important role forindustrial SiC chip production. The maininfluencing factor is the feed rate. Withthe mechanical dicing blade, typical feed rates of approx. 2-20 mm/s can beachieved. Latest TLS results show feedrates of up to 200 mm/s for 450 µm thick4H-SiC product wafers including epi-layer,

poly imide coating and back-side metal.At the same time, the edge quality of theseparated dies is increased significant-ly.[6] Since the laser has no tool wear, therisk of destroyed wafers due to brokensaw blades no longer exists.

Figure 2 illustrates topographic SEM-images of typical separation results pro-duced with a mechanical dicing blade and TLS. The mechanical wafer sawleaves scratches and microcracks[5] atthe sidewalls of the separated dies. Thehigh mechanical load at the edges of thekerf results in chipping on the front sideand the back side as well. Furthermore,peeling of the back-side metal occurs.TLS results in zero chipping at the front-side and back-side edges as well as insmooth sidewalls.

Dicing Through the pn-JunctionSilicon diodes are often made as whole

wafers and then cut into dice. The separationwith state-of-the-art techniques causes dam-age of the pn-junction. That is why the pn-junction of diodes needs to be protected.

While using TLS, the wafer is only heat-ed up to a few hundred degrees Celsius,which does not damage the pn-junction.Sidewalls of these diodes are smooth, likethe sidewalls illustrated in Figure 2(b).Thus, with TLS it is possible to separatediodes without damaging the pn-junction.

Therefore, TLS allows for directly cut-ting through the pn-junction avoiding theneed for any protection. This results inreduced costs and a decreased cycle timebecause additional process steps can beomitted.

ResizingDuring the transition to larger wafer

diameters, as currently projected in theITRS[10] for 450 mm, wafers of the newsize have to be easily adapted to fit, e.g.,using currently available metrology tools.Using mechanical wafer dicing for resizingresults in a low edge quality of the newwafers. This increases the probability ofwafer breakage during subsequent han-dling or processing of the new wafers.Resizing with laser ablation techniques alsoleads to wafers with low edge quality. Inaddition, the laser ablation-based resizingof standard thick wafers is only possiblewith low throughput, because a v-shapedprofile has to be used for resizing.[11]

As mentioned above, the TLS process isnot bound by the crystal plane. Therefore,with TLS it is possible to resize Si waferswithin a short process time, achieving highedge quality, as shown in Figure 3. Thesetwo aspects make TLS a powerful solutionfor resizing.[11]

Summary and ConclusionThe novel separation technology TLS

was investigated and compared to state-of-the-art dicing technologies regarding spe-cial applications such as SiC dicing; dicing

Thermal Laser Separation and Its Applications ASSEMBLY, TEST & PACKAGING TECHNOLOGIES

Figure 2. Topographic SEM images of typical separation results produced with (a) mechanicalwafer dicing and (b) TLS dicing[6]

Figure 3. TLS Process Result for Resizing a 300mm Single Crystalline Si Bare Wafer to a Diameterof 200 mm[11]


ADVERTISERS INDEX

CyberOptics Semiconductor, Inc. www.CyberOpticsSemi.com 85

Hitachi www.hitachi-hta.com 70

Nikon www.nikonprecision.com 3 46

Swagelok www.swagelok.com 1

TFS www.tfs-us.com 17



directly through the pn-junction of Si-diodes; and resizing of crystalline Si wafers.TLS was found to have several advantagesover state-of-the-art mechanical blade dic-ing and laser-based dicing techniques. Thekerf-free TLS-process results in zero chip-ping, concurrently allowing for high feedrates. Therefore, TLS is a very promisingapproach for these special applications.Future R&D will focus on further improvingTLS crack guiding.

References1. G.E. Moore, “Cramming more compo-

nents onto integrated circuits,”Electronics, vol. 38, no. 8, 1965

2. Arden, W. et al. “More-than-Moore –White Paper,” www.itrs.net, 2010

3. Knutti, J.W. et al. “Trends in MEMS Com-mercialization,” in: Baltes et al. (eds.),Advanced Micro & Nano-systems, vol. 1,Enabling Technology for MEMS andNanodevices, WILEY-VCH Verlag GmbH& Co. KGaA, pp. 21-47 (2004)

4. Gatzen, M. et al., “Dual Wheel MiniatureGang for Silicon Wafer Dicing,” Proc. of2nd euspen International Conference,Turin, Italy (2001)

5. Vagues, M., “Analyzing BacksideChipping Issues of the die at WaferSaw,” in: Partial Fulfillment of MatE 234,SJSU, San Jose, California (2003)

6. Lewke D. et al. “Ablation Free Dicing of4H-SiC Wafers with Feed Rates up to200 mm/s by Using Thermal LaserSeparation,” MRS Spring Meeting (2012)

7. Chichkov, B.N., “Femtosecond,Picosecond and Nanosecond LaserAblation of Solids,” J. of Appl. Phys., A 63, pp. 109-115 (1996)

8. Kumagai, M. et al. “Advanced DicingTechnology for Semiconductor Wafer –Stealth Dicing,” IEEE T SEMICONDUCTM, vol. 20, No. 3, pp. 259-265 (2007)

9. Zühlke, H.-U., “Thermal Laser Separationfor Wafer Dicing,” Solid State Technol-ogy (2009)

10. ITRS, International Roadmap for Semi-conductors (2010)

11. Koitzsch M. et al. “Enhancements inResizing Single Crystalline Silicon Wafersup to 450 mm by using Thermal LaserSeparation,” ASMC 2012, pp. 336-341

About the Authors

Fraunhofer Institute for Integrated Systemsand Device Technology IISBDirk Lewke – research scientist

Matthias Koitzsch – research scientist

Dr. Martin Schellenberger – group mana-ger for equipment and advanced processcontrol

Prof. Dr. Lothar Pfitzner – head, Semicon-ductor Manufacturing department; profes-sor of electrical engineering, University ofErlangen-Nuremberg

Prof. Dr. Heiner Ryssel – founder; profes-sor of electrical engineering, University of Erlangen-Nuremberg

Jenoptik Automatisierungstechnik GmbHDr. Hans-Ulrich Zühlke – business develop-ment manager �


Thermal Laser Separation and Its Applications

PRINTthis article

E-MAILthis article

http://www.cyberoptics.com/products/wafersense/


http://www.future-fab.com/?nikon42ad

http://www.swagelok.com/industries/semiconductor.aspx



In Association with: ISSUE 42 – July 2012 · Director of Technology Strategy for Intel...

Documents

Transcript of In Association with: ISSUE 42 – July 2012 · Director of Technology Strategy for Intel...