Improved PLL design based on SDFT and SGDFT

for Grid Interfaced Renewable Energy Sources

under Harmonic Condition

Abstract—Generally phase lock loop (PLL) is used for

grid synchronization and also to evaluate the phase angle

and frequency for grid interfaced renewable energy

sources (RES). During harmonics in the grid voltage,

conventional PLL design methods have more steady state

error in the tracked frequency and phase. This paper

proposes an improved phase estimation method based on

sliding discrete Fourier transform (SDFT) and sliding

Goertzel discrete Fourier transform (SGDFT) techniques.

The SDFT based PLL has additional number of

multiplications and computation process is reduced by

using SGDFT PLL by providing a pole-zero pair in the

system such that the performance of the PLL is improved.

The proposed techniques are mathematically explained

and simulated and finally the acquired results are

compared with each other and result shows that the

SGDFT PLL has less computation process and accurately

tracked the phase and frequency with less total harmonic

distortion (THD) of the estimated fundamental signal

under harmonics grid in the voltage.

Keywords—phase lock loop; renewable energy sources;

sliding discrete Fourier transfrom;

I. INTRODUCTION

With increasing demand for electric power with

improved power quality (PQ) and reliability,

renewable energy sources (RES) are attracting more

attention to provide power to full fill the demand-

supply gap. Grid connected inverters need exact

information about the frequency and phase angle in

order to regulate the power factor and power flow

such that utility voltages are precisely synchronized

with the reference voltage and current. Fault ride

through (FRT), PQ and stability are some of the

grid code requirements and should be satisfied

through grid side converters. Proper phase tracking

and grid synchronization techniques are required to

evaluate the phase angle and frequency of the utility

systems in order to satisfy the issues related to PQ

standards. Phase lock loop (PLL) is one of the most

widely used technique and it has been applied to the

control of electric drives, communications systems,

and others [1] and it is used to synchronize the

utility voltage and controlled currents or voltages in

the utility interface of converters and the basic idea

behind the PLL is any variation in the phase of the

given signal is adaptively tracking by phase angle of

the estimated signal and the resultant error is

reduced through loop filter (LF).

In three-phase systems, synchronous reference

frame (SRF) PLL is the most general type and

under ideal grid conditions, SRF PLL is able to

estimate the phase and frequency by very fast and

accurate way due to its high bandwidth. But under

non-ideal grid conditions, the bandwidth has to be

decreased in order to remove the ripples. So under

distorted grid conditions, SRF PLL has failed to

track the frequency and phase angle by the fast and

accurate way with reduced steady state error [2].

The development in the digital signal processing

(DSP) applications of the power systems brings the

concept of digital filters in the PLL design to track

the grid frequency and phase during ideal and

disturbed grid conditions. In [3] new discrete

Fourier transforms (DFT) based PLL is proposed

based on phase error and time window calculation

method, however sampling time rate gave more

steady state error. Fundamental frequency

extraction based on sliding discrete Fourier

transform (SDFT) is discussed in [4] and the idea is

periodic signals are divided into harmonic

components and fundamental components are

extracted from the selected harmonic components.

B.Chitti Babu et al. proposed sliding discrete

Fourier transform (SDFT) based grid

S.A Lakshmanan

School of Computing and Electrical Engg

Indian Institute of Technology Mandi

lakshmanan_s_a@students.iitmandi.ac.in

Amit Jain Smart Power & Energy System

Central Power Research Institute

amitjain@cpri.in

amitjain@cpri.in

B. S. Rajpurohit School of Computing and Electrical Engg

Indian Institute of Technology Mandi

bsr@iitmandi.ac.in

synchronization for distributed generation (DG)

applications with improved dynamic performance

[5]. However, this method leads more steady state

error in the frequency of the voltage controlled

oscillator (VCO) output during the process of

calculation and also the system has more

computation process. So based on the above

discussions, the paper presents an improved phase

detection method by using sliding discrete Fourier

transform (SDFT) and sliding Goertzel discrete

Fourier transform (SGDFT) techniques. The

number of calculations required by the SDFT PLL

is reduced by using SGDFT PLL by providing pole-

zero pair in the system, such that computation

process is simplified and also phase angle is tracked

with improved performance and less steady state

error. The workability of the proposed methods are

analyzed by using pole-zero and bode plots and

simulated results are compared with each other and

as a result, SGDFT PLL has improved performance

with reduced computation process under harmonics

in the grid voltage. This paper has prepared as

follows. In section II, control structure of the

conventional SRF PLL, proposed SDFT PLL and

SGDFT PLL systems were discussed and

frequency response analysis of the proposed

techniques was given in section III. In section IV,

simulation results are presented and discussed and

section V presents conclusions.

II. CONVENTIONAL SRF PLL AND

PROPOSED SDFT PLL & SGDFT PLL

BASED PHASE DETECTION

A. SRF PLL based phase detection method

In grid-connected RES applications, it is

common to use the PLL for grid synchronization

and also for estimating the frequency and phase of

the given signal. Three-phase SRF PLL based phase

detection is systematically shown in Fig. 1 in which,

three-phase grid voltage signals EgA, EgB, EgC are the

inputs and transformed into SRF direct and indirect

voltage components Vd and Vq respectively by using

Parks‟s and Clarkes transformation matrices. The

input voltage signals are expressed as

(

)

Here q-axis voltage component is synchronized

along with voltage space vector and carrying out the

matrix transformation and voltages in

the dq-frame are expressed by

[

] [

]

The estimated phase θest is obtained by

integrating the frequency component ωest which is

the summation of feed forward frequency ωff and

output of the PI regulator based LF and finally the

error . The gains of the LF are tuned

such that d-component voltage Vd follows reference

voltage Vdref =0. The system fundamental frequency

is locked with estimated frequency ωest and q-axis

component is synchronized along with voltage

space vector when Vd=0, so the phase angle θ equal

to the estimated phase angle θest [6]. The feed

forward frequency ωff is added to control the PI

controller for an output signal that goes to zero. The

feed forward frequency is 314 rad/sec and grid

frequency is 50Hz and once the system has

estimated the phase, the output of the regulator is

zero. If θest equals to phase angle θ, the small signal

approximation for the d-component voltage Vd= -

Vmδ and the corresponding small signal model of

the PLL in the z-domain is shown in Fig. 2. [7].

EgA

EgB

EgC

abc Va

Vß

aß

dqVdq

22

qdest VVV

1/ VestVd

Vq

Vd *= 0Loop

Filter

1/2p

fest

+

+

+

-

PI

Controller

Phase

DetectorVCO

Vest. mag

aß

ff

est

Δω

∫

ω

θ

Fig. 1. Basic control structure of three-phase SRF PLL

Grid voltage signals are under ideal condition,

the input signals are positive sequence voltage

components and high bandwidth SRF PLL is

talented to track the frequency and this is the basic

idea of the PLL algorithm. However, whenever the

grid is under distorted conditions, high bandwidth

increases the voltage distortions and due to that

several harmonics are presented in the PLL output.

-Vm

Vd

Vd*=0

PI

Controller VCO

1

z

zK

1z

Ts

+

++

-

θest

θ Δω

ω ff

ωest θest+

_

Fig. 2. Small signal model of SRF PLL in the discrete domain

B. SDFT PLL based phase detection technique

Basically, SDFT is used to investigate the

harmonic components and to track the fundamental

part of the frequency and the basic schematic

control structure of the PLL based on SDFT method

is shown in Fig. 3. In the given sliding window, N-

point DFT is calculated by using SDFT technique

and based on the previous results of the DFT, a new

N-point DFT is calculcated by increasing the

sample by one [8].

Input signal

p(t)

Analog to Digital

Converter

p(n)

SDFT

In-phase com (pp)

Quad comp (pq)

SDFT cosine

p(n) Phase

Detector

Moving

Average

Filter

PI

Controller

e1(n)Limiter NCO

Sampling

pulses

ena

ena

ena0

With harmonics

Fig. 3. Basic schematic structure of PLL based on SDFT algorithm

The in-phase and orthogonal components of the

input harmonic signals are extracted by using the

SDFT block on the PLL system. The system is

included with MAF filter together with PD, PI

controller based LF and VCO. The time-domain

sequence of a windowed DFT is p(k) and then after

shifting by one sample, the sequence is . The SDFT PLL is designed based on the

given sampling frequency (fs) and fundamental

frequency f, then the system is determined by

another signal having the frequency of (f+Δf) and

the phase shift ΔΦ is accumulated with sine and

cosine wave output and it is proportional to the Δfs

and this property is used to track the phase angle

and using ΔΦ, it adjusts the fs to (fs+Δfs). For the

given single bin (k) at given angle rad,

the corresponding fundamental frequency is (kfs/N)

with k values of 0 k N. The following equation

which describes the SDFT algorithm is

where is the time domain signal, is the

present input sample and is the delayed

input sample. So here pk(n) is obtained by adding

the current input sample p(n) along with pk(n-1)

components and subtract the delayed input samle

p(n-N). The system based on SDFT PLL and for

each output sample, the number of real addiations

required by the system is two and also it has one

complex multiplication. Based on the analysis given

in [9], window width of the MAF filter is N, the

SDFT can do as N-point DFT and the number of

real additions and multiplications required by SDFT

is 4N and at the each successive N-point output

having the computational difficulty of O(N)

compared with other FFT algorithms. The sine

wave with proper magnitude, phase and frequency

is achieved by doing proper disintegration of

periodic signals by fitting one complete cycle into

the window width N. The z-domain transfer

function of the SDFT algorithm for the kth

bin is

expressed as [9]

The real and imaginary parts of the z-domain

based SDFT transfer function have been generated

by using comp filter and resonator and the comp

filter is a finite impulse response (FIR) type and it is

represented as , errors are accrued during

the computation process and it leads instability in

the system which can be solved by using addition of

stability factor . The in-phase and quadrature

components of the signals Re[Pk_real] and

Img[Pk_img] are obtained from the input harmonic

signals and phase lock is achieved by using the

quadrature signal when k=2. In the SDFT based

PLL, due to the instantaneous computation problem,

phase error exists with respect to one sampling

interval. This problem can be solved by introducing

an unit delay between comb filter and resonator and

the complete mathematical control structure of the

SDFT with unit delay and damping factor is shown

in Fig. 4 and the corresponding modified z-domain

based SDFT PLL is expressed as

So due the introduction of unit delay, the phase

error is reduced and the in-phase component

obtained by using SDFT algorithm is synchronized

with the fundamental component. In the low

frequency applications, harmonics and fundamental

components are extracted using SDFT PLL and the

block diagram shown in Fig. 4 is built by using

moving average filter (MAF), PD, PI controller,

VCO along with SDFT block. Maintaining the

window length N is constant, the sampling

frequency fs is adaptively varied and supplied to the

-200

0

200

Mag

nit

ud

e (

dB

)

100

102

-360

0

360

720

1080

Ph

ase (

deg

)

Bode Diagram

Frequency (Hz)

-2 -1 0 1 2-1

-0.5

0

0.5

1Pole-Zero Map

Real Axis

Imag

inary

Axis

Pole zero

cancel

-200

0

200

Mag

nit

ud

e (d

B)

100

102

-720

0

720

1440

2160

2880

Ph

ase

(d

eg

)

Bode Diagram

Frequency (Hz)

-1 0 1-1.5

-1

-0.5

0

0.5

1

1.5Pole-Zero Map

Real Axis

Imag

inary

Axi

s

Pole zero cancel

SDFT block. The harmonic signals fed into the

SDFT block and the corresponding outputs are in-

phase Re[Pk_real] and quadrature components

Img[Pk_img] respectively. The quadrature component

is 90° phase shift with the in-phase component with

respect to the fundamental part and the extracted in-

phase signal is having less phase or magnitude

error. The extracted quadrature component is a

cosine fundamental signal , input signal is compared

and the resultant phase error is given to MAF. The

phase error is effectively used by varying the

sampling frequency of the SDFT block and PI

controller takes the input from MAF and the

resultant output is steady dc with reduced steady

state error [9].

+ +p(n)

z-N

z-1

Pk(n)

Pk(n-1)

-γNγej2*3.14*k.N

Fig. 4. Structure of SDFT PLL with damping factor and unit dealy

C. SGDFT based phase detection

In order to track the fundamental part from the

input harmonic signal, the number of

multiplications required by the SDFT PLL system is

further reduced by generating a pole-zero pair and

the proposed method is called as SGDFT PLL based

phase estimation. The factor

is used in

the numerator and denominator of the equation

given (6) and finally the z-domain based SGDFT

PLL is expressed as [9]

The structure of the SGDFT PLL is shown in

Fig. 5 and due to the availability of real feed back

coefficients, the samples v(n) are obtained from the

Fig. 4 are real-only and sample by sample based

spectral updates is required for real-time processing

[10].

III. PERFORMANCE ANALYSIS OF SDFT PLL

& SGDFT PLL SYSTEM

Performance of the SDFT PLL and SGDFT PLL

systems were analysed by using pole-zero and bode

plots. The phase response and ability of the noise

elimination are identified through frequency

response characteristics of the SDFT PLL system.

+ +p(n)

z-N

z-1

Pk(n)

-1

z-1

-1

+

2ocs(2*3.14*k/N) -ej2*3.14*k/N

Fig. 5. Basic schematic structure of PLL based on SGDFT algorithm

In order to analyse the system performance,

sampling frequency fs=5000Hz, window width

N=20 and fundamental frequency f=50Hz are

considered, and for k=2, the equation (6) is

simulated and the corresponding pole-zero and bode

plots are depicted in Fig. 6 and it is seen that single

pole is created by extracting the single frequency

component and cancelling with a zero at and other zeros are placed on the unit circle.

The frequency response plot shown in Fig. 6(b)

states that all the harmonic components are rejected

and allows only fundamental frequency component.

The SDFT PLL system is marginally stable and

sometimes bounded-input bounded-output stable if

errors obtained during the computation process are

less.

Fig. 6. Frequency response based on SDFT algorithm a) bode plot

b) pole-zero map.

The SGDFT PLL having the characteristcis of

impulse response with a finite duration and for

every input sample, feedforward calauctaions

Frequency(Hz) Real Axis

Frequency(Hz) Real axis Fig. 7. Frequency response based on SDFT algorithm a)

bode plot b) pole-zero map

(a) (b)

(a) (b)

0 0.05 0.1 0.15 0.2-500

0

500

Time[Sec]

Vo

ltag

e[V

]

0 0.05 0.1 0.15 0.2-500

0

500

Time[Sec]

Vo

ltag

e[V

]

In-phase

Quadrature

0 0.05 0.1 0.15 0.2-500

0

500

Time[Sec]

Vo

ltag

e[V

]

Actual Phase

Estimated Phase

0 0.05 0.1 0.15 0.20

5

10

Time[Sec]

Ph

ase A

ng

le

Actual Phase

Estimated Phase

0 0.05 0.1 0.15 0.240

50

60

Time[sec]

Fre

qu

en

cy[H

z]

0 0.05 0.1 0.15 0.20

5

10

Time[Sec]

Pha

se A

ngle

Actual Phase Angle

Estimated Phase Angle

0 0.05 0.1 0.15 0.2-500

0

500

Time[Sec]

Vo

ltag

e[V

]

EgA

EgB

EgC

0 0.05 0.1 0.15 0.2-500

0

500

Time[Sec]

Vo

ltag

e[V

]

In-phase

Quadrature

0 0.05 0.1 0.15 0.2-500

0

500

Time[Sec]

Vo

ltag

e[V

]

Actual phase

Estimated phase

0 0.05 0.1 0.15 0.250

50

50

Time[sec]

Fre

qu

ency

[Hz]

0 2 4 6 8 100

0.2

0.4

0.6

0.8

1

1.2

1.4Fundamental(50Hz)=1.0001, THD=1.5%

Harmonic order

Mag

nitu

de

0 2 4 6 8 100

0.2

0.4

0.6

0.8

1Fundamental (50Hz)=1.0001, THD=1.1%

Harmonic order

Mag

nitu

de

should be performed. The SGDFT PLL is simulated

and the corresponding bode and pole-zero plots

were depicted in Fig. 7. Due to the reason of

in the numerator of (8), a new zero

is placed at and zeros are cancelled

by conjugate ploes at and N zeros are

placed on the unit circle.

IV. SIMULATION RESULTS AND DISCUSSIONS

The performance of the proposed methods based

on SDFT and SGDFT PLL systems for grid

synchronization and phase detection were simulated

by using MATLAB Simulink solver under

harmonics in the grid voltage. The parameters used

for the simulation study is given here. The input

voltage with amplitude Vm=321V, fundamental

frequency f=50Hz, window width N=20, sampling

frequency fs=5000Hz, enabling clock frequency

fenao=26.6 kHz and kp=0.01, ki=0.0036.

Three-phase grid voltage signal with fundamental

frequency of 50Hz including harmonic components

of 5th

,7th

and 11th

order with the corresponding

magnitudes of 10%, 7% and 5% of the peak

amplitude voltage is expressed as

.

Fig. 8. SDFT PLL under grid voltage harmonics a) input signals

with harmonics b) in-phase and orthogonal signals c) actual and

estimated phase d) actual and estimated phase angle e) estimated

frequency f) THD of the tracked fundamental signal

The response of the SDFT PLL under grid

voltage harmonics is shown in Fig. 8. The input

harmonic signal and real, quadrature signals

obtained from the SDFT block is shown in Fig. 8(a)

and (b) respectively. In order to reduce the

computational error and also to improve the system

stability, stability factor is included and the

estimated phase and phase angle along with actual

values are shown in Fig. 8(c) and (d).

0 0.05 0.1 0.15 0.2-500

0

500

Time[Sec]

Vo

ltag

e[V

]

Actual Phase

Estimated Phase

(a)

(b)

(c)

(e)

Fig. 9. SGDFT PLL under grid voltage harmonics a) input

signals with harmonics b) in-phase and orthogonal signals c)

actual and estimated phase d) actual and estimated phase

angle e) estimated frequency f) THD of the tracked

fundamental signal

(d)

(f)

(b)

(a)

(c)

(d)

(e)

(f)

The output of the VCO is shown in Fig. 8(e) and it

shows that output frequency is not accuraterly

tracked due to more computation process. The THD

of the estimated fundamental component is 1.5%

which is depicted in Fig. 8(f).

The SGDFT PLL have improved performance

under grid voltage harmonics such that the

fundamental frequency and phase angle have been

tracked accurately with less computation process by

generating a pole-zero pair in the system. The input

harmonic signals and real, quadrature signals

obtained from the SGDFT block is shown in Fig.

9(a) and (b) respectively. By using VCO, phase and

phase angles have been tracked and compared with

actual value that have been shown in Fig. 9(c) and

(d) respectively. The estimated fundamental

frequency with least steady state error is depicted in

Fig. 9(e) and THD of the tracked fundamental

signal is 1.1%, which is shown in Fig. 9(f).

So based on the results shown in the above,

comparative study has been made which is given in

Table.1. The SDFT PLL is able to track the

fundamental due to less sensitive variation with

harmonics and the THD of the fundamental signal is

1.5%. The order of multiplications required for the

SDFT PLL is 4N. The SGDFT PLL required only

N+2 multiplicatios and it is able to track the

fundamental very accurately and THD of the

estimated fundamental signal is 1.1%. TABLE II

COMPARATIVE ANALYSIS OF SDFT & SGDFT PLL SYSTEMS UNDER

HARMONICS IN THE GRID VOLTAGE

Disturbance SDFT

PLL

SGDFT

PLL

Harmonics

Extraction of

Fundamental

Less

accurate

Accurate

THD 1.5% 1.1%

Speed of

dynamic

response

Low Fast

Number of

multiplications

4N N+2

V. CONCLUSIONS

The accurate information about phase angle and

frequency of the grid voltage and current is essential

for grid synchronization and also useful for

generation of reference current signals in order to

implement the control algorithms. This paper

proposes an improved phase lock loop (PLL) design

based on sliding discrete Fourier transform (SDFT)

and sliding Goertzel discrete Fourier transform

(SGDFT) techniques for grid-connected renewable

energy sources (RES) under harmonics polluted

grid voltage. The SDFT PLL and SGDFT PLL

systems were discussed separately and simulated by

using MATLAB tool. The obtained results are

compared and discussed with each other and it is

seen that the SDFT PLL has more computation

process and also the estimated frequency has more

error. The number of multiplications is reduced by

using SGDFT PLL by providing pole-zero pair in

the system so the dynamic performance is improved

and accurate tracking of the fundamental frequency

is achieved with less total harmonic distortion

(THD) of the estimated signal.

ACKNOWLEDGMENT

The authors acknowledge the financial support

provided by the project under DST-SERB and

CPRI-Bangalore.

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