Improved control signal distribution for very wide VLSl data buses

P.VV. Diodato H.T. Weston

Indexing terms: VLSI dutu buses, Signul distribution, On-chip control signal

- Abstract: A new technique for distributing electronic signals by way of a conducting path across large spatial distances with minimal temporal dispersion is presented. It provides for the delivery of a common signal to any number of different receivers located along the signal path, with near zero skew and little degradation of the signal’s riseifall transition times. The method involves the placement of an active routing structure in parallel with, and appropriately strapped to, a conventional passive conductor. The concept is demonstrated in the paper, within the context of VLSI design, by a solution to the problem of distributing an on-chip control signal to the many lines of a physically very wide data lbus.

1 Introduction

The performance of an electronic system is often deter- mined by the speed at which information can be moved between its components. In particular, the delay in arrival times of a signal at different destinations within a system has a large impact on overall operation. Within a synchronous environment, for example, the worse case for such delay largely determines the latency of the system, since the extended propagation time requires a longer interval for logic setup and execution. This, in turn, constrains the maximum frequency at which the system can be clocked without functional failure.

Critical itself in many applications is the relative delay, or skew, that arises between copies of a clock signal disseminated over different paths. Techniques for its minimisation are typified in modern VLSI device design. Much research has been done on optimising the hierarchical tree-like distribution of on-chip clock sig- nals to maintain synchronisation across the area of a die [l-7 and refs. therein]. In the present work, consid- eration is focussed on how, for a given branch of a dis- tribution network, skew can be essentially eliminated between timing signals that are tapped off to gates located along the length of the branch. Motivation is

0 IEE, 1997 IEE Proceedings online no. 1997 I365 Paper first received 19th July 1996 and in revised form 9th April 1997 The authors are with Bell Laboratories, Lucent Technologies, 700 Moun- tain Avenue, Murray Hill, NJ 07974, USA

provided by the need to deliver control signals of con- stant relative phase to the many lines of large data buses. Doing so with the usual buffering techniques has been reported difficult for buses 2 64 bits wide [8], and is sure to become more problematic as future VLSI chips evolve to even wider bus designs. To this end, a new technique is presented here for routing such con- trol signals across very wide data buses with nearly zero phase distortion and also minimal degradation of transition edges.

2

In many hardware interconnection media, buses are often configured such that data is carried in a given direction on one routing level, while timing signals are delivered to the control gates for the bus on an orthog- onally orientated level. Such a scheme is illustrated in Fig. 1 with data moving vertically and timingicontrol signals moving horizontally. For integrated circuits, particularly those fabricated in MOS technologies, the conductive layer for data is usually provided by metal, and that for control by silicided polysilicon. In instances where the polycide is more resistive than can be tolerated, it is common to place ‘repeater’ buffer stages in series along the polysilicon path [9]. They serve to lower both the resistance and capacitance seen by the driver that sources the control signal, and hence reduce the delay across the data bus. Alternatively, when a second level of metal is provided by the tech- nology, it is usually used as a passive strap to the poly- silicon. thereby contributing a low resistance shunt path.

Temporal dispersion of bus control signals

n Lines o f data bus

-

c 3

m

E C

z .-

0 0 0

Fig. 1 Typical bus con)guvution

J

209 IEE ProcComput. Digit. Tech., Vol 144, No. 4, July 1997

Control signal propagation via these standard imple- mcntations is depicted in Figs. 2, 3 and 4. Included are the rcsults of circuit simulations performed for a 32-bit wide data bus, modelled with technology parameters of a 0.35pm CMOS process. A 32-bit bus offers program- ming convenience for the SPICE-like software tool used [lo], yet it is sufficiently large to illustrate the rele- vant concepts. Specifically, the bus is 8 O O p m wide, with the control gate for each bit line providing approxi- mately 16 fF of capacitance. In each Figure, the timing signal path across the bus is portrayed as a long resis- tor, and the control gate for each bit line is; for sim- plicity, represented as an inverter load. Also, for the sake of clarity, only a subset of all 32 control gate input waveforms is shown.

signal input path

control gate 0 control gate 31

I

bit 16

0 2000 LOOO 6000 8000 time, ps

Fig. 2 32-hit duta hus hy 1552/0 WSi, conlrolpath

Sirnuluted i.e.s~il1s / i i i de1iver.v ojiiniing &nuis to cotitroi giires o j

signal input path repeater

control gate 31 contra( gate 15 control gate 16

0 1000 2000 3000 LOOO time, p s

Fig. 3 Siinulated resultsfor delivery of timing sigizair to control gutes of 32-bit datu hus by 15n/o WSi, control path, with noninverting rejjeciter buffer located midway across bus

original added signal parallel passive path path straps

control gate 0 control gate 31

0 1200 2000 2800 time, ps

Simulated rcsults for delivery of timing signals to control gutes of Fig.4 32-bit datu lms by 1 5 C K W S i control path, passively .rtrcippec? bj V.OSQE Metal 2 at evevy,fbuut/i b t

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The simplest way to route a control signal to the 32 bit lines is via a single runner of silicided polysilicon. We assume the use of WSi2, having a sheet resistance of about 15PiO. Its path width alternates from 0 . 4 ~ in the -100A thin oxide regions where the control gate MOSFETs are formed, to 1 . 0 ~ in the intervening -5000 A thick oxide regions that serve to isolate electri- cally the individual transistors. As a result, nearly 650Q of additional series resistance accumulates in the control signal path as it traverses each bit line of the data bus. The large distributed RC load on the WSi2 path gives rise to the poor signal propagation charac- teristics presented in Fig. 2. As the input signal (after an initial buffering by a dual-inverter driver) crosses the bus, its arrival time at successive bit lines is severely skewed, and the transition time of its edge is signifi- cantly increased. Only the rising edge of the control signal is shown in the Figures; the falling edge demon- strates nearly identical temporal behaviour and needs no additional consideration. As expected, most degra- dation occurs for the last bit line located at the far side of the data bus. The wait between the times when the input to the dual-inverter driver and that to the control gate for bit 31 rise to half the 3.3V supply voltage is given by:

latency = delay max = 2070 ps (bit 31). Also, the relative delay between arrival times of the control signal at the first and last bit lines is:

skew = delay max ~ delay min = 2070 ps (bit 31) 161 ps (bit 0) = 1909ps.

And lastly, the signal risetimes (from 10% to 90% of full swing), are:

risetime mean = 2555ps, risetime spread = risetime max ~ risetime min = 4040ps (bit 31) ~ 1070 ps (bit 0) = 2970 ps.

The above four quantities are shown in the first row of the summary Table 1, and serve as a convenient refer- ence for the circuit enhancements that follow.

2. I Repeaters Matters are improved somewhat if the dual-inverter driver at the top of the control signal path is supple- mented with like drivers spaced along the length of the polycide runner. The control path is thereby parti- tioned by the noninverting buffer stages into a number of series-connected segments. Each buffer serves as a repeater to regenerate the signal for its segment and also to drive the input of the buffer for the following segment [9]. Fig. 3 shows how the presence of only one additional inverter pair buffer halfway down the con- trol path affects the signal propagation across the 32- bit bus. The buffer is sized to share as close to half the burden of the control path as possible. It is seen that the skew among the group of first 16-bit lines is greatly diminished; and, likewise for the second group of 16-bit lines. Separating the two groups in time is the gate delay inherent to the repeater itself. The latency is now reduced to 153Ops (bit 31), and the skew becomes 1530ps (bit 31) - 161ps (bit 0) = 1 3 6 9 ~ s . (Additional repeaters, in this case, offer marginal further improve- ment as their gate delay approaches and even exceeds the reduction in skew provided in each segment of the control path.) Again, the other parameter of interest is the mean risetime for the inputs to all control gates of the bus, which is here lowered to 928ps. The risetime

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Table 1: Delay and transition time results for different methods of delivering timing signalis to a 32-bit data bus

Delay Risetime Routing method for timing signals Latency Skew Mean Spread

(PSI (ps) (ps) (ps)

Reference { Method 1 2070 1909 2555 2970

Single level metal Method2 1530 1369 928 483 technology Method3 734 89 534 364

Multilevel metal Method4 595 16 968 0 technology { Method5 442 4 204 0

(All values are derived from circuit simulations [ I O ] and are expressed to the nearest picosecond.) Method 1: Resistive poly path. Method 2: Resistive poly path with repeater. Method 3: Resistive poly path actively strapped with another poly path at every 4th bit line. Method 4: Resistive poly palh passively strapped with metal path at every bit line. Method 5: Resistive poly patih actively strapped with metal path at every 4th bit line

spread is determined by the distribution across each half segment of the control signal path, and is just 1170 ps (bit 15 or 31) - 687ps (bit 0 or 16) = 483ps. These results for the repeater are presented in the second row of Table 1.

2.2 Passive strapping Often, a VLSI technology will offer multiple levels of conductive material to extend the versatility of on-chip routing. If the fabrication process provides an addi- tional metal level, there is obvious merit in taking advantage of its relatively low resistivity, and incorpo- rating it into the interconnections for the timing sig- nals. An effective way to do this is via passive strapping, whereby a runner of the second level metal is positioned above the polycide path, and the two are connected at numerous locations along their length [ l l ] . The shunting action of the metal greatly reduces the resistance of the control path, with a corresponding improvement in its signal propagation characteristics. Fig. 4 illustrates the benefit of using a 1 .OO pm wide line of 0.05 Q/O Metal 2 connected in parallel with the WSi2 path. Shown is the result when the strapping con- tacts are spaced at intervals of 1 0 0 ~ (i.e. every fourth bit) across the data bus. No repeater stages are present. The control signal timing parameters for this case are latency = 614ps, skew = 36ps, risetime mean = 972ps, and risetime spread = Ips. If the degree of strapping is increased fourfold so that the metal makes contact to the polycide at every bit line of the data bus, the latency, skew, risetime mean, and risetime spread are reduced a little further to 595ps, 16ps, 968ps, and Ops, respectively. It is these latter numbers, representing the best case for passive strapping, that are included as the fourth row of data in Table 1.

It should be remarked that the skew here can, in principle, be reduced to zero by sending the control sig- nal on the metal path first to the centre of the bus and then distributing it to all the bit lines via equal length paths. Such a tree-like structure, however, is not partic- ularly suitable for routing signals across a data bus. The hierarchy inherent to the tree would either OCCUPY excessive area (if constructed laterally with a single level of metal), or tend to obstruct the orthogonal flow of data signals (if constructed vertically from several levels of metal). Furthermore, the sharpness of the con-

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trol signal transitions continues to suffer serious degra- dation even with the use of a passive distribution tree. Hence, a better solution is needed.

2.3 Active strapping The improvements provided by repeaters (in a single level metal technology) or passive strapping (in a multi- ple level metal technology) may not be sufficient for all applications. Accordingly, an enhanced routing scheme has been devised for the distribution of timingicontrol signals across a large region when sourced from only one side of that region. The concept builds on the active nature of the buffers that are inherent to repeat- ers along with the shunting aspect of strapping, and is therefore termed ‘active strapping’. Basically, the signal path is composed of a pair of parallel runners that are bridged at numerous locations along their length, not by passive wire connections, but instead by active ele- ments.

adder original added inverter signal parallel

input 1 path path active strops

control gate 31

0 LO0 800 1200 time, p s

Fig.5 Sindated results for delivery of timinx signals to control gutes of 32-hit d(ita hus hy 155;1/0 WSi, control path, actively strapped hj, 0.05SLa Metal 2 at every fourth bit

Fig. 5 exemplifies the technique as it may be applied to a data bus, again chosen for illustrative purposes to be 32 bits wide. Continuing with the case of multilevel interconnects discussed at the end of the previous Sec- tion, the original WSi, path across the bus is, as before, shunted by a second level metal path. Here, however,

21 1

each strap connection is made active with a simple inverting device. One additional inverter is positioned at the head of the shunt path to maintain the logical sense of the signal delivered to the control gates by way of the straps. A subtle aspect of the active strapping arrangement is the fact that the original polypath is no longer driven directly by the dual inverter buffer that sources the control signal. Omission of this connection, as highlighted in Fig. 5 , is necessary to avoid positive feedback between the inverter that drives the added path and any of the active strap inverters. Latching action would otherwise occur, and upset the proper operation of the circuit.

The placement and sizing of the active straps is important for effectively exploiting the extra degree of buffering provided by them. We have found that good results are obtained if the drive capability of the active straps increases across the bus in a fashion similar to the delay that the timing signal ordinarily suffers as it traverses the control path. Two means of achieving this are: (i) use fixed size strap inverters with increasing fre- quency of strapping farther from the signal source, or (ii) employ uniformly spaced straps that incorporate progressively larger inverters toward the far side of the bus. Because the fixed pitch of the bit lines in the bus may be incompatible with the strap spacing required by the first method, it is expected that the second method most often will be easier to implement. Considering the latter method then, Fig. 5 deals with a control path being actively strapped at regular intervals. As in Fig. 4, the strapping occurs at every fourth bit line. It is noteworthy that the area overhead of a strap inverter located at a given bit line does not add significantly to that of the associated timing control logic, which is needed for the line in any case. Furthermore, the execu- tion logic for an individual bit line is rarely so dense that it will not accommodate the placement of an addi- tional inverter. Therefore, the strap inverter can usually be embedded within the street already allocated for the control and execution logic of a bit line with little or no area penalty.

The procedure for determining the appropriate sizes of the active straps is discussed in Section 3. Fortu- nately, the benefit that strap inverters provide is not critically dependent on exactly how their size increases across the bus. For the case shown in Fig. 5, the rela- tive widths of the strap inverters are chosen as 113, 113, 213, 213, 213, 213, 1, 1 with respect to the inverter that represents the control gate load for each bit line. The performance achieved by this scheme is: latency = 442ps, skew = 4ps, risetime mean = 204ps, and rise- time spread = Ops. These results are shown in the last row of Table 1. This active strapping provides the best means for reducing the parameters for both delay and transition time for the signals delivered to all the bit lines of the data bus.

The noninverting buffer at the input of the active strap configuration is present to insure a fair compari- son with the other methods of routing the control sig- nal across the data bus which require such a buffer. If this buffer is deleted, so that only a single inverter is used to drive the control signal path, the latency is reduced further to 336ps.

Active strapping may be used to advantage even in instances when an upper level of metal is unavailable to shunt the poly control path. The third row of Table 1 gives the calculated values for the case where the origi-

nal WSi2 path across the data bus is actively strapped by another such polycide path. Again, the active strap- ping occurs at every fourth bit line of the bus. As expected, the results are not as good as those obtained when an additional metal level is employed, but they are a definite improvement over the use of repeaters (c.f. the second row of Table 1).

3 Sizing of active straps

To develop the details for active strapping, it is helpful to consider the propagation of timing signals across a data bus in terms of delivering charge to the capacitive loads for the bit lines. For the case at hand, the capac- itors are of fixed equal size and connected to the con- trol signal path at evenly spaced intervals across the bus. Within the context of a fluid model [12], it is intu- itive that capacitors near the start of the control signal path will ordinarily ‘fill’ faster than those far from the source of the charge. This is simply due to the natural time delay of charge flow along the length of the con- trol path.

What is needed to equalise the fill times of the capac- itors is a means for reducing the charge flow into the control path at its end near the source while increasing the charge flow into the path at its far end. This may be done by attaching the source of the timing signal not directly to the control path, but instead to a second parallel path that is configured with an arrangement of connections (i.e. straps) to the first path to accomplish the desired sourcing of charge to the first path. Specifi- cally, some of the charge that otherwise would enter the first path at its head end is redirected to enter instead farther along its length. Such regulation of the transfer of charge from the added shunt path to the original path influences, in turn, the quantity of ‘charge per unit length’ that flows from the first path into the receiving capacitors. When this quantity is made uni- form along the first path, the fill-times of the capaci- tors will be equal, and the system is considered skewless.

For the case where the connections between the two paths are active straps, the size (and secondarily the position) of the strap inverters are adjusted to regulate the signal transfer from the shunt path to the control path. Essentially, one retards the signal transfer near the source end while enhancing it near the far end by varying the drive capability of the active straps in pro- portion to the skew that the straps are meant to cor- rect. To do so, first requires that the delay characteristics along a template of the actively strapped line be established. This template serves as the starting configuration. It consists of inverter straps uniformly spaced, with placement usually at every second or every fourth bit position of the data bus. In addition, all the straps in the template are of the same size, usually equal to that of the per bit load for each line of the data bus. The electrical response of the template is then determined by way of circuit simulation [lo] or other convenient means such as the Elmore delay model [13]. The resulting dependence of delay against bit position is subsequently used to prorate the sizes of the transis- tors in each strap inverter. Dimensions are normalised such that the width of the active strap at the far end remains that of the starting template.

Some modifications of the above procedure are often required. For example, the delay function may suggest that straps close to the source have transistor sizes

IEE Pvoc.-Comput. Digit Tech, Vol. 144, No. 4, July 1557

unrealistically small for the design rules of the VLSI technology employed. A compromise that has been found to work well replaces two such small straps with a larger, more reasonably sized one. This strap is located at a bit position between that of the original two small straps. It is fortuitous that the optimum active strap arrangement resides in a broad minimum of the strap configuration space, so that a good solu- tion can be obtained with few iterations.

4 Conclusions

Table 1 provides a concise summary of this .work in that it facilitates the comparison of the timing parame- ters associated with each of the routing schemes dis- cussed. It is easy to see that active strapping offers a marked improvement over other methods for delivering timing/control signals across a wide data bus. This is especially true for the active strapping case shown in the fifth row of Table 1, where the shunt path for the control signal is of low resistivity metal. Here, the skew is so small that the relative delay between the control signals for the first and last bits of the bus is hardly discernible when drawn in a timing diagram whose timescale encompasses the collective results of all simu- lations. Even for active strapping where shunting is provided by a second resistive poly path, the third row of Table 1 indicates electrical behaviour comparable to that (shown in the fourth row) which can be obtained by conventional passive strapping with a metal shunt path.

Besides the increased rate of data throughpul. that is enabled by the reduction in control signal latency and skew, active strapping provides an additional perform- ance advantage over other means for routing a signal path across a data bus. Namely, the sharpness of tran- sition times associated with active strapping serves to speed up the turn-on and turn-off times of the transis- tors in the bit line gates that are driven by the control signals. This has the effect of reducing the transient energy loss by these gates, and as such helps reduce the overall power dissipation of the circuitry.

The results of this paper have been derived from con- sideration of 32-bit data buses as appear in many VLSI

devices today. Yet, active strapping is applicable to the one-sided sourcing of control signals across any size bus. Wider buses may require that the shunt path for the control line itself be strapped by an additional shunt path. In any case, active strapping is expected to be essential for the very wide bus designs that are cer- tain to occur in future IC chips. Moreover, the concept appears to offer a solution to the general problem of propagating a common signal in a wire for distribution to many receivers along its length with minimal skew. As such, active strapping should also be of value to systems larger in size than individual integrated cir- cuits.

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