IMPLEMENTING THE 10-BIT, 50MS/SEC PIPELINED...

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CHAPTER 5

IMPLEMENTING THE 10-BIT, 50MS/SEC PIPELINED

ADC

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5.0 INTRODUCTION

This chapter is devoted to describe the implementation of a 10-bit,

50MS/sec pipelined ADC with different stage resolutions using the

designed blocks of chapter 4. An N-bit pipelined ADC can be

implemented in any number of stages. If only a single bit is converted

per stage then, we need 10 stages. However, if two bits are converted

per stage then, only five stages are required and so on. This chapter

discusses about the implementation of 10-bit pipelined ADCs with 1,

1.5, 2, 3, 4 and 5-bits/stage conversion mechanisms.

5.1 1-BIT /STAGE PIPELINED ADC

An N-bit pipelined ADC can be implemented in any number of

steps. If only a single bit is converted per stage, then we need N stages

connected in series as shown in Fig. 5.1. This ADC can achieve high

resolution and at high speeds [115].

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Fig. 5.1 One bit/stage Pipelined ADC

As shown in Fig. 5.1, each stage is called a multiplying DAC (MDAC),

consisting of a 1-bit sub-converter (comparator), a S/H amplifier, a

subtractor and a residue amplifier with a gain of two. The operation of

the circuit is as follows.

1. The input signal is sampled and compared with Vref/2. If

Vin > Vref/2 the output of comparator is ‘1’. If Vin < Vref/2, the

output of comparator is ‘0’. The comparator output is the

converted bit of that stage.

2. If Vin > Vref/2, then comparator output=1 and Vref/2 must be

subtracted from the input signal and the residue is passed to

the amplifier with a gain of two. However if Vin < Vref/2, then the

output of comparator = ‘0’ and 0V must be subtracted from the

held input and the residue is passed to amplifier for providing a

gain of two i.e.,

If Vin > Vref, output of residue amplifier is 2Vin-Vref

and If Vin < Vref , output of residue amplifier is 2Vin.

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The output of residue amplifier becomes the input to the next stage

S/H circuit and the process repeats until the signal passes through all

the stages.

Here, all the odd numbers stages operates on Φ while all the even

number stages operates on Φ’ so that, when even stages samples on

the residues of odd stages, the odd stages are free to sample the

output of even stages. Since all stages are processing simultaneously,

the pipelined ADC results in a high throughput. After an initial delay

of N-clock cycles called latency, one conversion will be completed per

clock cycle.

5.1.1 Switched capacitor MDAC (unipolar input)

The structure of MDAC to convert 1-bit/stage can be implemented

using switched capacitor circuits. The circuit for unipolar input is

shown in Fig. 5.2. The switch connections shown are for the MDAC in

sampling mode. During sampling, the capacitor Ci and Cf are charged

to Vin. During hold mode, the switches S1 to S3 change their positions.

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Fig. 5.2 Single bit MDAC for Unipolar input

Now Ci is connected to the DAC output and Cf is connected in the

feedback path of op-amp to work as a difference amplifier. For

1-bit/stage conversion, the sub ADC simply reduces to a single

comparator. The comparator compares the hold input signal with

Vref/2. If Vin > Vref/2, the output of comparator, D=’1’ and if

Vin < Vref/2, the output of D=‘0’. When D=’1’ the D/A converter switch

connects +Vref to Ci else if D = ’0’, ground is connected to Ci. Therefore

the op-amp along with Ci and Cf acts as a residue amplifier.

The expression for the output of amplifier is

refinf

iresidueout VDV

CCV .1 −

+= -----Eq. (5.1)

If Ci = Cf, then Vresidueout = 2Vin-Vref for D=’1’ and Vresidueout = 2Vin for

D=’0’ as required. The output of this MDAC is fed as input to the next

stage and so on.

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5.1.2 Switched capacitor MDAC (bipolar input)

The MDAC circuit for bipolar input i.e., Vin between –Vref and +Vref

is as shown in Fig. 5.3.

Fig. 5.3 Single bit MDAC for Bipolar input

The output of this MDAC can be expressed as

refinf

iresidueout VDV

CCV .1 +

+= -----Eq. (5.2)

Here D can be ±1.

Therefore for Ci = Cf the output can be

Vresidueout = 2Vin+Vref for D=+1

And Vresidueout = 2Vin-Vref for D=-1

The gain accuracy of this converter depends on the matching accuracy

of the capacitor Ci and Cf. Although, single ended op-amp architecture

is used here; we can extend this for differential op-amp architecture

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as shown in Fig. 5.4 so that the noise and offsets and other errors are

minimized.

Fig. 5.4 Fully Differential S/H circuit with gain

The expression for residue output now modifies to

( ) )(1 DACNDACPf

iinninp

f

ioutnoutpout VV

CCVV

CCVVV −−−

+=−= -----Eq. (5.3)

In this architecture, the first stage output (MSB) is available much

earlier than the outputs of other stages. Therefore, we need to

synchronize the outputs by making them move through a series of

latches/flip-flops. The waveforms of Fig. 5.5 shows the various lengths

of shift registers required for different stages. From figure it is clear

that the first stage output must be passed through five positive edge

triggered flip-flops and one negative edge triggered flip-flop and the

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last stage needs only one positive edge triggered flip-flop. The latency

of this converter is seen to be 215 clock cycles.

Fig. 5.5 Waveforms to decide the shift logic of different stages

5.1.3 Accuracy issues of 1-bit/stage pipelined ADC

Assume all the components to be ideal. The one bit/stage ADC can

be analyzed by estimating the switching voltage of the comparators for

the ideal and the non-ideal cases. Let VSW1 be the input voltage at

which the first stage comparator switches. Therefore,

VSW1 = ½ Vref -----Eq. (5.4)

The input voltage on the second comparator will then be

−= − refNini VDVV .

212 12 -----Eq. (5.5)

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Where, DN-1 is the MSB output of first stage comparator.

The second stage comparator now switches when Vi2 = ½Vref.

Therefore,

refref VV41 . D

21 = V 1-N2SW + -----Eq. (5.6)

Proceeding like this, we can write the input voltage to the third stage

comparator as

−−= −− ).

21().

21(22 213 refNrefNini VDVDVV -----Eq. (5.7)

and the switching voltage of third comparator is

refrefref VVV81 .D

41 . D

21 = V 2-N1-NSW3 ++ -----Eq. (5.8)

The general expression can now be written as

refrefrefrefref VVVVV N11-N3-N2-N1-NSWN 21.D

21...............D

81 .D

41 . D

21 = V +++++ -----Eq. (5.9)

D0 will not be seen in above equation as no more conversion is

required after the last stage. Now let us evaluate the switching

voltages for comparator for the non-ideal cases. Let us include the

S/H amplifier offset voltage (VSHO) and comparator offset (VCO) as the

non-idealities. Let all the residue amplifiers have equal gain ‘A’. The

input voltage to the non-ideal comparator of the first stage is

11'

SHOini VVV += -----Eq. (5.10)

Then the switching voltage of this comparator will be

1SW1'

21 = V COref VV + -----Eq. (5.11)

Equating Eq. (5.10) and Eq. (5.11), we get

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11SW1'

21 = V SHOCOref VVV −+ -----Eq. (5.12)

The input voltage to the non-ideal second stage comparator will be

2112' )..

21( SHOrefNSHOini VAVDVVV +−+= − -----Eq. (5.13)

Then the switching voltage of second stage comparator will be

)(121.

21

21112'

COSHOSHOref

refNSW VVA

VA

VVDV −−−+= − -----Eq. (5.14)

Extending this to the last stage, we can generalize the switching

voltage of the Nth stage as

∑=

−−−−−− −+++++=N

kK

SHOKN

CONNref

Nrefref

NrefNSWNA

VAV

AV

AV

DA

VDVDV

11112121

'

21

21..........

21.

21 ----Eq. (5.15)

The integral non-linearity (INL) error of one bit pipeline stage can be

evaluated by subtracting the switching voltages of non-ideal and ideal

cases.

The INL of first stage can be written by subtracting VSW1 from VSW1’.

i.e.,

1111'

1 SHOCOSWSW VVVVINL −=−= -----Eq. (5.16)

Similarly

AV

AV

VA

VVVINL COSHO

SHOref

SWSW22

122'

2 211

2+−−

−=−= -----Eq. (5.17)

And

--Eq. (5.18)

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The addition of all offsets must be within ½ LSB for the ADC to be

accurate. In equation for INLN, we see that the effect of offsets on INL

of Nth stage is minimal as it is divided by a large gain. Therefore, the

later stages of a pipelined ADC are more accurate and the design is

not a critical issue. Hence, by using less accurate designs for the last

stages, we infact can save area and power. The last term of Eq. (5.18)

indicates that the effect of first stage on INL is the largest. Therefore,

in pipelined ADC design, the first stage must be much more accurate

than the later stages. Hence, the first stage is designed carefully and

later stages designed only to save area and power.

The differential non-linearity error (DNL) can be evaluated by

calculating the worst case difference of the switching points and then

subtracting the ideal value of an LSB. The worst case switching occurs

when digital output switches from 0111….1111 to 1000 ……… 0000

when all bit positions are changed.

Therefore,

Nref

SWNSWV

VVDNL2

'1

'max −−= -----Eq. (5.19)

By substituting DN-1 = 1 and all other bits = 0 in the expression for

V’SWN, We get

Nref

N

KK

SHOKN

CONCO

N

KKref

VA

VAVV

AVDNL

211

21

2111

1

1max −+−+

−= ∑∑

=−−

−

=

-----Eq. (5.20)

This value must be less than ½ LSB.

5.2 1.5-BITs /STAGE PIPELINED ADC

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In ADC/DAC, one bit corresponds to two levels, 0 and 1 and two

bits corresponds to four levels 00, 01, 10 and 11. In a stage, if we use

only three levels for conversion then it is 1.5-bits/stage conversion.

Fig. 5.6 Sub-converter Architecture for Unipolar input

A 1.5-bits/stage is a 1-bit/stage into which we add some redundancy

to compensate for the device imperfections and tolerances. The digital

error correction algorithm [116] removes this redundancy at a later

stage to convert the output back to 1-bit. The sub-converter

architecture for 1.5 bit/stage with unipolar input is as shown in Fig.

5.6 and for the bipolar input the figure is as shown in Fig. 5.7.

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Fig. 5.7 Subconverter Architecture for Bipolar input

The Fig. 5.8 shows the transfer characteristics for single ended and

bipolar input signals.

For unipolar signals,

if 4ref

in

VV < then the digital output will be ab = 00

and if 4

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refin

ref VV

V<< then the digital output will be ab = 01

and if 4

3 refin

VV > then the digital output will be ab = 11.

And for bipolar input,

if 4

refin

VV

−< then the digital output will be ab = 00

and if 44

refin

ref VV

V +<<

− then the digital output will be ab = 01

if 4

refin

VV

+> then the digital output will be ab = 11.

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(a) (b)

Fig. 5.8 Transfer curves for (a) unipolar and (b) Bipolar inputs

The encoding logic changes 11 to 10. So that the output of analog

multiplexer (DAC) will be as shown in Table 5.1

Table 5.1 Generation of codes in sub-converter

Input range ab Output of DAC Output of MDAC

4ref

in

VV

−< 00 -Vref 2Vin+Vref

44ref

inref V

VV +

<<−

01 0 2Vin

4ref

in

VV

+> 10 +Vref 2Vin-Vref

5.2.1 MDAC implementing 1.5-bits/stage

The MDAC circuit with single ended output used to implement this

table is as shown in Fig. 5.9. During sampling mode, S1 is closed and

S2 is open to sample the input signal onto the capacitors Ci and Cf.

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During the hold mode, the switches change their positions. Now the

sub ADC and DAC connects (Vref/0/-Vref) to Ci and the capacitor Cf

will be in feedback path of the op-amp. The output of MDAC will then

be as shown in Table 5.1.

Fig. 5.9 1.5-bit MDAC

5.2.2 The redundancy bit removal algorithm

This algorithm converts the 2bit code of a stage to the final

1-bit/stage code. The expected error sources in pipelined ADCs are

offset voltages of amplifiers and comparators, gain errors in amplifiers

and also the non-linearity errors in sub-converters. Many of these

errors can be corrected by using the 1.5-bits conversion and this

algorithm. To generate the final code, the individual bits of all stages

must be added in a predetermined way as follows. If DN-1,1 is the MSB

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bit of Nth stage and DN-1,0 is the LSB bit of Nth stage and so on. Then

output code is achieved by adding them as shown below.

DN-1,1 DN-1,0

DN-2,1 DN-2,0

DN-3,1 DN-3,0 -----

----- D1,1 D1,0

D0,1 D0,0

_______________________________________________________________________________________

DN-1 DN-2 ------------ D2 D1 D0

_______________________________________________________________________________________

To achieve this, we need to use a combination adder with inputs as

shown in Fig. 5.10.

Fig. 5.10 Digital Arithmetic in 1.5-bits/stage

Table 5.2 shows the conversion mechanism and the codes generated

in a three stage pipeline. For example, if Vin = 0.79V, then the codes

generated by successive stages will be (as shown highlighted in third

row) 10, 01, and 00.

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Table 5.2 Code generation in subconverters of 1.5bits/stage

These codes must be added in a predetermined way as follows.

Discarding the LSB, the final output code for Vin = 0.79V is 101. The

same logic is extended to generate a 10-bit error corrected output

code.

5.3 2-BITs /STAGE PIPELINED ADC

The detailed block diagram of a 2-bits/stage pipelined ADC is

shown in Fig. 5.11. We need 5 stages to implement a 10-bit pipelined

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ADC. Each stage generates 2-bits which are passed through a chain of

shift registers of varied lengths.

Fig. 5.11 10-Bit Pipelined ADC with 2-bits/stage

The waveforms of Fig. 5.12 shows that stage one needs three positive

edge triggered flip flops to shift data while stage two requires two

positive edge triggered flip flops and one negative edge triggered flip

flop and so on.

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Fig. 5.12 Waveforms to decide shift register lengths

Each stage in the pipeline has a 2-bit flash sub-converter, encoding

logic, DAC and a switched capacitor amplifier with gain of 4 as shown

in Fig. 5.13.

Fig. 5.13 Stage details of 2-bits/stage pipelined ADC

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The code conversion mechanism is explained in Table 5.3.

Table 5.3 Code generation in subconverter of 2-bits/stage

inV Code Output of DAC Output of stage

4ref

in

VV < 00 0V inV4

24ref

inref V

VV

<< 01 4refV

−

44 ref

in

VV

43

2ref

inref V

VV

<< 10 2refV

−

24 ref

in

VV

43 ref

in

VV > 11 refV

43

− refin VV

434

5.3.1 Two bit priority encoder

The output of comparator blocks (abc) and the required digital

output code generation is shown in Table 5.4. The priority encoder

design is based on the inputs(abc) and outputs(B1 B0) of the table.

Table 5.4 Truth table of 3:2 priority encoder

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From Table 5.4, using sum of products we get

B1 = bc

B0 = a’b’c+abc

And the CMOS digital implementation is shown in Fig. 5.14.

Fig. 5.14 Two Bit Priority Encoder

5.3.2 Two bit DAC

The circuit diagram for 2-bit DAC is shown in Fig. 5.15. The DAC is

implemented using transmission gates only. As the DAC doesn’t use

an op-amp, it is inherently fast. The input and output details of DAC

are shown in Table 5.3. The simulation results of 2-bit D/A Converter

is shown in Fig. 5.16. The delay of the DAC is seen to be 2ns. The

latency of this ADC is 3 clock cycles.

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Fig. 5.15 Two bit D/A Converter

Fig. 5.16 Simulation results of 2-bit D/A Converter

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Using 3-bits/stage, we need at least four stages as shown in Fig.

5.17 with the first three stages converting 3-bits/stage and the last

one converting 1-bit.

Fig. 5.17 10-Bit Pipelined ADC with 3-bits/stage

The sub-converter uses a 3-bit flash subconverter and a 3-bit priority

encoder to generate the final 3-bit code/stage. The 3-bit DAC

implemented is an R-2R ladder DAC as shown in Fig. 5.18. This

architecture needs four S/H amplifiers and 22 comparators. The

simulation results of 3-bit R-2R DAC are shown in Fig. 5.19 and the

delay of the 3-bit DAC is seen to be 2.5ns.

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Fig. 5.18 3-bit D/A Converter


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Fig. 5.20 3-Bit flash subconverter and encoding logic

5.4.1 3-bit priority encoder

The requirements of 3-bit priority encoder are as shown in

Table 5.5. The outputs of comparators (X7 to X1) are the inputs to the

priority encoder. The inputs are transformed to (a7 to a0) by using

XOR logic. Starting from LSB bit and XORing the adjacent bits in

every row, we get results (a7 to a0) as shown in Table 5.5. Using SOP,

the Boolean expression for the final digital output (B2B1B0) can be

evaluated as follows

B0 = a1+a3+a5+a7

B1 = a2+a3+a6+a7

B2 = a4+a5+a6+a7

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Table 5.5 Encoding logic in 3-bits/stage

Input Range Comparator

outputs (X7 to X1)

Inputs after XORing (a7 to a0)

Digital Outputs (B2B1B0)

8ref

in

VV < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

refinref VVV81

82

>> 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1

refinref VVV82

83

>> 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 0

refinref VVV83

84

>> 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 1 1

refinref VVV84

85

>> 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0

refinref VVV85

86

>> 0 0 1 1 1 1 1 0 0 1 0 0 0 0 1 0 1

refinref VVV86

87

>> 0 1 1 1 1 1 1 0 1 0 0 0 0 0 1 1 0

refin VV87

> 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1

Therefore, to implement a 7:3 priority encoder we need seven two-

input XOR gates and three four-input OR gates. The final digital

circuit of 3-bit priority encoder is as shown in Fig. 5.20. The XOR and

OR gates are implemented in fully static CMOS logic with minimum

transistor sizes to save area and power. The digital output (B2B1B0) is

passed through a bank of shift registers to result in the final digital

output. The waveforms and the number of flip flops required in every

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stage is shown in Fig. 5.21. The latency for this ADC is only 2½ clock

cycles.

Fig. 5.21 Waveforms deciding shift register lengths in different stages


Using 4-bits/stage, we need at least three stages with first and

second stage converting 4-bits each and the third stage 2-bits. The

general block diagram is shown in Fig. 5.22.

Fig. 5.22 10-bit Pipelined ADC with 4-bits/stage

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The first two stages in the pipeline have 4-bit flash sub-converters and

the third has a 2-bit flash. Each stage has encoding logic and a DAC.

This architecture needs only three S/H amplifiers with gains of 16, 16

and 4. This ADC needs 33 comparators to implement the sub-

converters.

A 15:4 priority encoder is required here. It is implemented using

the extended logic as discussed for 2-bit priority encoder. The final

Boolean equations to be implemented are

B0 = a1+a3+a5+a7+a9+a11+a13+a15

B1 = a2+a3+a6+a7+a10+a11+a14+a15

B2 = a4+a5+a6+a7+a12+a13+a14+a15

and B3 = a8+a9+a10+a11+a12+a13+a14+a15

The DAC is a 4-bit R-2R ladder DAC for stages with 4-bits

conversion and for the 2-bit last stage, the DAC uses of simple set of

transmission gates. The S/H amplifier circuit used is switched

capacitor type discussed previously. The S/H amplifier of the first two

stages needs a gain of 16. Hence Ci/Cf is appropriately adjusted to

result in the required gain. The waveforms explaining the digital shift

logic are shown in Fig. 5.23. The latency for this 4-bits/stage

pipelined ADC is only two cycles.

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Fig. 5.23 Waveforms to decide shift register length in different stages

The 4-bit DAC implemented is an R-2R ladder DAC as shown in

Fig. 5.24. The simulation results are shown in Fig. 5.25.

Fig. 5.24 Schematic of 4-bit D/A Converter

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Using 5-bits/stage, this pipelined ADC needs only two stages. The

general block diagram is as shown in Fig. 5.26.

Fig. 5.26 10-bit Pipelined ADC with 5-bits/stage

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The waveforms shows that the first stage needs two flip-flops, a

positive edge triggered flip-flop followed by a negative edge triggered

flip-flop. However, stage two needs only one positive edge triggered flip

flop. The latency for this ADC is only 1½ clock cycles. Since there are

only two stages, this ADC needs only two S/H amplifiers. The two

subconverters use 5-bit flash stage and hence needs 62 comparators.

The subconverters generate 31 outputs which are to be finally

converted to 5-bits. Therefore, we need a 31:5 bit priority encoder and

is implemented using the extended logic of 4-bit priority encoder.

5.7 LAYOUT ISSUES OF PIPELINED ADCs

A fixed height layout, with variable widths is always preferred in

CMOS design. It is also preferred to have analog signals and digital

signals separate.

Fig. 5.27 Layout structure with fixed height

Fig. 5.27 shows a typical layout structure with fixed height. VDD and

VSS lines are wide enough and also separated by enough distance to

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accommodate PMOS transistors close to VDD and NMOS transistors

towards VSS. A typical pipelined ADC has switched capacitor S/H

amplifier, comparators and clock generator circuits as analog blocks

and digital storage, shifting and error correction circuits as digital

blocks. These analog and digital blocks may be separated as shown in

Fig. 5.28 [117] [118].

The following points must be looked into when laying out the design.

1. Let the differential input signals be laid out close to each other

as shown in Fig. 5.28. So that the noise that interferes (common

mode signal) will be equal on both lines and hence cancels out.

Let all the differential signals be laid out like this.

2. Let the input signals be surrounded by ground pads as shown.

This reduces the noise coupling onto the input signals.

3. At high sampling rates, clock signals also radiate a lot of energy.

Hence let the clock signal also be surrounded by ground pads

so that it will not interfere with differential input signals.

4. More number of VDD and VSS pads may be used in analog

circuits so that the supply to op-amps and the reference

voltages are separated.

5. Outside the chip, both analog and digital VDD and VSS can be

common. But, within the chip they must be separated as

shown.

6. Decoupling capacitors can be used separately for analog and

digital as shown in Fig. 5.29.

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Fig. 5.28 Block Layout of a Pipelined ADC

7. Power and ground wires must be as wide as possible to handle

the required currents. Low noise signals can be routed in the

space between the op-amps.

8. Use guard rings, around sensitive analog circuits. This can

avoid coupling of substrate noise.

9. If a digital signal is moving over a sensitive analog signal or vice-

versa, shielding must be provided. For example, if sensitive

analog signal is on metal1 and the digital signal is on metal3,

then analog ground in M2 layer is interposed between M3 and

M1 layers. This shielding provides isolation between the analog

and digital signals.

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Fig. 5.29 Decoupling capacitors in mixed signal chip

5.8 SPECIFICATIONS OF IMPLEMENTED ADC

The specifications of implemented 1bit/stage ADC are listed in

Table 5.6. The FFT plots for 1MHz and 20MHz inputs are as shown in

Fig. 5.30. The INL and DNL curves are shown in Fig. 5.31.

Table 5.6 Specifications of Implemented ADC

Technology 0.18μm Resolution 10 Bits

Conversion Rate 50MS/sec Supply Voltage 3.3V

Power Consumption 110mW SNDR 56.9dB at input frequency of 1 MHz

54.6dB at input frequency of 20 MHz SFDR 69dB ENOB 8.8b

INL ± 0.4 LSB DNL ± 0.22 LSB

Transistor Area 4960μm2 Temperature Range 0 to 80oC

Vref 1V

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Fig. 5.30 FFT of 1MHz and 20MHz tones sampled at 50MHz

Fig. 5.31 Measured INL and DNL

IMPLEMENTING THE 10-BIT, 50MS/SEC PIPELINED...

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