Implementation strategies for digital design · Implementation strategies for digital design Chip...
Transcript of Implementation strategies for digital design · Implementation strategies for digital design Chip...
ImplementationstrategiesfordigitaldesignChipcomplexitygrowsfasterthandesignproductivity
From1980:DesigngapCompoundcomplexitygrowthrate(#transistors/chip): 58%/Year
Compoundproductivitygrowthrate(Transistor/Person-month): 21%/Year
à Teamsizeincreases(now1000)
Productivityleapsareduetotheintroductionofnewdesigntechnologies
Time:70s
ProgrammableLogicArrays
Standardcells
Macrocells,modulecompilers
Gatearrays
Reconfigurablehardware
ComplexdigitalICs(e.g.Microprocessors)
Memory
Datapath
ControlInterconnects
andI/O
To e
xter
nal w
orld
Combinatorialfunctions,arithmeticoperators,(customcellsorautomatedstandardcells)
[RO,RW][single-portaccess,multiportaccess][DRAM,SRAM,NVM](regularmacrocells) FiniteState
Machine(standardcells)
Onchip-buses,meshinterconnects(macrocells)
Semiautomaticplacementandrouting
Memory
Datapath
ControlInterconnects
andI/O
To e
xter
nal w
orld Somewhat
regular
Very regular structure
Ad hoc structure
Very regularstructure
Powerandclockdistributionsare
criticalandrequiredforallgates.
Intel4004– customdesign
Courtesy Intel
2300PMOS
10µmprocess
Clock:108KHz
Area:3mmx4mm
TransitiontoAutomationandRegularStructures
Intel 4004 (‘71)Intel 8080 Intel 8085
Intel 8286 Intel 8486Courtesy Intel
Tradeoffbetweenflexibilityandefficiency
- Reusabledesignofmultipleapplications
- Generichardwarewithupgradablesoftware
DISADVANTAGES:- Lossinperformance:
largeoverheadandsloweroperation(instructiondecoding)
- Increaseinenergyconsumption:samereason.
CustomHardwired(fixedatmanufacturing)
ConfigurableHW(parameters)
Applicationspecificprocessor(DSP,GPU)
Embeddedmicroprocessor
Energyefficie
ncy Flexibility
ADVANTAGESofFlexibility(Programmability):
Costofanintegratedcircuit
Totalcostof1chip=
RecurringExpenses(Variablecosts)
ProportionaltotheSalesvolume
NonRecurringExpenses(Fixedcosts)
IndependentoftheSalesvolume
+
Variablecostof1chip + fixedcosts#ofchips
NRE(Fixed Costs)andRE(Variable Costs)
NRE= Time&Person Months required forthedesign+productionequipment related tothespecific chip
costofdie + costofdietest + costofpackagingfinaltestyieldRE=
% of good chips
costofdie = costofwafer#diesperwafer×dieyield
% of good dies
DieYieldEmpiricalformula(foramodern CMOSprocess <~3)
Dieyield = 1 + #defectsperunitarea×diearea<AB
Forexample:1defect/cm2
Diearea Yield0.025cm2 99%0.25cm2 78%2.5cm2 16.2%
0%
20%
40%
60%
80%
100%
0 0,5 1 1,5 2 2,5
DieYield(%)vsDieArea(cm2)
Implementation approaches todigital design
Customdesign Semi-customdesign
Cellbased
Standardcells Macrocells
Arraybased
Gatearray Reconfigurablelogic (FPGA)
Customdesign
Transistorbytransistordesignofcompletecircuit• [+]Highperformance• [-]Timeconsumingà Highcost ofdesign
à Hightimetomarket
WHEN Blocks that have tobeused many times
e.g.Library Cells
Very high volumeICs e.g.MicroprocessorsCost is not anissue e.g. defenseapplications
e.g.supercomputingapplications
Cell-based semicustom design
We need alibrary ofcells tobeused forthedesign
Type oflibraryStandard cells Logic gates,
MSIcircuits:Decoders,multiplexes,encoders
Macrocells MemoryBankMegacells Microprocessor, DSP,PCIinterface
1st generationStandardCell— Example
[Brodersen92]
Rows for cells
Rows for cells
Routing channel
Not very dense– lot ofspace used bytherouting channels
StandardCell– TheNewGeneration
Cell-structurehidden underinterconnect layers
Much denser structure: no space occupied by routing channelsRouting occurs through higher interconnect layers
Designat ahighlevel ofabstractionHardwaredescriptionlanguage
Logicsynthesystools
Gate-leveldesign
Placementandrouting
toolsStandardcell
layoutTofoundry
Suitable toFabless industry model
Fabless company Design+Testing +Sale
e.g.Marvell, QualcommDialog Semiconductor,Altera,Xilinx
Foundry Fabrication +Standard cells forFabless
e.g.TSMC, UMC, SMIC
IDM (IntegratedDeviceManufacturer)
Design+Fabrication +Testing +Sale
e.g.INTEL, SamsungSTM
IPVendor Macro cell librarySoftMacromodulesIP
e.g. ARM
Macrocells orMacromodules
HardMacrocells
Customdesignedfor aspecific CMOSprocess
Predetermined functionalityANDPredetermined physicalimplementatione.g.embeddedmicroprocessor,embeddedmemory
SoftMacrocells
Portable todifferentCMOSProcesses(GateNetlist)
Predetermined functionalitybut NOphysical implementationTypically provided byIPvendors [withsoftwaretools,testing procedures andtools]
MacroModules
256´32 (or 8192 bit) SRAMGenerated by hard-macro module generator
SoftMacroModules andIP
Synopsys DesignCompiler
Semicustomdesignflow
1. Designcapture Schematic+VHDL+IPblocks
2. LogicSynthesys Gate netlist+Placementandroutingconstraints
3. Pre-layoutsimulationandverification
4. Floorplanning5. Placementand
routingLayoutandMasks
6. Electrical circuitextraction
7. Post-layoutsimulationandverification
Array-basedimplementation
Donotrequireacompletemanufacturingrun
Gatearray(orSeaofgates)
Mask Programmablearrays
Prediffusedwafers,ONLYMetallayersaremissing
FieldProgrammableGateArray(FPGA)
Completeseparation betweenthemanufacturingphaseandtheimplementationphase
Manufacturing phasehaslargevolumes[+]ShortTime-to-marketandLOWNRE[- ]PerformancelossandHIGHRE
Howarecellsprogrammed
Fuse-basedFPGA[WriteOnce]– Fuse: Normallyshortcircuits(ahighcurrentcanblowupthefuse)
– Antifuse:NormallyOPENcircuit(ahighvoltagecancauseoxidebreakdownandshortcircuit)
NonvolatileFPGA
SRAM-basedFPGA
Whattypeoflogiccanbeprogrammed?
Array-basedprogrammablelogic(e.g.PLA,PAL)
Any combinatorialfunction[any AND-ORFunction]
Cell-basedprogrammablelogic
Out
ln1 ln2
Memory In Out
00 00
01 1
10 1
11 0
Look Up Table based logic cells: Any combinatorial logic
Seaofgates
Random Logic
MemorySubsystem
LSI Logic LEA300K(0.6 µm CMOS)
Courtesy LSI Logic
RAM-basedFPGA
Xilinx XC4000ex
Courtesy Xilinx
XilinxVirtex UltraScale
ICProduction– Installedcapacity
ICProductionBreakdownbyRegion
Korea, Japan ~ 2x EuropeTaiwan ~ 3x Europe