Implementation strategies for digital ics
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Transcript of Implementation strategies for digital ics
IMPLEMENTATION STRATEGIES FOR DIGITAL ICS
GROUP MEMBERS● NAYYAR ● SIDRA● MAJIDA
TABLE OF CONTENTS
● INTRODUCTION
● VLSI DESIGN CYCLE
● MOORE’S LAW
● PRODUCTIVITY GROWTH RATE
● DESIGN IMPLEMENTATION STRATEGIES
● COMPARISON
● DISCUSSION
VLSI
VLSI – Very Large Scale IntegrationRefers to the many fields of electrical and computer engineering that deal with the analysis and design of very dense electronic integrated circuits
VLSI DESIGN CYCLE
SYSTEM SPECIFICATION
FUNCTION DESIGN
LOGIC DESIGN
CIRCUIT DESIGN
PHYSICAL DESIGN
DESIGN VERIFICATION
FABRICATION
PACKAGING,TESTING AND DEBUGGING
A SIMPLE PROCESSOR
MEMORY
DATAPATH
CONTROL
INPU
T-OU
TPUT
BUILDING BLOCKS FOR DIGITAL ARCHITECTURE
Arithmetic unitBit-sliced data path ( Adder, comparator, shifter, multiplier etc.) Memory- RAM, ROM, Buffers, Shift registers
Control- Finite state machine (PLA, random logic.)- Counters
Interconnect- Switches- Arbiters- Bus
STEPS TO CONSTRUCTION IN VLSI
• Start with a design team• Then move to a design hierarchy• Digital design is usually based on some type of Hardware Description Language (HDL)• Choice is based on the following: Design complexity Timing requirements Area requirements Power requirements Project Schedule and Resources
Gordon Moore (Intel)The number of transistors on a chip would double about every 18 months
MOORE’S LAW
Design productivity is usually very low. Typically 10 to 20 transistors per day, per designer.
58%/Yr. compoundComplexity growth rate
21%/Yr. compoundProductivity growth rate
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PRODUCTIVITY GROWTH RATE
DESIGN IMPLEMENTATION
IC designers have two options to implement a circuit block: I. Synthesis / Auto place and route (ASIC)
II. Custom circuit design / Custom Layout (Full Custom)
DIGITAL DESIGN
CUSTOM SEMI CUSTOM
FLOW DIAGRAM OF DESIGN IMPLEMENTATION
FULL CUSTOM DESIGN
INTRODUCTION FULL CUSTOM DESIGN
BASIC DESIGN METHOD
COST
TIME
RIGOROUS CIRCUITS
EXAMPLE
SEMI-CUSTOM
INTRODUCTION
In digital CMOS VLSI, full-custom design is rarely used due to the high labor cost.
Exceptions to this include the design of high-volume products such as memory chips, high-performance microprocessors and FPGA masters.
The standard-cells based design is often called semi custom design. The cells are pre-designed for general use and the same cells are
utilized in many different chip designs.
Problem: Full Custom design has long iteration time and upfront planning:
• Circuit designer has to plan every single detail of the block• Mask designer has to draw every polygon of the layout before we
can have fully routed design
Semi-custom flow uses an iterative approach:
• At any point during this process we can stop and have a fully routed design
• Result: better trade off between ‘how much to optimize’ vs. ‘how quick to finish’
• Extreme usage case:
DESIGN IMPLEMENTATION(CONT.)
STANDARD CELL BASED DESIGN
INTRODUCTION One of the most prevalent custom design styles. Also called semi-custom design style. Requires developing full custom mask set. Basic idea: All of the commonly used logic cells are developed, characterized, and stored in a standard cell library. A typical library may contain a few hundred cells. Inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-latches, and flip-flops.
CHARACTERISTIC OF THE CELLS
Each cell is designed with a fixed height. To enable automated placement of the cells, and routing of inter-cell
connections. A number of cells can be abutted side-by-side to form rows. The power and ground rails typically run parallel to upper and lower
boundaries of cell. Neighboring cells share a common power and ground bus. nMOS transistors are located closer to the ground rail while the pMOS
transistors are placed closer to the power rail. The input and output pins are located on the upper and lower boundaries of
the cell.
STANDARD CELL
FLOORPLAN FOR STANDARD CELL DESIGN
Inside the I/O frame which is reserved for I/O cells, the chip area contains rows or columns of standard cells.
Between cell rows are channels for dedicated inter-cell routing. Over-the-cell routing is also possible. The physical design and layout of logic cells ensure that :1. When placed into rows, their heights match. 2. Neighboring cells can be abutted side-by-side, which provides natural
connections for power and ground lines in each row.
GATE ARRAY
INTRODUCTION
In view of the fast prototyping capability, the gate array (GA) comes after the FPGA.
Design implementation of FPGA chip is done with user programming, Gate array is done with metal mask design and processing. Gate array implementation requires a two-step manufacturing process:
a) The first phase, which is based on generic (standard) masks, results in an array of uncommitted transistors on each GA chip.b) These uncommitted chips can be customized later, which is completed by defining the metal interconnects between the transistors of the array.
CONTD.
The GA chip utilization factor is higher than that of FPGA. Chip speed is also higher. More customized design can be achieved with metal mask designs. Current gate array chips can implement as many as hundreds of
thousands of logic gates.
FIELD PROGRAMMABLE GATE ARRAY (FPGA)
INTRODUCTION
User / Field Programmability. Array of logic cells connected via routing channels. Different types of cells: Special I/O cells. Logic cells. Mainly lookup tables (LUT) with associated registers. Interconnection between cells: Using fuse switches. Using antifuse elements.
CLB FUNCTIONALITIES Two 4-input function generators Implemented using Lookup Tables using 16x1 RAM. Can also implement 16x1 memory. Two Registers Each can be configured as flip-flop or latch. Independent clock polarity. Synchronous and asynchronous Set / Reset
DESIGN FLOW
FPGA DESIGN FLOW
Design Entry In schematic, VHDL, or Verilog. Implementation Placement & Routing Bit stream generation Analyze timing, view layout, simulation, etc. Download Directly to Xilinx hardware devices with unlimited reconfigurations.
IMPLEMENTATION OF A DESIGN IN FPGA
COMPARISON AMONG VARIOUS DESIGN STYLES
DISCUSSION
● Designers tend to think of a hard boundary between the two flows: ● Block containing some non-static circuits (SRAM or dynamic) end up as
Full Custom● In reality only a portion of that block is non-static● Most blocks also contain some standard CMOS circuits (data path and
control logic)● These portions can be built as ASIC or tiled standard cells.
Goal: allow designers to mix and match aspect from both ASIC and Full Custom approaches to improve productivity
Q&A
● Thank You!