Implementation of Interface Synthesis System

Implementation of Interface Synthesis System


배 영 환

1999. 9. 28.


Contents

• The Final Goal and Boundary of Research• Problem Definition• Why Interface Synthesis?• Classification of Interface Synthesis• Previous Works• One Asynchronous Interface Synthesis Algorithm• Limitation of the Algorithm• Conclusions


The Final Goal and Boundary of Research

• Final Goal– Development of New Interface Synthesis Algorithm

– Implementation of Interface Synthesis System

• Research Boundary– Asynchronous Interface Synthesis

– Input : Timing Diagram

– Output : Verilog (or VDHL) Code


Problem Definition of Interface Synthesis

P ro toco lA

InterfaceModule

P ro toco lB

- Automatically obtaining a customized implementation of the interface between two modules


Why Interface Synthesis ?

• IP(Intellectual Property) based design• Standard on-chip bus (AMBA, etc)• Separation of interface from core for reusability• Interface design is tedious and error prone task.


Classification of Interface Synthesis• Synchronization Scheme

– Asynchronous Interface– Synchronous Interface

• Communication Media– Point to Point– Bus

• Input Description– Timing Diagram– Finite State Machines (Previous Works (I))– Protocols Written in HDL (Previous Works II))


Previous Works (I)• Synthesizing Converters between Finite State Protocols

(ICCD’91 - J.Akella)– goal

• generation of the state machine of the protocol converter

– proposed approach• the FSM part of the protocol converter is obtained from the

product of protocol state machine• require a third state machine for inter protocol operation

0

12

0

1

2 3

4

Protocol A Protocol B Productprotocol

Correctinter-operationstate change

FSM forprotocol converter


Previous Works (II)• Interfacing Incompatible Protocols using Interface process

generation (S.Narayan, DAC, ‘95.)– input : HDL descriptions of the two fixed protocols– output : HDL description of the interface process

port ADDRp[7:0], ARDYp, DREQp out ;port DATAp[15:0], ARCVp, DRDYp in ;

ADDRp <= AddrVar[7:0];ARDYp <= 1;wait until (ARCVp == 1);ADDRp <= AddrVar[15:8];DREQp <= 1;wait until (DRDYp == 1);DataVar <= DATAp;

port MADDRp[15:0], RDp in ;port MDATAp[15:0] out ;

wait until (RDp == 1);MAddrVar <= MADDRp;wait for 100ns;MDATAp <= MemVar(MAddrVar);

8

8ADDRp

DATAp

ARDYp

ARCVp

DREQp

DRDYp

RDp

MADDRpMDATAp 16

16

Processor Memory (64K x 16b)Protocol : Pa Protocol : Pb


Previous Works (II)(Cont.)

• Automatically synthesis interface process using dual operations.


Previous Works (II)(Cont.)


Previous Works (III) One Asynchronous Interface Synthesis Algorithm

(By Michael Kishinevsky, DAC, ‘98, )

Timing Diagram (in Text Form)Timing Diagram (in Text Form)

Signal Transition GraphSignal Transition Graph

State GraphState Graph

State AssignmentState Assignment

Output FSM (Verilog, VHDL)Output FSM (Verilog, VHDL)


Input Timing Diagram


Building Signal Transition Graph from Timing Diagram

Timing Diagram

Signal Transition Graph (Petri Net)


Building State Graph

Signal Transition Graph (concurrent)

State Graph(sequential)


State Assignment

State Graph


Limitation of the Algorithm and Research Directions

• Single Transaction – Considering Multiple Transactions

• Control Signal Only– Adding Data Transfer Signals

• Asynchronous Interface– Extending to Synchronous Interface

• No Timing Constraint– Adding Timing Constraints


Conclusions

• Select one asynchronous interface synthesis algorithm.

• Develop improved algorithm until the end of this course.

• Implement in C language• Input : Timing Diagram• Output : Verilog (or VHDL) code

Implementation of Interface Synthesis System

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