Implementation Implementation of of

DSP Algorithm DSP Algorithm on on SoC SoC

Mid-Semester Mid-Semester PresentationPresentation

Student : Einat TevelStudent : Einat TevelSupervisor : Isaschar WalterSupervisor : Isaschar WalterAccompaning engineer : Emilia BurlakAccompaning engineer : Emilia Burlak

The project is conducted withThe project is conducted withcooperation of Rafael.cooperation of Rafael.

winter 2003/2004winter 2003/2004

Project Goals - ReviewProject Goals - Review

Studying and investigating the architecture of Studying and investigating the architecture of System on Programmable Chip (SoC).System on Programmable Chip (SoC).

Deciding on the Software/Hardware partition to Deciding on the Software/Hardware partition to be implemented.be implemented.

Implementing a signal processing algorithm on Implementing a signal processing algorithm on the chosen platform.the chosen platform.

First Semester:First Semester:• Full understanding of the elements Full understanding of the elements

and studied environments.and studied environments.• Running examples on the evaluation Running examples on the evaluation

board.board.

Project Schedule Project Schedule First Semester First Semester

1.1. Studying the VHDL programming Studying the VHDL programming language. language.

2.2. Get familiar with the FPGA structure.Get familiar with the FPGA structure.

3.3. Get familiar with the FPGA design process.Get familiar with the FPGA design process.

4.4. Studying Simulation and Synthesis Studying Simulation and Synthesis programs.programs.

5.5. Studying the Xilinx’s FPGA.Studying the Xilinx’s FPGA.

6.6. Studying Xilinx’s P&R program.Studying Xilinx’s P&R program.

11 . .Studying the VHDL Studying the VHDL Programming LanguageProgramming Language..

Self-study from the Digital Lab’s CD and Self-study from the Digital Lab’s CD and Guidance brochure of SITAL Technology.Guidance brochure of SITAL Technology.

‘‘Rules of VHDL writing for synthesis’ – Rules of VHDL writing for synthesis’ – two tutorials given by the digital lab.two tutorials given by the digital lab.

Writing a FIFO example, Using a Writing a FIFO example, Using a RAMB4_S1_S1 (4K*1 bit) component, of RAMB4_S1_S1 (4K*1 bit) component, of several implementations:several implementations:

1.1. Building a 4K*8 bit memory space.Building a 4K*8 bit memory space.2.2. Buliding a 8K*1 bit memory space.Buliding a 8K*1 bit memory space.3.3. FIFO with Overflow.FIFO with Overflow.4.4. Synchronized Fifo – using Empty/Full Flags.Synchronized Fifo – using Empty/Full Flags.

22 . .Get Familiar with the Get Familiar with the FPGA StructureFPGA Structure..

Field Programmable Gate ArrayField Programmable Gate Array

LUT

FFLUT

Logic Cell

Slice

CLB=8 LC = 4 Slices

FPGA

CLB RAM

33 . .Get Familiar with the Get Familiar with the FPGA Design ProcessFPGA Design Process..

FPGA Design:FPGA Design:1.1. Requirements – the purpose and functionality of Requirements – the purpose and functionality of

the device.the device.2.2. Architecture – Interfaces (In/Out signals) and a Architecture – Interfaces (In/Out signals) and a

general block scheme.general block scheme.3.3. Design – a specification of each block in the block Design – a specification of each block in the block

scheme.scheme.4.4. Implementation – writing the VHDL Code.Implementation – writing the VHDL Code.5.5. Simulations – both logical and using test vectors, Simulations – both logical and using test vectors,

to ensure rightness of previous stages.to ensure rightness of previous stages.6.6. Synthesis – building Gate-Level implementation.Synthesis – building Gate-Level implementation.7.7. Place & Route – building and downloading a Place & Route – building and downloading a

bitstream for the final device.bitstream for the final device.8.8. Integration and debugging.Integration and debugging.

33 . .Get Familiar with the Get Familiar with the FPGA Design Process FPGA Design Process

(cont.)(cont.)FlowFlow::

Editor

Simulator

Synth. P&R FPGA

.VHD

.EDIF

.EDN

.BIT

.EXO

44 . .Studying Simulation and Studying Simulation and Synthesis ProgramsSynthesis Programs..

4.1 Simulation program - ModelSim

44 . .Studying Simulation and Studying Simulation and Synthesis Programs (cont.)Synthesis Programs (cont.)

4.2 Synthesis program Input: .VHD file with the Input: .VHD file with the

code.code. Output: .EDIF file with Output: .EDIF file with

the implementation of the implementation of the design using the logic the design using the logic units of the chosen FPGA.units of the chosen FPGA.

Optimization of the Optimization of the design by adding design by adding constrains on signals and constrains on signals and critical paths.critical paths.

Timing analysis.Timing analysis. Provide a smooth Provide a smooth

transition to P&R.transition to P&R.

Leonardo

55 . .Studying the Xilinx’s Studying the Xilinx’s FPGAFPGA

“The Virtex II pro Family is a platform FPGA for designs that are based on IP cores and customized modules.

The family incorporates multi-gigabit transceivers and PowerPC CPU cores. It empowers complete solutions for Telecommunications, Wireless, Networking, Video and DSP applications.

Virtex II Pro devices are User-Programmable gate arrays with various configurable elements and embedded cores optimized for high-density and high-performance system designs.”

55 . .Xilinx’s FPGA (cont)Xilinx’s FPGA (cont)Components:Components:• FPGA Logic: the RTL Design.FPGA Logic: the RTL Design.• PowerPC MicroProcessor.PowerPC MicroProcessor.• CoreConnect Bus – the Processor CoreConnect Bus – the Processor

Local Bus (LPB).Local Bus (LPB).• Gigabit I/O.Gigabit I/O.Functionality:Functionality:• Serial TransceiversSerial Transceivers

(serial->parallel; parallel -(serial->parallel; parallel ->serial).>serial).

• PowerPC 405 RISC CPU (1 inst. PowerPC 405 RISC CPU (1 inst. Per cycle)Per cycle)

• I/OI/O• CLB (Comb. and Sync.) – 4 slices CLB (Comb. and Sync.) – 4 slices

& 2 3-state buffers& 2 3-state buffers• RAM MemoryRAM Memory• Clock Management circuitry Clock Management circuitry

(clock phase shifting, clock (clock phase shifting, clock multiplication And division etc.)multiplication And division etc.)

66 . .Studying Xilinx’s P&R Studying Xilinx’s P&R programprogram

Synthesis stages:Synthesis stages:

compile

Map

P & R Implement

• Code analysis

• Identification of logic structures

• First optimization

• Creating RTL View

• Implementation of structures

• Optimization

• Creating Technology View

• Placing the blocks

• WiringCreating the Physical Device

66 . .Studying Xilinx’s P&R Studying Xilinx’s P&R program (cont.)program (cont.)

ISEISE – – IIntegrated ntegrated SSoftware oftware EEnvironment nvironment

Xilinx design software suite. Xilinx design software suite. Various options to start the Various options to start the

design from (HDL, EDIF).design from (HDL, EDIF). Quick verification of the Quick verification of the

functionality of the sources functionality of the sources using the integrated simulation using the integrated simulation capabilities (ModelSim).capabilities (ModelSim).

synthesis using the Xilinx synthesis using the Xilinx Synthesis Technology (XST) as Synthesis Technology (XST) as well as partner synthesis well as partner synthesis engines used standalone or engines used standalone or integrated into ISE (Leonardo).integrated into ISE (Leonardo).

The Xilinx implementation The Xilinx implementation tools continue the process into tools continue the process into a a placed and routedplaced and routed FPGA , FPGA , and finally produce a bitstream and finally produce a bitstream for the device configuration. for the device configuration.

System ViewSystem View

PowerPC 405 Core

I-Cache

D-Cache

CoreConnect Processor Local Bus (PLB)

User Logic

External Memory

High Speed Peripherals

CoreConnect On-Chip Peripheral Bus (OPB)

Low Speed

Peripherals

PLB-OPB Bridge

FPGA Block RAM

FPGA Block RAM

Project ScheduleProject ScheduleSecond Half of First Second Half of First

SemesterSemester 1010thth week: Studying the PowerPC processor. week: Studying the PowerPC processor.

1111thth week: Studying the EDK software for week: Studying the EDK software for developing SoC. developing SoC.

1212thth week: Studying the SoC design process. week: Studying the SoC design process.

1313thth week: Get familiar with the Xilinx’s week: Get familiar with the Xilinx’s evaluation evaluation board. board.

1414thth week: Writing and Running examples week: Writing and Running examples on the on the evaluation board. evaluation board.

Thank YouThank You