Impedances Signal Integrity - DARE!! NL...SI – Signal Integrity Impedances 2018/19 Track Width top...

Impedances

Signal Integrity

www.we-online.com Impedances 2018/19

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Seite 1

Agenda

Signal Integrity – Products

• Würth Elektronik CBT

• Basics - Material parameters

• Impedance calculation - Measurement

• HDI aspects

• Low loss materials


Stefan KellerProduct [email protected]

Seite 2

Victor HaaghRegional Manager

Benelux [email protected]

www.we-online.com Impedances Seite 3 2018/19

www.we-online.com Impedances Seite 4 2018/19

SI – Signal Integrity


MICROSTRIP

Impedance - influencing factors

rε

strong

strong

low medium

w+h = layouter / manufacturert = plating process, base copper

εr = base material (dielectric)

Our offer: competent collaboration!

Seite 5

SI – Signal Integrity


Track Width

top - bottom

Dielectricspacing

Track height

Solder Resistthickness

Parameters

Seite 6

Signal Integrity: Epsilon R / Permittivity


Dielectric losses

FR4 Prepreg Type 1080

Thickness 60 - 70 µmResin content ~ 60%

FR4 Prepreg Type 7628

Thickness 170 – 190 µmResin content ~ 45%

εr Glas = 6 - 8εr Epoxy ~ 3,5

Influences: - Dielectric spacing- Frequency ….

Influence on impedance and edge steepness …

InfluenceResin content

Seite 7

Signal Integrity Epsilon R


Determination εr effective

Seite 8

Signal Integrity Impedance Models


Layer configuration:

Line configuration:

Track

Width

Gap /

separation

Track

Width

Gnd

Gnd

Single

Differential

Coplanar

Surface

Microstrip

Embedded

Microstrip

Stripline

Seite 9

Signal Integrity Impedance Calculation


Impedance Zo / Zdiff

Seite 10

www.we-online.com Impedances 2018/19Seite 11


T1 Cu thickness

W2Line Width (head)

εrPermittivity

FR4

H1Dielectric spacingSignal - reference

εrPermittivity

Solder Resist[typ. 3,5]

C2Thickness Solder Resist

over Cu [typ. 15 µm]

S1Gap between

Trackslayout

C1=C3Thickness Solder Resist

over FR4[typ. 42 µm]

W1Line Width (foot)

layout



Prepreg (each one ply) 1080 2113 2116

Layer spacing

above plane layer(pressed thickness , 1 oz copper L2)

68 µm

εr effective 3.5

92 µm

εr effective 3.6

108 µm

εr effective 3.8

Track Width

50 Ω Single Impedance109 µm

(with εr 4.2: 94 µm)

154 µm

(with εr 4.2: 136 µm)

179 µm

(with εr 4.2: 165 µm)

Track Width

Track Separation

100 Ω diff. Impedance

100 µm

305 µm

100 µm

137 µm

100 µm

122 µm

Prepregs: TG 150°, filled, halogen freeMicrostrip Outer Layers

Seite 12

Signal Integrity Impedance calculation

www.we-online.com Impedances 2018/19Seite 13

8 - Layers

WE-Articel No.:

Customer:

Raw-

MaterialCU

Dielectric

constant

Final

Thickness

Customer

requirements

Customer WE [εr] [µm] [µm]

TOP/VS Ref Foil 17.5 µm 17

3.5128

2 S1 S2 35 µm 33

0,150 mm 3.9150

3 Ref Ref 35 µm 33

3.5 128

4 35 µm 33

0,410 mm 4.3410

5 35 µm 33

3.5 128

6 Ref Ref 35 µm 33

0,150 mm 3.9150

PREPREG

1)

2 x 1080

configuration

2 x 1080

Build Up

2 x 1080

ML 8

layer description

Impedance calculation:

S1 Zo 50 Ohms @ 119 µm track width

S2 Zo 50 Ohms @ 236 µm track width

S2 Zdiff 100 Ohm @ 100 / 115 / 100 µm

Signal Integrity Impedance Measurement


Technology TDR(Polar Instruments)

Crossovertest prod - PCB

Seite 14

Signal Integrity Impedance Measurement


23 mm

28 mm

150 mm

Single150 x 23 mm

max. 6 measurements

Differential150 x 28 mm

max. 2 measurements

Impedance Report

on TCs

Seite 15

Signal Integrity HDI


Version 1:PTH

Version 2:Microvia / Buried Via

“Open ended antennas”

Seite 16

Discontinuities in possible wiring schemes

Blind and Buried Viasresult in reduced discontinuities!

HDI instead ofexpensive RF Mat.

Spread Glas



Layer 1 GND

Layer 2 Signal 1

Layer 3 Signal 2Layer 4 GND

Layer 1 GND

Layer 2 Signal 1

Layer 3 Signal 2

Layer 4 GND

Seite 17



Layer 2 / 11 Layer 3 / 10

TypEdge Coupled

Offset strip lineEdge Coupled

Offset strip line

Distance layer 1 / 12 GND 130 µm 211 µm

Distance layer 4 / 9 GND 181 µm 100 µm

Cu Thickness T 30 µm 16 µm

Upper trace width Wup 82 µm 95 µm

Lower trace width Wlow 100 µm 100 µm

Separation S 214 µm 152 µm

Substrate Dielectric εr 3.8 / 3.5 / 3.8 3.8 / 3.5 / 3.8

Impedance 100,0 Ω 100,0 Ω

Core

Prepreg

Wlow

H1 = 130 µm

H2 = 81 µm

H3 = 100 µm

Wup

S

layer 1 / 12 GND

layer 2 / 11 Sig

layer 3 / 10 Sig

layer 4 / 9 GND

T = 30 µm

T = 16 µm

Seite 18



Almost without impedance restricions

Layer spacing ~ 100 µm

Track Width 90 µm

Example:

INTEL Atom

Pitch 0.593 mm diagonal

Seite 19

Signal Integrity


High Frequency – High Speed

Next challenges:

– Low Loss Materials

• up to 10 or 25 GHz

– ELIC / Stacked Buried / Microvias as an alternative to Back Drilling as well

• especially for BGA Pitch ≤ 0.50 mm (because of the µVia Pad size)

– Very Low Profile copper foils (Skin Effekt)

– Upgrading measurement technique for High Frequency

Seite 20

Signal Integrity High Frequency


0%

500%

1000%

1500%

Kern

0.1

0

Kern

0.2

5

Pre

pre

g 1

00

µm

Material Costs in Comparison(100 Panels)

FR4 Standard 100%

FR4 low CTE

Mid Performance 1

Mid Performance 2

High Performance

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Co

re

Co

re

Services


Services

Design

– Design Support

– DFM Check

– Impedance matching

– Build-ups

– Impedance measurement

– Development partnerships

12 - Lagen

WE-Artikel Nr.:

Kunde: CBT SH

BASIS-

Material CU

Dielektrizitäts-

konstante ENDDICKE

KUNDEN-

FORDERUNG

KUNDE WE [εr] [µm] [µm]

TOP/VS S1 S3 Foil 17,5 µm 16

4.25 175

2 REF 35 µm 33

0,100 mm 3.8 100

3 REF 35 µm 33

3.7 134

4 S2 17,5 µm 16

0,100 mm 3.8 100

5 REF REF 17,5 µm 16

3.6 87

6 S 17,5 µm 16

0,100 mm 3.8 100

7 S 17,5 µm 16

LAGENAUFBAU

ML12

AUFBAUPREPREG

ANZAHL/TYP

2 x 1080

LAGENBEZEICHNUNG

1)

1 x 1080

1 x 2116

1 x 2113

Seite 22


ServicesSystemsProducts

Knowing the relationships - is a secret of success!

We are looking forward to good cooperation!

Stefan Keller

Product Manager

[email protected]

Victor Haagh

Regional Manager Benelux

[email protected]

Seite 23

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