Impact of Wafer and Technology Selectionon Liner Stress Mobility Enhancement

M. Mochizuki and K. FukudaOki Electric Industry Co., 550-1 Higashi-Asakawa-Cho, Hachioji, Tokyo, 193-8550, Japan

mochizuki877goki.com

Abstract - For the first time, the drain current enhancementeffect of stressed contact liner applied to various wafermaterial is discussed in this paper. The enhancement is largerin SOI and SOQ device than in bulk MOSFET. Thinner SOIfilm causes more enhancement, but saturation currentfluctuation sensitive to SOI thickness variation increasesdrastically. In case of SOS wafer, enhancement is reduced asSOS film thickness becomes thinner, because of large elasticmodulus of sapphire.

I. IntroductionTo keep Moore's law, mobility enhancement by uni-axial

stress of liner SiN is suggested by many groups. Nfetmobility enhancement presented in 2005 conferences[ 1] [2] [3]is summarized in fig. 1. In these papers, bulk, PD, FD-SOI arediscussed individually, and impact of technology selection onmobility enhancement is not clear yet. Since most papersintroduce several mobility enhancement approachessimultaneously, it is hard to separate liner effect from othereffects.

In this paper, liner mobility enhancement of major waferssuch as bulk, SO, SOQ and SOS are compared and impactof wafer structure is clarified through simulation with stresseffects. Furthermore, statistical problems arising from gatelength and body thickness are discussed.

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II. Simulation MethodAn example of simulation structure is shown in fig.2.

Simulations were performed using a three-dimensionalprocess/device simulator ENEXSS[4]. Intrinsic stress of gatepoly-Si, sidewall nitride, and liner nitride are considered as inref. [5]. Stress arising from gate oxidation is also included.

Fig.3 shows an example of 2D stress distribution and itscross section along channel direction. In the following section,difference of stress at channel center calculated with andwithout liner stress are monitored, changing substratematerial, thickness, and gate length.

III. Wafer DependenceChannel stress as a function oftop silicon thickness (Tsoi) is

plotted for SOI, SOQ, SOS and bulk devices in fig.4. In caseof SOI and SOQ wafers, stress effects are enhanced as Tsoibecomes thinner, but are reduced in case of SOS on thecontrary.SOI BOX thickness dependence is shown in fig.5. With

thick BOX such as 500nm, SOI behaves identical to SOQ,and with thin BOX, identical to bulk wafer.

Poly-SiI

liner SiN

A* * bulk* PD-SOIA FD-SOI

Il50

Lgate[nm]100

Fig 1. Mobility enhancement at various generationand various technology presented in 2005conferences[ 1] [2] [3].

Fig 2. Simulated structure of SOI. The right half ofthe device is calculated. The boundary condition ofthe channel center is Neumann. Si Substrate isthick enough for the accuracy.

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Top Silicon Thickness (nm)

Fig 4. Impact ofwafer material to Aoxx-Tsoi. SOI:solid line with filled circle. SOQ: dashed line withcross. SOS: dashed line with rectangle. BOXthickness of SOI is 200nm.

w/o SiN linerwith SiN liner ...

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Fig 3. oxx distribution. (a) 2-dimensional profile ofSOI. (b) Cross section along channel direction atsilicon surface. Solid line is oxx profile without SiNliner, and dashed line is oxx profile with SiN liner.The difference of oxx at channel center is monitoredas Ao-xx.

To confirm that these results are caused mainly bymechanical characteristics of substrate materials, simplestructure shown in fig.6 is simulated with only liner stress.In this simulation, left part not covered by SiN is assumedto be MOSFET channel. Horizontal distribution of Sisurface stress is shown in fig.6(b) and (c).Under the nitride layer, compressive stress is caused by

nitride intrinsic stress, and this causes tensile stress in

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Top Silicon Thickness (nm)

Fig 5. Impact ofBOX thickness of SOI on Tsieffect to Ao-xx. Stress effect enhancement alongwith Tsoi thickness reduction increases as BOXthickness becomes thicker.

channel region not covered by nitride. In SOS case, straincaused in sapphire is small because of its large elasticmodulus. As a result, tensile stress in channel regionbecomes smaller. Hence this effect enhances by thinnersilicon thickness, mobility enhancement by stress linerdiminishes in scaled-down SOS devices.

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IV. Gate Length DependenceTo confirm scaling effects, Tsoi dependence of different

gate lengths is plotted in fig.7. Because liner effects arealmost similar both for 0.15um and 0.1Oum, gate lengthand body thickness has small interaction for mobilityenhancement. When gate length is scaled down, SOQtakes advantage more than SOI. This means that reducingBOX thickness is not desirable for SOI scaling from thestress liner point of view.

Tsoi dependence of Drain current increase is almostsame as that of 67xx component of stress. SOQ and SOIhave more advantage than bulk and SOS.

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ness)

Covered withnnitride film

0.96 0.98 1 1.02 1.04 1.06 1.08Horizontal Distance (4m)

1.1

0 50 100 150

Top Silicon Thickness (nm)

Fig 7. Impact of gate length on Tsi effect toAo-xx. SOI: solid line with filled circle. SOQ:dashed line with cross. SOS: dashed line withrectangle.

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Fig 6. Stress simulation with simple structure to confirm thedifferences of the dependence of Tsi are caused mainly bymechanical characteristics of substrate materials (a). Crosssection along channel direction at silicon surface of variouswafer materials. (b) and BOX thickness of SOI. Left part notcovered by SiN is assumed to be MOSFET channel area.

0

0 50 100 1 50

Top Silicon Thickness (nm)

Fig 8. Drain current increase vs. Tsoi. The trends ofincrease are the same as Ao-xx, but the enhancementsare not in proportion to Ac-xx because of the influenceof the original stress without liner film.

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(a)

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V. ConclusionWafer structure dependence of stress liner effects are

studied by simulation. When top silicon layer is scalingdown, SOQ takes more advantage compared to SOI andbulk devices. In case of SOI, stress effect becomesidentical to SOQ with thick BOX, and identical to bulkwith thin BOX. Scaled-down SOS takes less advantage ofstress liner. Gate length has small interaction on Tsoidependence of stress effects.

REFERENCES[1] Symp. VLSI Tech. Dig. 2005.[2] SSDM Ext. Abs. 2005.[3] IEDM Tech. Dig. 2005.[4] T. Wada and N. Kotani, "Design and Development of3-dimensional Process Simulator," IEICE Trans.Electron.,E82-C, pp. 839-847, 1999.[5] V. Senez et al., "Investigations of Stress Sensitivity of0.12 CMOS Technology Using Process Modeling," IEDMTech. Digest, pp. 38.1.1-38.1.4 ,2001.

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