IMPACT Seminar - University of California, San Diego
Transcript of IMPACT Seminar - University of California, San Diego
March 17, 2008 CMP
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IMPACT
Title: Past, present, and future of CMP
Faculty: David Dornfeld
Department: Mechanical Engineering
University: Berkeley
IMPACT Seminar
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• CMP Overview
• CMP History and Future Development (courtesy
of Ken Cadien, formerly of Intel (Fellow Emeritus)
and now Professor and Canada Research Chair in
Nanofabrication, University of Alberta, Department
of Chemical & Materials Engineering)
- slurries and pads
• Towards design for manufacturing (DFM) for CMP
in IMPACT
Outline
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Mechanical
Phenomena
Chemical
Phenomena
Interfacial and
Colloid
Phenomena
Components of Chemical Mechanical Planarization
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Scale Issues in CMP
From E. Hwang, 2004
Scale/sizenm !m mm
Material
Removal
Mechanical particle forces
Particle enhanced chemistry
Chemical
Reactions
Active
AbrasivesPores,
WallsGrooves
Tool mechanics,
Load, Speed
critical features dies
Pad
Mechanism
Layoutwafer
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Head
Plate
n
Pad
do
wn
-
forc
e
slurry
supply
rotation
of wafer
head
Wafe
r 4-
12”
Copper
Featur
e
pad asperity
abrasive
particles
100nm-10!m
~1!
m1-10!m
Pad asperity
Abrasive
Pad/Wafer
Die
Feature/Asperity
Abrasive Contact
CMP phenomena at different scales
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Cadien Cadien OutlineOutline
•• History 1984-2008History 1984-2008
•• Challenges andChallenges and
solutions: slurries andsolutions: slurries and
padspads
–– Next 10 yearsNext 10 years
•• Very long TermVery long Term
•• ConclusionsConclusionsSource: K. Cadien, “The Future of CMP: Slurries and pads,” Keynote
presentation, CMP-MIC, Fremont, March 4, 2008.
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IMPACT
History circa 1984History circa 1984
The semiconductor industry thought that scaling was done
at the 1.0 mm dimension due to topography
Topography 3 µm
Topography > DOF !
Source: K. Cadien, “The Future of CMP: Slurries and pads,” Keynote
presentation, CMP-MIC, Fremont, March 4, 2008.
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History 1984History 1984
“Karey Holland remembers her reaction one day
in 1984 when a colleague, Bill Cote, at IBM
recommended that she use what seemed for all
the world like a scrub pad and a scouring liquid for
one of the critical steps in processing the silicon
wafers that contained the next-generation
memory chips”.
“The idea of exposing the wafer surface to billions
of abrasive particles did not sit well with her.
‘You’re not going to put that dirt on my wafer,’ she
protested”.Source: Scientific American Magazine, February 1998
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IMPACT
Interconnect Scaling
500 nm
ILD planarization, W plugs w etch
back
130 nm
Six Cu Layer
350 nm
Four Al metal layers, W polish, PSG
180 nm
Six Al Metal layers
250 nm
Five Al metal layers,
SiOF
65 nm
Eight Cu
Layer
90 nm
Seven Cu
Layer
1000 nm
Two Al Metal layers,
BPSG
Oxide PolishSTI PolishPoly PolishTungsten PolishCopper PolishBarrier PolishWet Station CleanDSS cleanDry in/Dry out
Manymilestones
Enable
d by
CMP
Source: K. Cadien, “The Future of CMP: Slurries and pads,” Keynote
presentation, CMP-MIC, Fremont, March 4, 2008.
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Transistors have also been enabled by CMPTransistors have also been enabled by CMP
Don Scansen, “Under the hood of Intel’s 45nm technology”, WWW.semiconductor.com
Source: K. Cadien, “The Future of CMP: Slurries and pads,” Keynote
presentation, CMP-MIC, Fremont, March 4, 2008.
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CMP’s Attributes• CMP improved yield
•Removes defects
• CMP reduced electromigration
• CMP enabled optical lithography
• CMP enabled novel integration
schemes•Cu damascene technology
• Enabled upstream modules•CVD
•EPSource: K. Cadien, “The Future of CMP: Slurries and pads,” Keynote
presentation, CMP-MIC, Fremont, March 4, 2008.
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IMPACT
5-inch FSM5-inch FSM
The Future (next 10 years)
CMP Applied to Many Non-IC
Applications (Courtesy Cabot Microelectronics)
Ref: K. Cadien, “The Future of CMP: Slurries and pads,”
Keynote presentation, CMP-MIC, Fremont, March 4, 2008.
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Challenges for the IC IndustryChallenges for the IC IndustryThe next 10 yearsThe next 10 years
•• Integrating porous Integrating porous ILDsILDs
•• Improving copper dishing, erosion, defects;Improving copper dishing, erosion, defects;
many more metal layersmany more metal layers
•• More tune ability for STI, W, barrierMore tune ability for STI, W, barrier
•• Polishing novel materialsPolishing novel materials
•• 450 mm wafers?450 mm wafers?
•• 1.5 mm edge exclusion?1.5 mm edge exclusion?
Source: K. Cadien, “The Future of CMP: Slurries and pads,”
Keynote presentation, CMP-MIC, Fremont, March 4, 2008.
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ITRS 2007ITRS 2007
PLANARIZATION POTENTIAL SOLUTIONS, pg 24PLANARIZATION POTENTIAL SOLUTIONS, pg 24
Slurries and
Pads
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250 nm
chip 32 nm chip
Oxide
SiON
Poly
Nitride
Doped Ox
Doped Si
W
Ti(N)
Cu
Low K
High K
Ni Silicide
Ru +Ta(N)
ULK
Al(Cu)
A Variety of Materials
Make Up Chip Surfaces
Source: Spiro et al, Proceedings 2007 ICST Conference, Shanghai.
60 Elements (Potential)
15 Elements
Smaller Traces; New Materials,
Processes and Designs
Semiconductors Have Changed
Source: K. Cadien, 2008.
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Oxide Rate2500
NitrideRate
1000
0 0
2500
0 Å/min
Poly
Rate
Fully Tunable Oxide, Nitride, and Poly Polish( Courtesy Cabot Microelectronics)
Source: K. Cadien, “The Future of CMP: Slurries and pads,”
Keynote presentation, CMP-MIC, Fremont, March 4, 2008.
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Designers Are Demanding More Choice:Example – Tungsten Tunability
SIN
Ti/TiN
PETEOS
Pad Ox
AP-USG
SIN
PETEOS
Pad Ox
AP-USG
Non-Selective
W
SIN
PETEOS
Pad Ox
AP-USG
Selective
i.e.W2000 i.e. W7300Courtesy Cabot Microelectronics
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CMCCMC’’s Epic® D100 Pad - New Pad Process:s Epic® D100 Pad - New Pad Process:
Continuous Extrusion, Supercritical CO2, High Density Continuous Extrusion, Supercritical CO2, High Density
Courtesy Cabot MicroelectronicsSource: K. Cadien, “The Future of CMP: Slurries and pads,”
Keynote presentation, CMP-MIC, Fremont, March 4, 2008.
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• Material Selection and Control– Interspersed Long/Short Chain Polymers
– Optimize Number and Regularity of Hard/Soft Domains
– Control Phase and Void Composition
• Material Processing: Liquid Casting
– Custom Tuned Texture Across the Pad
– Unique Elastic, Viscoelastic and Thermal Properties
Both material and processing knobs allowtunability and extensibility of pad properties
CMP Pads Optimized for Application PerformanceCMP Pads Optimized for Application Performance
Source: K. Cadien, “The Future of CMP: Slurries and pads,”
Keynote presentation, CMP-MIC, Fremont, March 4, 2008.
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Materials/Process Design: RationaleMaterials/Process Design: Rationale
•• Numerous small hard and soft domainsNumerous small hard and soft domains
–– control tribological and thermal propertiescontrol tribological and thermal properties
–– stable and extended boundary lubrication regimestable and extended boundary lubrication regime
•• Specific curativesSpecific curatives
–– control elastic and control elastic and viscoelastic viscoelastic propertiesproperties
•• GradingGrading
–– improve across the wafer uniformity w/o compromisingimprove across the wafer uniformity w/o compromisingplanarization efficiencyplanarization efficiency
•• Solid lubricantSolid lubricant
–– reduce motor torque during polishreduce motor torque during polish
–– lower friction and lower shear w/o compromising RRlower friction and lower shear w/o compromising RR
•• Extended & lower COFExtended & lower COF
–– lower dishing/erosion and stacking faultslower dishing/erosion and stacking faults
–– lower stress on low k dielectrics during CMPlower stress on low k dielectrics during CMP
Neopad, Ra ~2.35um
Source: K. Cadien, “The Future of CMP: Slurries and pads,”
Keynote presentation, CMP-MIC, Fremont, March 4, 2008.
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Innovative Pad Design Enhanced Performance
•• Solo pad technology Solo pad technology w/ w/ soft & hard segments in the polymer matrix:soft & hard segments in the polymer matrix:–– Improved planarity within die and within waferImproved planarity within die and within wafer
–– Improved non-uniformity and low edge exclusionImproved non-uniformity and low edge exclusion
–– Reduce Reduce microscratches microscratches and lower defectsand lower defects
–– Competitive material polish ratesCompetitive material polish rates
•• Pad technology designed Pad technology designed w/ w/ ““tunabilitytunability”” feature for each application: feature for each application:–– Provides a novel key process parameter to improve CMP processProvides a novel key process parameter to improve CMP process
performance for current and advanced technologiesperformance for current and advanced technologies
•• Differentiated Pad Manufacturing Concept: Compression moldedDifferentiated Pad Manufacturing Concept: Compression molded– In-situ pad grooves ensure uniform, high integrity profiles and provide
better slurry distribution and efficiency
– Enables significant batch-to-batch process control
•• Lower CoO:Lower CoO:– Material cross-linking: lower wear rates and >2X extended pad life
– Reduced slurry usage (20-30% reduction)
– Less defect addersSource: K. Cadien, “The Future of CMP: Slurries and pads,”
Keynote presentation, CMP-MIC, Fremont, March 4, 2008.
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Very long term - circa 2030
•• There is definitely an inflection pointThere is definitely an inflection point
occurring in the next 20 yearsoccurring in the next 20 years
• Both transistors and interconnects
face fundamental change
Source: K. Cadien, “The Future of CMP: Slurries and pads,”
Keynote presentation, CMP-MIC, Fremont, March 4, 2008.
Running out of elements for both
transistors and interconnects
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ITRS 2007 Emerging Research DevicesITRS 2007 Emerging Research Devices
Source: K. Cadien, “The Future of CMP: Slurries and pads,”
Keynote presentation, CMP-MIC, Fremont, March 4, 2008.
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Cu interconnect scaling is an issue long term
Source: S. M. Rossnagel and T. S. Kuan, “Alteration of Cu conductivity in the size effect regime”, J. Vac.
Sci. Technol. B 22.1., Jan-Feb 2004
Source: K. Cadien, “The Future of CMP: Slurries and pads,”
Keynote presentation, CMP-MIC, Fremont, March 4, 2008.
Resistivity increases with
reduced film thickness
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Could Al replace Cu?
Source: P. Kapur, J. P. McVittie, and K. C. Saraswat, “Technology and
Reliability Constrained Future Copper Interconnects—Part I: Resistance
Modeling”, IEEE Trans. On Electron Devices, 49, (2002) 590-597
Timing depends on barrier
thickness, resistivity
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500 nm
ILD planarization, W
plugs w etch back
130 nm
Six Cu Layer
350 nm
Four Al metal
layers, W polish,
PSG?
180 nm
Six Al Metal layers
250 nm
Five Al metal
layers, SiOF
1000 nm
Two Al Metal
layers, BPSG
Interconnect Scaling & Future Options
65 nm
Eight Cu
Layer
90 nm
Seven Cu Layer
Laser
µP
Optical
modulator
Receiver
circuit
Transmitte r
circuit
Optical WG
Photodetector
Optical
Coupler
Laser
µP
Optical
modulator
Receiver
circuit
Transmitte r
circuit
Optical WG
Photodetector
Optical
Coupler
CNT
?
Optical
3D
Options
After severalgenerations of scaling
Source: K. Cadien, “The Future of CMP: Slurries
and pads,” Keynote presentation, CMP-MIC,
Fremont, March 4, 2008.
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What does all of this mean for CMP?What does all of this mean for CMP?
• Hard to predict
– Depends on integration scheme
• CMP’s attributes will be relevant
– CMP does improve yield so whatever the
scheme this may be useful
– Scattering in interconnects is due partially to the
roughness of the interconnect...CMP does
smooth...Cu and optical
• There is some hope that CMP will be around
in 2030Source: K. Cadien, “The Future of CMP: Slurries
and pads,” Keynote presentation, CMP-MIC,
Fremont, March 4, 2008.
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Summary
Next 10+ years
Continuous improvement
Pad & slurry tunability
New materials
2030 and beyond
3D then optical
Transition/paradigm
shift in 10-20 years
Depends on design,
architecture, etc.
Source: K. Cadien, “The Future of CMP: Slurries
and pads,” Keynote presentation, CMP-MIC,
Fremont, March 4, 2008.
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Cadien’s Summary
• For the next decade or more
- CMP will need to do continuous improvement
•Improved defects, dishing and erosion
•Increased tunability for slurries
•New slurries for new materials
•Novel pads with more tunability to enable the
above
• How is IMPACT addressing these?- process understanding embedded in process model
- stress-induced failures and reduced force polishing
- slurry behavior and slurry “design” based on mechanics
- revive “SMART pad?”
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Pad asperity
Abrasive
Abrasive Contact
Let’s zoom in…
Slurry agglomeration
Charging issues in lapping
Tribo-chemical removal
CMP induced stress
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• Present methods treat CMP process as a black box; are blind toprocess & consumable parameters
• Need detailed process understanding
– For modeling pattern evolution accurately
• Present methods do not predict small feature CMP well
– For process design (not based on just trail and error)
• Multiscale analysis needed to capture different phenomena:
– At sufficient resolution & speed
• CMP process less rigid than other processes: possibility of optimizingconsumable & process parameters based on chip design
– MfD & DfM
• Source of pattern dependence is twofold:
– Asperity contact area (not addressed yet)
– Pad hard layer flexion due to soft layer compression (addressed byprevious models)
CMP Modeling Challenges - IMPACT
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Removal Rate (RR)
Adding the electro-chemical effects
Slurry chemistry(pH, conc. of oxidizer, inhibitor
& complexing agent)
Pad propertieslayers’ hardness, structure
AbrasiveType, size & conc.
Polishing conditions(pressure P, velocity V)
• Develop a transient tribo-electro-chemical model for material removal
during copper CMP
– Experimentally investigate different components of the model
• Using above model develop a framework for pattern dependency
effects.
Polished material
Planarization,
Uniformity, Defects
Incoming topography
CMP
Model1. Passivation Kinetics
2. Mechanical Properties
of Passive Film
3. Abrasive-copper Interaction
Frequency & Force
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Conclusion
• Continuing evolution of devices and materials
• CMP offers interesting challenges at manydifferent scales
– Defect reduction
– “Predictability” for slurry/pad development
• Modeling provides driver for DfM (and MfD)
• Accommodate new applications of CMP
• Strategy must allow appropriate detail at anylevel
• Data structure should allow inheritance to linkhigher views to lower views, rapidly
• Must be well validated/calibrated
• Needs to be “user friendly”
• Requires close interaction with industry drivers