IIP2-improved Frontend Receiver using a Mismatch ... JAE-KYUNG LEE et al : IIP2-IMPROVED FRONTEND...

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.5, OCTOBER, 2017 ISSN(Print) 1598-1657 https://doi.org/10.5573/JSTS.2017.17.5.603 ISSN(Online) 2233-4866

Manuscript received Sep. 12, 2016; accepted Sep. 2, 2017 1 Korea Aerospace University, Goyang, 412-791, Korea 2 Donghyun Baek is with Chung-Ang University, Seoul, 412-791, Korea E-mail : [email protected]

IIP2-improved Frontend Receiver using a Mismatch Compensation LNA

Jae-Kyung Lee1, Donghyun Baek2, and Young-Jin Kim1

Abstract—In this letter, a second-order intercept point (IIP2) improved frontend receiver by compensating the differential mismatches is proposed. The mismatch compensation at the LNA makes the relative variation of the IIP2 to be less sensitive to the channel frequency and differential mismatch from the external components. The frontend receiver achieves an IIP2 of >56 dBm for all frequency bands without calibration. The IIP2 calibrator is designed with a digitally-tunable resistor, which increases the IIP2 of >68 dBm and reduces IIP2 variation of <10 dB. The proposed frontend receiver has a gain of >38 dB and NF of <3.6 dB with current consumption of 24 mA from a 1.8-V supply. The frontend receiver is fabricated using a 130-nm CMOS. Index Terms—CMOS, IIP2, LNA, mismatch compensation, frontend receiver, RFIC

I. INTRODUCTION

As the growth rate of the mobile applications has been saturated, the demands for low cost and highly integrated transceivers supporting the multiband and multi applications are requested. Main difficulty on reducing the bill of materials (BOM) is the SAW filter for removing the transmitter (TX) blockers, which resides between the low noise amplifier (LNA) and mixer [1]. The numerous strategies to remove the SAW filter have

been suggested [2-4]. Since the SAW filter has a function of single-to-

differential conversion, external transformer or internal active balun circuit should provide this function. However, since these components (LMSP4LMA-550) in Fig. 1 have high differential mismatches of +/-10-degree phase and +/-1 dB magnitude, causing second-order intercept point (IIP2) degradation, the mismatch correction is required [5].

A previous study reported on a simple IIP2 model, including an LO duty cycle, the second-order nonlinearity factor, the trans-conductance of the input transistor, and imbalances of the RF signals and load resistors [6]. The load resistors of the mixer were tuned using digital codes by controlling parallel-connected resistors [6, 7]. The gate bias voltage was tuned to adjust the IIP2 using a digital-to-analog converter (DAC) by improving LO duty mismatches [8]. The output voltages at the load were tuned to balance differential signals

Fig. 1. Block diagram of the implemented proposed RX.

604 JAE-KYUNG LEE et al : IIP2-IMPROVED FRONTEND RECEIVER USING A MISMATCH COMPENSATION LNA

using the current DAC [9]. Section II analyzes the IIP2 requirements in the

SAWless receiver (RX). Section III shows the principles of the mismatch compensation in the LNA for improving the IIP2. The RX with mismatch compensation function shows improvements in IIP2 characteristics. Section IV demonstrates the measured results. Section V concludes this paper.

II. IIP2 CONSIDERATION IN RECEIVER

ARCHITECTURE

Fig. 1 shows the block diagram of the proposed front-end RX. The RX has five LNAs with the external SAWs or transformers, which operates at 850 MHz, 900 MHz, 1800 MHz, 1900 MHz and 2100 MHz, respectively. The three switching cores for mixers are employed by sharing the TIA with the RC feedback. The IIP2 calibrators are employed in the feedback circuit. The 25% duty generators are used to drive LO in the down conversion mixers.

1. IIP2 Requirement by Transmitter Leakage

The noise figure (NF) requirement of the RX is

determined by the reference sensitivity. The reference sensitivity is -117 dBm with a 3.84-MHz channel bandwidth and a 25-dB processing gain. Then, the required NF for 7-dB SNR is 9 dB. The calculated second-order distortion (PIMD2) is -105.9 dBm. The required IIP2 is calculated without considering the phase noise and third-order intercept point (IIP3) requirements, as follows.

22 2 52.6

3 710log8 24

in IMDIIP P P CF dBm

CFN

= × - + =

æ ö@ -ç ÷è ø

Q (1)

where Pin is the power at the input of the LNA, CF is the correction factor and N is the channel number.

A closed-form approximation for the CF is included [10]. The transmitter operates at its maximum power of 24 dBm at the antenna with a 20-MHz frequency separation between the TX and RX. In Fig. 2, the TX leakage power (PTX2RX = PPA - LTX,RX) remains at the RX. A typical duplexer guarantees that LTX,RX >50 dB and LTX,ANT <1.5 dB. The worst TX leakage is as high as -24.5 dBm. From Eq. (1), the calculated IIP2 with an 8-dB NF is 52.6 dBm [11].

2. IIP2 Consideration in Receiver Design

The IIP2 of the mixer depends on the duty ratio

mismatch Dh of the LO signal [6, 7]. The IIP2 of the passive mixer with 25% duty is calculated as;

( ){ }'2

8 222 2RF m

IIPA g R

pa h h

@× × D × ×D + D + ×D

(2)

where a2’ is the second-order nonlinear coefficient [6], Dh is the duty ratio of the LO signal, DARF is the input amplitude mismatch, Dgm is the transconductance mismatch, and DR is the output load mismatch.

There are two ways to improve the IIP2. First one is to minimize the second-order nonlinear coefficient (α2), second one is to zero the relative mismatch function that is composed of the LO duty, input amplitude, transconductance, and load mismatches. In this paper, the load mismatch calibration is employed to minimize the mismatch function.

III. CIRCUIT DESCRIPTION

1. Proposed Low Noise Amplifier Fig. 3(a) and (b) show the block diagram of the

conventional and proposed LNAs. The proposed LNA compensates the input signal mismatch by employing the current mirrors (M51, M52) and cross connected (M62,

Fig. 2. TX leakage power at RX with a duplexer [11].

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.5, OCTOBER, 2017 605

M52) configuration. Fig. 3(c) reveals the simulated results of conventional and proposed LNA with same conditions, which are the 12 nH external inductor for input matching. The gain, NF and S11 of conventional and proposed LNA at 1.9 GHz is 14 and 14.3 dB, 1.7 and 1.65 dB, -8 and -7.4 dB respectively. Because the S22 is not matched with 50 ohm, the S22 is not plotted. The NF is not deviated each other, even though the propose LNA employs the current mirrors and cross connected configuration. The comparison of NF reveals that the gain in the input transistors lowers the NF contribution of

the following transistors. Fig. 3(d) reveals the simulated time domain output

voltages, when the input signal has a 10° phase mismatch and 1-dB (12.3%) magnitude error [5]. The output phase mismatch of the conventional LNA is 8.5°, however the output phase mismatch of the proposed LNA is reduced to <0.1°. And, the output magnitude mismatches from 1-dB (or 12.3%) input magnitude mismatches are improved to 0.01 from 0.7 dB.

Fig. 4(a) shows the current flows for the proposed mismatch compensated LNA. The transcondcutance from the differential input voltages (vip, vin) to drain currents (ids1, ids2) is written as;

( )1 2 1

1,2 1 2 2 1 1,22ds ds m

mip in gs s L L m gs

i i gG

v v C R R R L g Cw= = =

+ + + ×

(3)

where Cgs1,2 is the input capacitances, Rs is the source resistance of 50 W, RL1 is the series resistance of the inductor L1, and RL2 is the series resistance of the degeneration inductor L2. The differential output voltages, vop and von are calculated from the drain currents and the output resistances Ro as;

(a) (b)

(c)

(d)

Fig. 3. (a) Block diagram of a conventional LNA, (b) proposed LNA with mismatch compensation, (c) Simulated results of conventional and proposed LNA, (d) Simulated outputs.

(a)

(b)

Fig. 4. (a) Proposed LNA scheme, (b) Voltage vector expression.


( ) ( )1 2

2

0 _ _ 1 1 /100 cos ( )

op op o ds o ds o

m o i mis i mis

V i R i R i R

G R A A t fw q

= × @ × + ×

= × × + + D + D

(4)

( ) ( )1 2

2

0 _ _ 1 1 /100 cos ( )

on on o ds o ds o

m o i mis i mis

V i R i R i R

G R A A t fw q

= × = - × - ×

= - × × + + D + D

(5)

where ΔAi_mis is the input amplitude mismatch and Δθi_mis is the input phase mismatch. Since the input amplitude and phase mismatches equally contribute to the differential output voltages (vop, von) due to the proposed cross connected loads with the current mirrors, the output amplitude and phase mismatches are minimized in the LNA output according to Eqs. (4, 5). Fig. 4(b) shows the vector expressions of the phases and amplitudes of the voltage signals. Fig. 5(a) shows the simulated results of the output phase mismatches. The worst mismatches of the proposed and conventional LNAs are 0.1° and 8.5°, respectively. Fig. 5(b) shows the simulated results of the output amplitude mismatches. The output magnitude mismatches from 1-dB (or 12.3%) input magnitude mismatches of those are improved to 0.01 and 0.94 dB, respectively.

Considering the mismatch compensation capability of the proposed LNA, the IIP2 of the front-end RX can be modified from Eq. (2) as;

( )'2 _

8 222norm i mis m

IIPA G R

pa h h b

@é ù× D ×D + D + Dë û

(6)

where DGm is the mismatch of the transconductance at the LNA, and b is the scaling constant. The mismatches are scaled down by the factor of b as a result of the mismatch compensation. Moreover, these results indicate that the IIP2 is less sensitive to the input magnitude mismatches. Because the 12.3% input mismatch is reduced to 0.01 dB (or 0.13%), the factor of b is approximately 95.

2. Down-conversion Mixer

In Fig. 6, a double balanced passive mixer with a

trans-impedance amplifier (TIA) is adopted. In Eq. (6), all mismatches from external components and the asymmetry at layout are zeroed by tuning the resistance values, which are connected in parallel to the feedback resistance. The IIP2 calibrator is designed with a digitally-tunable resistor and connected, as shown in Fig. 6 [7]. An MSB code is assigned to the sign, and the last 7-b codes are used to tune the resistance digitally. The coarse path, which makes a significant deviation, has 3-b control and dummy resistance. The fine path, which makes a less significant deviation, has 4-b control and dummy resistance. The dummy resistors on the two calibrators are added to minimize the phase difference via the parasitic capacitance between differential nodes. The tuning range of the resistance is designed to be lower than 1.3% at differential nodes.

In Fig. 7(a), the schematic double balanced mixer is shown and operated as a passive mixer driven by duty

(a) (b)

Fig. 5. Mismatch simulation of the proposed LNA (a) Output phase mismatch (Δθo_mis), (b) Output amplitude mismatch (ΔAo_mis).

Fig. 6. Double balanced passive mixer with 8-b IIP2 calibrator [7].


25% LO waveform. The capacitor (C1, C2) makes a role of removing glitch by LO signals and making low impedance at RF and LO frequencies. In Fig. 7(b), the 25% duty generator is designed as a high speed AND-INV-INV logic chain. Because the NAND Gate input is not symmetrical, one of the zero phase LOs is connected to the upper input, and the other is connected to the lower input. The supply voltage of the duty generator is 1.2 V, but the supply voltage of double balanced mixer is operated at 1.8 V. So, the DC bias should be shifted up to 0.9 V.

3. IIP2-improved RX with Proposed LNA

The IIP2 simulations of the conventional and proposed

RXs are carried out in Fig. 8. The simulation conditions are a 0.01% load resistance mismatch of the TIA feedback and a 10% duty mismatch (DM) between the LO signals with the same 44-dB conversion gain. In Fig. 8(a), the proposed RX with the proposed LNA has a peak of 106 dBm and an improvement of 15.5 dB at a zero ΔAi_mis. Because the DM and ΔAi_mis is set at 10% mismatch and zero, the generated IMD2 at LNA is not perfectly cancelled at the output of LNA. But, the proposed LNA has the cancellation of IMD2 cancellation in Fig. 8(b). This improvement is expected from the

scaled value at the denominator of Eq. (6). To achieve the same IIP2 of 52.6 dBm, which is the target of the SAW-less RX, the same 52.6-dBm IIP2 with a 15% worse input amplitude mismatch is achieved. The IIP2 versus amplitude mismatch is asymmetrical because the 0.01% load resistance mismatch is set. The x-axis at the IIP2 peak shifts to the negative axis. The slope of the IIP2 of the proposed RX is lower than that of the conventional RX. The merit of having a low slope according to the amplitude mismatch means that the IIP2 variation resulting from external conditions, i.e. the input mismatches, is less sensitive.

IV. MEASUREMENT RESULTS

Fig. 1 shows the block diagram of the implemented proposed RX. The RX has five LNAs, which operates at 850 MHz, 900 MHz, 1800 MHz, 1900 MHz and 2100 MHz, respectively. Since the down-conversion mixer is placed close to the LNAs, the three switching cores are employed to minimize the performance

(a)

(b)

Fig. 7. (a) Double balanced passive mixer with in-phase and quad-phase, (b) 25% duty generator with DC bias shift.

(a)

(b)

Fig. 8. (a) IIP2 simulations of the conventional and proposed RXs, (b) Current direction by IMD2 and cancellation principle.


degradation in the interconnection by sharing the TIA with the RC feedback.

For the IIP2 measurements, two-tone signals that are 20 MHz and 20.7 MHz away from the LO signals are applied to the DUT. Fig. 9 depicts the measured IIP2 according to the IIP2 control codes. The worst 57-dBm IIP2 at 900 MHz is achieved without the calibrator, and the maximum 96-dBm IIP2 at 1800 MHz is achieved with the help of the calibrator. Fig. 10(a) shows the measured IIP2 at 2100 MHz. The IIP2 of 57 dBm before calibration is improved to 82 dBm after calibration. It is predicted that the IIP2 difference of I/Q path can be caused by the duty mismatches of LO and the resistive feedback of TIA from Eq. (2). The before-and-after calibration IIP2 values at five bands are summarized in Fig. 10(b). The IIP2 at all bands is > 52.6 dBm, which is the target value of the SAWless RX.

Fig. 11 shows the measured IIP2 according the channel frequency. After the calibration is carried out at

one channel once, and the calibration code is fixed, then the frequency swept IIP2 is measured. While maintaining the calibration code, all of the channels are measured at the I-path of the 900-MHz and 1800-MHz RX. The channel variation is <10 dB, and the minimum IIP2 with the calibrated code is >68 dBm.

The in-band IIP3s are -15.2 dBm and -11.8 dBm at 940 MHz and 1840 MHz, respectively, in Fig. 12. The conversion gain of the RX is measured to be around 40 dB. The worst NF is <3.6 dB over all bands. The measured results are summarized in Table 1. The LNA, duty generator and mixer consume 10 mA, 7 mA and 5 mA, respectively. The total RX current consumption is 22 mA from a 1.8-V supply. The microphotography of the proposed RX is depicted in Fig. 13. The RX is implemented in 1P7M 130-nm CMOS technology. It occupies an area of 3.2 x 1.9 mm2.

(a) (b)

(c) (d)

Fig. 9. Measured IIP2 vs. calibration code (offset frequency = 20.0 MHz, 20.7 MHz) (a) IIP2 at 850 MHz, (b) IIP2 at 900MHz, (c) IIP2 at 1800 MHz, (d) IIP2 at 1900 MHz.

(a) (b)

Fig. 10. (a) IIP2 at 2100 MHz, (b) IIP2 measured summary at 5-bands.

(a) (b)

Fig. 11. Measured IIP2 vs. channel frequency (a) IIP2 at 900 MHz, (b) IIP2 at 1800 MHz.


In Fig. 14, the test board is shown. The test board has QFN-packaged chip, SPI control interface. The 850, 900, 1800 and 1900 MHz are tested through digitally switchable Murata SAW. The 2100 MHz are tested through another SMA port.

V. CONCLUSIONS

In this paper, an IIP2-improved front-end RX, including an LNA with differential mismatch

compensation capability, is proposed. The proposed LNA compensates the magnitude and phase mismatches coming from external inputs using the cross connected configuration. The LNA reduces the IIP2 variation to be less sensitive to the input mismatches and channel switching. Therefore, the channel switching setup time is minimized. The front-end RX satisfies the minimum IIP2 requirement for a SAWless RX after calibration. The front-end RX shows an IIP2 of >68 dBm and reduces IIP2 variation of <10 dB with a gain of >38 dB and NF of <3.6 dB.

REFERENCES

[1] R. Gharpurey, N. Yanduru, F. Dantoni, P. Litmanen, G. Sirna, T. Mayhugh, C. Lin, I. Deng, P. Fontaine, and F. Lin, “A Direct-Conversion Receiver for the 3G WCDMA Standard,” IEEE J. Solid-state Circuits, vol. 38, no. 3, pp. 556-560, Mar. 2003.

[2] C. Yu, I. S. Lu, Y. Chen, L. Cho, C. E. Sun, C. Tang, H. Chang, W. Lee, S. Huang, T. Wu, C. Chiu, and G. Chien, “A SAW-less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC,” IEEE J. Solid-state Circuits, vol.46, no.12, pp. 3047-3060, Dec. 2011.

[3] D. Kaczman, M. Shah, M. Alam, M. Rachedine, D. Cashen, L. Han, and A. Raghavan, “A Single-Chip 10-Band WCDMA/HSDPA 4-Band GSM/EDGE SAW-less CMOS Receiver with DigRF 3G Interface and +90 dBm IIP2,” IEEE J. Solid-state Circuits, vol.44, no. 3, pp. 718-739, Mar. 2009.

(a) (b)

Fig. 12. Measured IIP3 vs input power (a) IIP3 at 900 MHz, (b) IIP3 at 1800 MHz.

Table 1. Comparison and summary

This Work [3] [8] [12] [13] Unit Freq. L / M / H M / H M L / M L / M Gain 39.8 / 38 / 37.8 *55 / 62 38.5 *78.4/78 - dB NF 2.9 / 3.1 / 3.6 3.2/2.2 2.6 3.1/3.3 2.4 / 2.6 dB IIP2 (cal)

57(68) / 61(76) / 58(67) 65(90) 35(62) 50/45 55 / 50 dBm

IIP3 **-15.2/-11.8/

-11.5 - **-17.6 -11.2/ -12.4

-3.5 / 0.5 dBm

Current 22 15.1 15 55 56 / 57 mA Supply 1.8 1.5 1.5 1.3 3.7 V Process 130 90 130 65 130 nm

* RX,**inband IIP3, L:<1 GHz, M: 1-2 GHz, H: >2 GHz

Fig. 13. Microphotography of the proposed RX.

Fig. 14. Microphotography of test board.


[4] Y. Kim, J. Kim, V. Pakhomenko, D. Baek, J. Lee, E. Sung, I. Nam, and B. Park, “A Multi-Band Multi-Mode CMOS Direct-Conversion DVB-H Tuner,” in Proc. Int. Solid-State Circuits Conf., 2006, pp. 2504-2513.

[5] B. Kearns, and M. Nakazawa, “Embedded Circuit which Improves the Common Mode Response of a Balanced Output 2GHz SAW Filter,” in Proc. Int. Sym. on Ultrasonics, 2006, pp. 1069-1074.

[6] K. Kivekas, A. Parssinen, and K. A. I. Halonen, “Characterization of IIP2 and DC offsets in transconductance mixers,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 11, pp. 1028-1038, Nov. 2001.

[7] Y. Kim, Y. Son, V. N. Parkhomenko, I. Hwang, J. Cho, K. Nah, and B. Park, “A GSM/EGSM/DCS/ PCS Direct Conversion Receiver with Integrated Synthesizer,” IEEE Trans. Microw. Theory and Tech., vol. 53, no. 2, pp. 606-613, Feb. 2005.

[8] Y. Feng, G. Takemura, S. Kawaguchi, N. Itoh, and P. Kinget, “A Low-Power Low-Noise Direct-Conversion Front-End with Digitally Assisted IIP2 Background Self Calibration,” in Proc. Int. Solid-State Circuits Conf., 2010, pp. 70-71.

[9] K. Dufrêne, Z. Boos, and R. Weigel, “Digital Adaptive IIP2 Calibration Scheme for CMOS Downconversion Mixers,” IEEE J. Solid-state Circuits, vol. 43, no. 11, pp. 2434-2445, Nov. 2008.

[10] M. S. Khan, and N. Yanduru, “Analysis of Self Mixing Of Transmitter Interference in WCDMA Receivers,” in Proc. Int. Symp. on Circuits and Systems, 2006, pp. 4.

[11] J. Rogin, I. Kouchev, G. Brenna, D. Tschopp, and Q. Huang, “A 1.5-V 45-mW Direct-Conversion WCDMA Receiver IC in 0.13-mm CMOS,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2239-2248, Dec. 2003.

[12] A. Mirzaei, H. Darabi, A. Yazdi, Z. Zhou, E. Chang, and P. Suri, “A 65 nm CMOS Quad-Band SAW-Less Receiver SoC for GSM/GPRS/EDGE,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 950-964, Apr. 2011.

[13] T. Dellsperger, D. Tschopp, J. Rogin, Y. Chen, T. Burger, and Q. Huang, “A Quad-Band Class-39 RF CMOS Receiver for Evolved EDGE,” in Proc. Int. Solid-State Circuits Conf., 2010, pp. 56-57.

Jaekyoung Lee received the B.S., M.S. degrees in the department of electrical engineering, Incheon National University, Incheon, Korea, in 2005, and 2007, respectively. He is currently working towards his Ph.D. degree at Korea Aerospace Univer- sity. From 2006 to 2009, he was a

junior engineer with the Mobile TV tuner part, ADI, Soung-Nam, Korea, where he was engaged in mobile broadcasting RF receiver design. From 2009 to 2014, he was a senior engineer with the Design Team, RAONTECH, Soung-Nam, Korea, where he was engaged in mobile broadcasting RF receiver design. In 2013, He joined the school of Electrical Engineering, Korea Aerospace University, Go-Yang, Korea, where he is currently the doctor’s course of physics. His research interests include analog, RF, and mixed mode circuit designs for mobile communication, and wireless systems.

Donghyun Baek received the B.S., M.S., and Ph.D. degrees in the department of electrical engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1996, 1998, and 2003, respectively. From 2003 to 2007, he was a senior engineer with the

System LSI Division, Samsung Electronics, Ki-heung, Korea, where he was engaged in mobile broadcasting RF receiver design and led a CMOS power amplifier project for handsets. In 2007, He joined the school of Electrical Engineering, Chung-Ang University, Seoul, Korea, where he is currently an associate professor. His research interests include analog, RF, and mixed mode circuit designs for mobile communication, radar and sensor systems.

Young-Jin Kim received the B.S. degree in electrical engineering from the Kyung-pook national university in 1995, the M.S. and Ph.D. degree in electrical engineering from the KAIST(Korea Advanced Instituted of Science and Technology) in 1997 and 2002, respectively. His Ph.D. disser-

tation focused on the transceiver architecture about image rejection and spurious rejection. In 2002, he joined Samsung Electronics, Co., Ltd., Korea, as a Senior Engineer. Since then he has participated in the design of CDMA and GSM/GPRS wireless mobile application. Since then he has been designing LNA and down-conversion mixer for multi-mode CDMA and GSM/ GPRS. In 2006, He joined the school of Electronics and Information Engineering, Korea Aerospace University, Seoul, Korea.

IIP2-improved Frontend Receiver using a Mismatch ... JAE-KYUNG LEE et al : IIP2-IMPROVED FRONTEND...

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