IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-31, NO. 12, DECEMBER 1984 1969

showed a barrier height of 0.7 t o 0.8 eV across the 300 to 77 K range studied. The ideality factors were in the range of 1.0 t o 1.1 and the leakage currents were low. This allowed the device to operate over the 300 to 77 K range studied here. The structures showed very little or n o light sensitivity, in marked contrast to n-channel MODFET’s. Calculations indi- cate that transconductances of - 100 mS/mm should be achievable.

Our results indicated good potential for the hole gas MOD- FET in complementary logic applications. This paper will summarize the electrical characteristics observed and present properties of the device pertaining to complementary logic applications.

*Sponsored in part by the U.S. Army Research Office. H. L. Stormer et al., Appl . Phys. Lett., vol. 44, p. 139, 1984.

IIIA-5 Two-Dimensional Simulation of HEMT and GaAs Gate Heterojunction FET-J. Y.-F. Tang, IBM Research Center, Yorktown Heights, NY 10598.

Previous simulation studies on heterojunction devices have been limited to idealized device structures (mostly 1-D) which neglect important parasitic effects. In order to realistically simulate heterojunction devices, we have developed a general two-dimensional device simulation program and included for the first time features essential to designing and modeling real- istic devices, for examples, multilayers of heterostructure, a modified mobility model for the 2-D electron gas, Fermi level pinning at the surfaces, deep traps in the substrate, a thermionic current boundary condition at hetero-interfaces, etc. Finite difference scheme and decoupled algorithms were adopted to solve the coupled Poisson and the two-current continuity equa- tions of electrons and holes and convergence of the program at 77 K has been consistently obtained. Hot-electron effects have not been included at this stage. The surface defect states that cause the pinning of the GaAs surface potential have been assumed to be a simple SDjSA (single donor single acceptor) type. Roughly 2 x IO’* ern-' states are required t o effectively -pin the Fermi level for bulk dopings up to 2 X 1OI8 cm-3 from our prevous study.’ The same defect state levels relative to the conduction band edge are also assumed for GaAlAs.

Two types of high electron mobility heterojunction devices will be studied and compared. The first type is the conven- tional HEMT and the second type is the GaAs gate heterojunc- tion FET proposed by coworkers at this laboratory and first reported at the 1984 WOCSEMMAD (also see abstract of Solomon e t al. this conference2). The GaAs gate heterojunc- tion FET consists of a p” GaAs substrate, a thin (-500 8) undoped GaAlAs layer, and a heavily doped n+ GaAs which serves as the gate of t h e device. The access resistance to this device depends strongly on the ungated n+ to channel spacing and on the surface potential in this region. Preliminary simu- lation studies have shown that this device with one micron gate length is able t o achieve transconductances of - 100 msjmm at 300 K and e l 6 0 msjmm at 77 K, assuming a surface poten- tial of e 0 . 5 V (corresponding to a surface state density of 10 l2 in our SDjSA model) on a 0.1 pm gap. Detailed studies of the effects of low field mobility, saturation velocity, deep levels, and surface potential on the operation of these two devices will be reported. The added sophistications of our model should bring about a better understanding of the device opera- tion. The author would like to thank P. M. Solomon, s. E. Laux and J. L. Freeouf for many useful discussions.

J. Y:-F. Tang and J. L. Freeouf, “Non-uniform surface potentials and their observation by surface sensitive techniques,” presented at the 1984 PCSI, to be published in J. Vae. Sci. Technol.

2P. M. Solomon, C. M. Knoedler, and S. L. Wright, “A GaAs gate heterojunction FET,” this conference.

IIIA-6 An Analysis of Low Source Resistance HEMT with Multiple Cap Layer-S. J. Lee, Rockwell International Corpora- tion, Microelectronics Research & Development Center, Thou- sand Oaks, CA 91360 and Department of Materials Sciences, University of Southern California, Los Angeles, CA 9007, and C. R. Crowell, Rockwell International Corporation, Microelec- tronics Research & Development Center Thousand Oaks, CA 91360.

The optimization of high electron mobility transistors (HEMT) structures in a high-speed integrated circuit is essential for maximum circuit performance. We have investigated the layer parameters in a HEMT structure, in order that these can be chosen for a desired turn-on voltage, gate voltage swing, and maximum channel current density. Further optimization of the design requires a consideration of the parasitic source and drain resistance, both with respect to modeling, testing, and fabrication procedures.

Normally, the ohmic contact to the active channel in the HEMT is obtained by intrusion through the AlGaAs at a point reasonably removed from the gate electrode. This leaves an appreciable region of the device without adequate characteriza- tion. We show, however, that when the intervening GaAlAs layer is covered with a GaAs cap, the layer can not only provide passivation for the GaAlAs layer, but through appropriate structure design, an appreciable amount of electron can tunnel between the channel and the cap layer. Modeling of the tun- neling shows that the cap layer can effect an appreciable im- provement in reducing the source resistance, even when the active channel is terminated in an ideal ‘“ohmic” contact.

Our results demonstrate the range of GaAlA!, thickness over which this effect is appreciable and how the dopant and the layer structure in the GaAs cap can affect the behavior. The results are expressed in terms of a two-layer transmission line model. For a layer structure of 235-a-thick n-GaAlAs with a doping concentration of 1 X 1018/cm3 and the cap layer of n-GaAs with a doping concentration of 1 X lO1S/cm3, the characteristic coupling length is .0.85 pm, and the tunneling conductance is 8 X 1 04A/cm2-V at 300 K. If the cap struc- ture is designed in the optimized GaAs multilayer configura- tion, the tunneling conductance can exceed lo5 A/cm2-V and characteristic coupling length decreases to the order of a half micrometer. As a result of this work, parame.ters for layered growth can be selected to result in an -50-percent improve- ment in the coupling efficiency, and significant improvement in the device performance.

IIIA-7 GaAs Permeable Base Transistors Fabricated Using Organometallic Chemical Vapor Deposition*-Kirby B. Nichols, Ronald P. Gale, Mark A. Hollis, George A. Lincoln, and Carl 0. Bozler, Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, MA.

In this paper we describe the first GaAs permeable base transistors (PBT’s) fabricated using organometallic chemical vapor deposition (OMCVD) t o overgrow submicrometer tung- sten gratings. Extrapolation of microwave measurements on these devices yields a unity current gain frequency (fr) of 3 3 GHz, which matches that of any PBT fabricated to date.’ The OMCVD-overgrown PBT’s have higher transconductance, greater collector current density at a given bias, and more uni- form device characteristics than the PBT’s fabricated on a con- trol wafer that was prepared by using chloride 1:ransport vapor phase epitaxy (VPE) t o overgrow the tungsten gratings. Sec- ondary ion mass spectrometry analysis indicates that a high concentration of chlorine is present in the GaAs surrounding the VPE-overgrown gratings, but not in the Ga.As surrounding the OMCVD-overgrown gratings.

The OMCVD-overgrown PBT’s have a maximum stable gain

t 970 IEEE TRANSA:.:.IONS ON ELECTRON DEVICES, VOL. ED-31, NO. 12, DECEMBER 1984

of 1 9 dB at 10 GHz and a maximum available gain of 1 1 c l 3 at 18 GHz. Extrapolation of this maximum available gain usi l g a 6 dB/octave rolloff yields a maximum frequency of oscilla ion (fmax) of 65 GHz, compared with 100 GHz for the best 'le- vices.' The OMCVD-overgrown devices have a lower f l,lax

because their output impedance, as derived from an equiva cnt circuit model, is about an order of magnitude lower. Atten 11?ts are in progress t o fabricate PBT's with higher impedance ~ !,'or example, by reducing the doping of the overgrown GaAs 1a:er) without significantly degrading the other device parame1,ers. The performance of such devices would equal or exceed the best PBT performance so far achieved.

"This work was sponsored by the Department of the Air Force and

The U.S. Government assumes no responsibiltiy for the informa ?Ion

G. D. Alley et al., IEEE Trans. Electron Devices, vol. ED-29, no, LO,

the Defense Advanced Research Projects Agency.

presented.

p. 1708, Oct. 1982.

IIIB-1 Degradation of 77-K MOSFET Characteristics Due t o Channel Hot Electrons-Jack Y. C. Sun and Matthew R. Wordeman, IBM Thomas J. Watson Research Center, Yorktc: wn Heights, NY 10598.

The objective of this work is to identify the degradarilm mechanisms of silicon n-channel MOSFET characteristic? at 77 K as a result of channel hot-electron (CHE) damage lby theoretical analysis, 2-D simulation, and experimental verif.c:a- tion. Device design constraints for 77-K operation of cont. en- tional and lightly doped-drain (LDD) types of Si MOSFE,T's are examined.

An empirical approach was used by Ning and co-worker! t o find the CHE-limited voltages for reliable device and cirl. uit operation of small-geometry silicon M0SFETs.l However, the effects of CHE-induced trapped oxide charge and interface states on the MOSFET I-V characteristics at 77 K have ,lot been fully understood. CHE-induced degradation behaviol of LDD structures at 300 K has been reported: but the combilt::d effect of CHE damage and impurity freeze-out unique to L I D structures on their operation at 77 K has not been addressec.

Simple linear FET models were constructed to simulate :.le effect of localized trapped oxide and interface charge on :.le device I- V and transconductance. The effect of impurity free ?,e- out in the LDD region on the mobile carrier density was ca:l:u- lated using a one-dimensional model taking into account :he fringe field from the gate electrode. A two-dimensional fin le- element device analysis program (FIELDAY) was employec- as a powerful tool for the verification of CHE degradation me::h- anisms and analytical models. 300- and 77-K stress tests under maximum substrate current as well as maximum gate current conditions were performed on conventional and L.IlD types of n-channel silicon MOSFET's with various chan le1 lengths and vertical structures. Low and high drain I-V ckar- acteristics in both forward and reverse modes were monitored before and after stress tests at 300 and 77 K.

For a given CHE damage in a conventional MOSFET st1 .IC- ture, experiments showed more degradation of the current arid the transconductance at 77 than at 300 K. Simulations and models suggest that this is mostly due to the following t no mechanisms: 1 j Since the subthreshold slope at 77 K is rougilly 4 times steeper than that at 300 K, the narrow potential barrkr due to a given amount of localized CHE-induced trapped ox de and interface charge has more effect on the overall FET cun-~,:nt at 77 than at 300 K; and 2) the Fermi level is closer t o Ilne band edge at 77 K, which causes an increase in the occuparcy of the CHE-induced interface states.

For a given CHE damage in LDD structures, experime:lts again showed much more (>5 times) degradation of FET c Jr- rent and transconductance at 77 than at 300 K. Theory and

simulations show that this is caused by the strong effects of impurity freeze-out in the LDD region in addition to the mechanisms discussed above. In LDD regions with N o < 10" ~ m - ~ , only a small fraction of the donor impurities are ionized at 77 K. The CHE-induced interface state charge and oxide charge over the LDD region can then deplete the mobile charge and pinch off that region very effectively at 77 K causing a drastic reduction in transconductance.

This study provides a new understanding of the effects of CHE-induced oxide and interface trapped charge and impurity freeze-out on the operation of enhancement-mode MOSFET's a t 77 K. One important implication of these results is that the effect of CHE-induced localized damage on the MOSFET characteristics could become much severer as the operating temperature lowers and/or the channel length shortens, al- though lowering the supply voltage can alleviate the CHE damage rate. Another important conclusion is that the useful- ness of LDD structures at 77 K is further limited by the en- hanced CHE degradation due to impurity freeze-out. Free car- rrier concentration at 77 K in the LDD region is an important design parameter which has to be traded off among others such as junction depth, sheet resistance, and gate/drain overlap.

lT. H. Ning et al., IEEE Trans. Electron Devices, vol. ED-26, p. 346,

2F.-C. Hsu and H. R. Grinolds, IEEE Electron Device Lett., vol. EDL- 1979, and references therein.

5, p. 71, 1984.

IIIB-2 Mean Time to Failure Model for Hot-Carrier-Induced Degradation-K. L. Chen, S. A. Saller, I. A. Groves, and D. B. Scott, Semiconductor Group, Texas Instrustments Incorpo- rated, Dallas, TX 75265.

A study of hot-can-ier-induced device degradation has been conducted. The effect of hot-electron degradation under dc stress conditions is modeled and applied to a device design. In addition, the presence of hot-hole injection under ac stress conditions is demonstrated.

A model which predicts the mean time to failure as a result of hot-electron-induced device degradation has been developed for dc stress, conditions. This work is an extension of a pre- vious empirical model reported by Takeda and Suzuki.' How- ever, this new model for the first time describes the functional dependence of device degradation with channel length. As a demonstration, measurements were conducted to allow predic- tion of the mean time to failure for n-channel devices fabricated using a 2-pm 350-A gate oxide technology. Both the conven- tional arsenic only source/drains and the phosphorous graded, arsenic source/drains were considered. The results showed that addition of a phosphorous graded junction increased the predicted device lifetime from 70 h to 700 years. An operating voltage of 5.5 V and a failure criterion of a IO-mV threshold voltage shift were used.

In addition to the dc stress measurements discussed, the effects of ac stress were also investigated. For these measure- ments both the gate and drain were pulsed. It was found that for the same drain supply voltage, the device degraded more rapidly under ac stress conditions than,under dc stress condi- tions. By screening out the effect of trapped carriers near the drain end of the channel, using drain induced barrier height lowering, evidence of hot-hole injection was clearly observed. A plot of threshold voltage versus drain voltage showed that after dc stress, application of a sufficiently high drain voltage caused the threshold voltage to converge to its pre-stress value. However, after ac stress, the application of high drain voltages caused the threshold voltage to reduce significantly below that of its pre-stress value. The observed reduction in threshold voltage, at high drain voltages, is due to the injection of hot