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Transcript of III-V HBT and (MOS) HEMT scaling Mark Rodwell, University of California, Santa Barbara WSG Workshop:...
![Page 1: III-V HBT and (MOS) HEMT scaling Mark Rodwell, University of California, Santa Barbara WSG Workshop: Performance Metrics for mm-Wave Devices and Circuits.](https://reader035.fdocuments.in/reader035/viewer/2022062718/56649eb25503460f94bb8eee/html5/thumbnails/1.jpg)
III-V HBT and (MOS) HEMT scaling
Mark Rodwell, University of California, Santa Barbara
WSG Workshop: Performance Metrics for mm-Wave Devices and Circuits from the Perspective of the International Technology Roadmap for Semiconductors (ITRS), IEEE IMS Symposium, May 17, 2015, Phoenix
1
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THz Transistors: Systems Benefit from 5-500 GHz
precision analog design at microwave frequencies→ high-performance receivers
500 GHz digital logic→ fiber optics
Higher-Resolution Microwave ADCs, DACs, DDSs
THz amplifiers→ THz radios→ imaging, communications
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mm-Wave wireless: attributes & challenges
short wavelengths→ many parallel channelswide bandwidths available
Need mesh networksNeed phased arrays
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mm-Waves: high-capacity mobile communications
Needed: phased arrays, 50-500mW power amplifiers, low-noise-figure LNAs4
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mm-wave imaging radar: TV-like resolution
What you see in fog What 10GHz radar shows What you want to see
needs: ~0.2o resolution, 103-106 pixels
Large NxN phased array Frequency-scanned 1xN array
mm-waves → high resolution from small apertures
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InP HBTs and HEMTs for PAs and LNAs
Cell phones and Higher-Performance WiFi sets:GaAs HBT power amplifiersGaAs PHEMT LNAs
29-34GHz: emerging bands for 5GInP HBT PAs, InP HEMT LNAs ?
Later: 60, 71-76, 81-86, 140 GHz
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HeterojunctionBipolar Transistors
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Bipolar Transistor Design eW
bcWcTbT
nbb DT 22
satcc vT 2
ELlength emitter
eex AR /contact
2through-punchce,operatingce,max cesatc TVVAvI /)(,
contacts
contactsheet 612 AL
W
L
WR
e
bc
e
ebb
e
e
E W
L
L
PT ln1
cccb /TAC
8
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Bipolar Transistor Design: Scaling eW
bcWcTbT
nbb DT 22
satcc vT 2
ELlength emitter cccb /TAC
eex AR /contact
2through-punchce,operatingce,max cesatc TVVAvI /)(,
contacts
contactsheet 612 AL
W
L
WR
e
bc
e
ebb
e
e
E W
L
L
PT ln1
9
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Scaling Laws, Scaling Roadmap
HBT parameter changeemitter & collector junction widths decrease 4:1current density (mA/mm2) increase 4:1current density (mA/mm) constantcollector depletion thickness decrease 2:1base thickness decrease 1.4:1emitter & base contact resistivities decrease 4:1
Narrow junctions.
Thin layers
High current density
Ultra low resistivity contacts10
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Can we make a 2 THz SiGe Bipolar Transistor ?
InP SiGeemitter 64 18 nm width
2 0.6 m2 access r
base 64 18 nm contact width,
2.5 0.7 m2 contact r
collector 53 15 nm thick 36 125 mA/m2 2.75 1.3? V, breakdown
ft 1000 1000 GHzfmax 2000 2000 GHz
PAs 1000 1000 GHz digital 480 480 GHz(2:1 static divider metric)Assumes collector junction 3:1 wider than emitter.Assumes SiGe contacts no wider than junctions
Simple physics clearly drives scaling transit times, Ccb/Ic → thinner layers, higher current density high power density → narrow junctions small junctions→ low resistance contacts
Key challenge: Breakdown 15 nm collector → very low breakdown
Also required: low resistivity Ohmic contacts to Si very high current densities: heat
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Energy-limited vs. field-limited breakdown
band-band tunneling: base bandgapimpact ionization: collector bandgap
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THz InP HBTs: Performance @ 130 nm Node
Teledyne: M. Urteaga et al: 2011 DRC
UCSB: J. Rode et al: in review UCSB: J. Rode et al: in review
UCSB: J. Rode et al: in review
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Refractory Contacts to In(Ga)As
Refractory: robust under high-current operation / Low penetration depth: ~ 1 nm / Performance sufficient for 32 nm /2.8 THz node.
10-10
10-9
10-8
10-7
10-6
10-5
1018 1019 1020 1021
N-InGaAs
B=0.6 eV
0.4 eV0.2 eV
0 eV
Electron Concentration, cm-3
Co
nta
ct R
esi
stiv
ity
, c
m2
step-barrierLandauer
1018 1019 1020 1021
N-InAs
Electron Concentration, cm-3
0.2 eV
B=0.3 eV
step-barrier
B=0 eV
0.1 eV
Landauer
1018 1019 1020 1021
P-InGaAs
Hole Concentration, cm-3
B=0.8 eV
0.6 eV0.4 eV0.2 eV
step-barrierLandauer
32 nm (2.8THz) node requirements
Baraskar et al, Journal of Applied Physics, 2013
Why no ~2THz HBTs today ?Problem: reproducing these base contacts in full HBT process flow
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Refractory Blanket Base Metal Process (1)
Metal deposited on clean surface; no resist residue
Refractory Ru contact layer→ low penetration depth
2nm Pt reaction layer→ penetrate surface contaminants15
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Refractory Blanket Base Metal Process (2)
0 100
5 1019
1 1020
1.5 1020
2 1020
2.5 1020
0 5 10 15 20 25
dopi
ng, 1
/cm
3
depth, nm
2 nm doping pulse
1018 1019 1020 1021
P-InGaAs
10-10
10-9
10-8
10-7
10-6
10-5
Hole Concentration, cm-3
B=0.8 eV
0.6 eV0.4 eV0.2 eV
step-barrierLandauer
Co
nta
ct R
esis
tivi
ty,
cm
2
32 nm noderequirement
Increased surface doping: reduced contact resistivity, but increased Auger recombination.
→ Surface doping spike at most 2-5 thick.
Refractory contacts do not penetrate; compatible with pulse doping. 16
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Blanket Base Metal Process
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Parasitics along length of HBT emitter
Base pad & feed increases Ccb
Emitter undercut actual junction shorter than drawn. → excess Ccb , excess base metal resistance
Base metal resistance adds to Rbb
all these factors decrease fmax
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Emitter Length Effects: Decreased fmax
Results from finite-element modeling
cbmax 8
f=f
τπτ
On a 2 μm emitter finger, effect of base metal resistance can be comparable to adding 3 Ω-μm2 to the base contact resistivity !
base metalsheet resistance
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Reducing Emitter Length Effects
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Reducing Emitter Length Effects
Small Base Post Undercut
large base post
befo
relargeemitter endundercut
after
Large Base Post Undercut
small base post
small emitter endundercut
J. Rodein review
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Reducing Emitter Length Effects
before after
thicker Au layer in base metal→ smaller sheet resistivity
narrowercollector-basejunction
smaller contact penetration into baseJ. Rodein review
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200nm emitter InP HBT
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200nm emitter width: High Fmax
fmax is high:
...even at 2.9 mm emitter length
...even at 200nm emitter width
J. Rode
in review
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160nm emitter width: Unmeasurable Fmax
on HBTs with
...shorter 1.9 mm emitter length
...narrower 170nm emitter width
fmax cannot be measured because of calibration difficulties (small Y12)
fmax probably above 1.1THz, but we cannot prove this.
Better fmax measurement would require on-wafer LRL standards.
We no do not at presenthave the resources to pursue this.
J. Rode
in review
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Regrowth for high b in THz HBTs ?
2-3 THz fmax HBTs need ~1.5*1020 cm-3 doping under base contacts→ high Auger recombination→ low b.
Desire: high doping under contacts, lower doping elsewhere.
Regrowth processes enable this.
1018 1019 1020 1021
P-InGaAs
10-10
10-9
10-8
10-7
10-6
10-5
Hole Concentration, cm-3
B=0.8 eV
0.6 eV0.4 eV0.2 eV
step-barrierLandauer
Co
nta
ct R
esi
stiv
ity,
cm
2
TLM data, not HBT
32 nm requirements
26
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THz InP HBT Scaling Roadmap
130nm node: 550GHz f t , 1100 GHz fmax
Are the 64 nm and 32nm nodes feasible ?
Key challenge: base contacts
Recent demonstration of <2 -W mm2 contacts in HBT process flow. Longer term challenge : decoupling doping under contacts vs. under base
27
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86 GHz InP HBT Power Amplifier UCSB/Teledyne
Gain: 20.4dB S21 Gain at 86GHz
Saturated output power: 188mW at 86GHz
Output Power Density: 1.96 W/mm
PAE: 32.8%
Technology: 250 nm InP HBT
High W/mm, very small die1.4 mm x 0.60 mm
Park et al, JSSC, Oct. 2014 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6847236&tag=1
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81 GHz InP HBT Power Amplifier UCSB/Teledyne
Gain: 17.4dB S21 Gain at 81GHz
Saturated output power: 470mW at 81GHz
Output Power Density: 1.22 W/mm*
PAE: 23.4%
Power/(core die area): 1020W/mm2
Technology: 250 nm InP HBT
*design error: IC should have produced Psat=700mW, ~2 W/mm
High Power, very small die0.82mm x 0.82 mmPark et al, JSSC, Oct. 2014 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6847236&tag=1 29
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214 GHz InP HBT Power Amplifier UCSB/Teledyne
Gain: 25dB S21 Gain at 220GHz
Saturated output power: 164mW at 214GHz
Output Power Density: 0.43 W/mm
PAE: 2.4%
Technology: 250 nm InP HBT
(no die photo) 2.5mm x 2.1 mm
Reed et al, 2014 CSICS http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6659187&tag=1 30
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InP HBT Integrated Circuits: 600 GHz & Beyond 614 GHz fundamentalVCO
340 GHz dynamic frequency divider
Vout
VEE VBB
Vtune
Vout
VEE VBB
Vtune
620 GHz, 20 dB gain amplifierM Seo, TSCIMS 2013
M. Seo, TSC / UCSBM. Seo, UCSB/TSCIMS 2010
204 GHz static frequency divider(ECL master-slave latch)Z. Griffith, TSCCSIC 2010
300 GHz fundamentalPLLM. Seo, TSCIMS 2011
220 GHz 180 mWpower amplifier T. Reed, UCSBCSICS 2013
600 GHz IntegratedTransmitterPLL + MixerM. Seo TSC
Integrated 300/350GHz Receivers:LNA/Mixer/VCOM. Seo TSC
81 GHz 470 mWpower amplifier H-C Park UCSBIMS 2014
Not shown: 670 GHz amplifier:J. Hacker, TSCIMS 2013
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Field-Effect Transistors
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State of the Art (IMS 2014)
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HEMTs: Key Device for Low Noise Figure
34
1
)(2
)(21
2
min
f
fRRRg
f
fRRRgF
igsm
igsm
Hand-derived modified Fukui Expression, fits CAD simulation extremely well.
0
2
4
6
8
10
1010 1011 1012
ft=300GHzft=600GHzft=1200GHzft=2400GHz
Noi
se f
igu
re,
dB
frequency, Hz
2:1 to 4:1 increase in ft → greatly improved noise @ 200-670 GHz.
Better range in sub-mm-wave systems; or use smaller power amps.
Critical: Also enables THz systems beyond 820 GHz
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FET Design
gDS WLRR
S/D
contact
gW width gate
gfgsgd WCC ,
)/( gchgm LvCg
)/( vWLR ggDS
)density state /well(2// 2wellwell qTT
WLC
oxox
ggchg
masstransport
1
capacitors threeabove the
between ratiodivision voltage2/1
v
35
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FET Design: Scaling
gDS WLRR
S/D
contact
gW width gate
gfgsgd WCC ,
)/( gchgm LvCg
)/( vWLR ggDS
)density state /well(2// 2wellwell qTT
WLC
oxox
ggchg
masstransport
1
capacitors threeabove the
between ratiodivision voltage2/1
v
36
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FET Design: Scaling
gDS WLRR
S/D
contact
gW width gate
gfgsgd WCC ,
)/( gchgm LvCg
)/( vWLR ggDS
)density state /well(2// 2wellwell qTT
WLC
oxox
ggchg
masstransport
1
capacitors threeabove the
between ratiodivision voltage2/1
v
37
2:1 2:1
constant 2:12:1
2:1 2:1
2:1 2:1 2:1
2:1
constant
constant
2:1 2:1
constant
2:1 2:1
4:1
constant
constant
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FET parameter change
gate length decrease 2:1
current density (mA/mm), gm (mS/mm) increase 2:1
transport effective mass constant
channel 2DEG electron density increase 2:1
gate-channel capacitance density increase 2:1
dielectric equivalent thickness decrease 2:1
channel thickness decrease 2:1
channel density of states increase 2:1
source & drain contact resistivities decrease 4:1
Field-Effect Transistor Scaling Laws
fringing capacitance does not scale → linewidths scale as (1 / bandwidth )
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FET parameter change
gate length decrease 2:1
current density (mA/mm), gm (mS/mm) increase 2:1
transport effective mass constant
channel 2DEG electron density increase 2:1
gate-channel capacitance density increase 2:1
dielectric equivalent thickness decrease 2:1
channel thickness decrease 2:1
channel density of states increase 2:1
source & drain contact resistivities decrease 4:1
Field-Effect Transistors No Longer Scale Properly
39
Gate dielectric can't be much further scaled.Not in CMOS VLSI, not in mm-wave HEMTs
gm/Wg (mS/mm) hard to increase→ Cfringe / gm prevents ft scaling.
Shorter gate lengths degrade electrostatics→ reduced gm /Gds
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Scaling roadmap for InP HEMTs
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Why THz HEMTs no longer scale; how to fix this
HEMTs: gate barrier also lies under S/D contacts → high S/D access resistance S/D regrowth→ no barriers under contacts→ low RS/D→ higher fmax, lower Fmin
As gate length is scaled, gate barrier must be thinned for high gm, low Gds
HEMTs: High gate leakage when gate barrier is thinned→ cannot thin barrier ALD high-K gate dielectrics→ ultra-thin→ improved gm, Gds , increased (ft,fmax)
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Solutions to key HEMT scaling challenges have been developed during the development of III-V MOS for VLSI.
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UCSB's Record VLSI-Optimized MOSFET @ 25nm Lg.
Lee et al, 2014 VLSI Symposium
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UCSB's Record VLSI-Optimized MOSFET @ 25nm Lg.
~2.4 mS/μm Peak gm at VDS=0.5 V ~300 Ohm-µm on-resistance at VGS=0.7 V 77 mV/dec Subthreshold Swing at VDS=0.5 V,
76 mV/V DIBL at 1 µA/µm 0.5 mA/µm Ion at Ioff=100 nA/µm and VDD=0.5 V 61 mV/dec subthreshold swing @1 mm Lg
-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.50.0
0.2
0.4
0.6
0.8
1.0
gm (
mS
/m
)
Cu
rren
t D
ensi
ty (
mA
/m
)
Gate Bias (V)
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8L
g = 25 nm
Ion
= 500 A/m
(at Ioff
=100 nA/m, VDD
=0.5 V)
VDS
= 0.1 to 0.7 V
0.2 V increment
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Cu
rren
t D
ensi
ty (
mA
/m
)Drain Bias (V)
Ron
= 303 Ohm-m
at VGS
= 0.7 V
VGS
= -0.4 V to 0.7 V
0.1 V increment
-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.510-7
10-6
10-5
10-4
10-3
10-2
10-1
100
101
DIBL = 76 mV/V
VT = -85 mV at 1 A/m
SSmin
~ 72 mV/dec. (at VDS
= 0.1 V)
SSmin
~ 77 mV/dec. (at VDS
= 0.5 V)
Lg = 25 nm
VDS = 0.1 to 0.7 V
0.2 V increment
Cu
rre
nt
De
ns
ity
(mA
/m
)
Gate Bias (V)
Lee et al, 2014 VLSI Symposium
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High Transconductance III-V MOSFETs
-0.2 0.0 0.2 0.40.0
0.4
0.8
1.2
1.6
2.0
Gm
(mS
/m)
Curr
ent D
ensi
ty (m
A/
m)
Gate Bias (V)
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2VDS
= 0.1 to 0.7 V
0.2 V increment
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0.00.20.40.60.81.01.21.41.61.82.02.22.4
Curr
ent D
ensi
ty (m
A/
m)
Drain Bias (V)
Ron
= 201 Ohm-m
at VGS
= 1.0 V
VGS
= -0.4 V to 1.0 V
0.2 V increment
High gm, with low GDS, is critical for THz FETs
Here: 18nm gate length, 5nm InAs channel → 3mS/mm gm.
These FETs have large access resistance from non-self-aligned contacts; so gm can be readily increased.
Future: shorter gates, thinner channels, better dielectrics better contacts→ higher gm.
Lee et al, EDL, June 2014
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THz III-V MOS: Not the same as VLSI III-V MOS
UTB Si MOS UTB III-V MOS III-V THz MOS/HEMT
III-V THz HEMT
III-V MOS has a reasonable chance of use in VLSI at the 7nm nodeThese will *not* be THz devices
The real mm-wave / VLSI distinction:Device geometry optimized for high-frequency gain (THz)vs. optimized for small footprint & high DC on/off ratio (VLSI).
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mm-wave / THz devices: minimize overlap capacitances, drain offset for low Cgd & Gds, thicker channels optimized for gm, T-gates for low resistance
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Prospects for Higher-Bandwidth CMOS VLSI
Recall: Gate-dielectric can't scale much further.That stops gm (mS/mm) from increasing.(end capacitance)/gm limits achievable f t .
Also: Given fixed dielectric EOT, Gds degrades with scaling.
FinFETs have better electrostatics, hence better gm/Gds...But in present technologies the end capacitances are worse.
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And W via resistances reduce the gainInac et al, CSICS 2011 (45nm SOI CMOS)
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InP Field-Effect-Transistor Scaling Roadmap
2 THz FETs realized by:
Ultra low resistivity source/drain
High operating current densities
Very thin barriers & dielectrics
Gates scaled to 9 nm junctionshigh-barrier HEMTMOSFET
Impact:Sensitive, low-noise receiversfrom 100-1000 GHz.
3 dB less noise → need 3 dB less transmit power.
or
2-3 THz InP HEMTs are Feasible.
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Conclusions
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Roadmap for High-Frequency Transistors
Beware of physics-free roadmaps20% improvement /year extrapolations are meaningless.Real transistors are approaching scaling limits.VLSI transistors are optimized for density & digital, not RF.Lower standby power processes are slower RF processes.
Bandwidths of Si CMOS VLSI have leveled off.
There is market for application-specific high-frequency transistors.LNAs, PAs, front-ends generally.Just like cell phones today.
InP HBTs & HBTs have perhaps 2-3 scaling generations left.Doubling of bandwidth, perhaps a little more.Process technology development is getting quite hard.
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