III. Multicore Processors (3)
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Transcript of III. Multicore Processors (3)
III. Multicore Processors (3)
Dezső Sima
Spring 2007
(Ver. 2.0) Dezső Sima, 2007
Dual-Core Xeon UP-lines
10.1.3 Dual/quad-core server processors
Dual/Quad-Core Xeon DP-lines
Dual-Core Xeon MP-lines
• Xeon 3000 - line Core 2 Duo 60 nm9/2006
Dual-Core Xeon UP-lines
10.1.3 Dual/quad-core server processors
(Core based, monolithic, dual-core)
Table: Main features of the dual-core Xeon 3000 UP-lineSurces: Intel, Wikipedia
Xeon 3000 line (1)
Series3000
(Conroe)
Dual/Quad-Core DC
Models 3040-3070
Microarchitecture Core
Cores E6300-E6700
Intro. 9/2006
Technology 65 nm
Die size 143 mm2
Nr. of transistors 291 mtrs
fc [GHz] 1.86-2.66
L2 2*4 MB
FSB [MT/s] 1066
TDP [W] 65
Socket FC-LGA6
EM64T
HT
ED
VT
EIST
La Grande
AMT2
10.1.3 Xeon 3000 UP-line (Conroe)
10.1.3 Dual/quad-core server processors
• Xeon DP 2.8 Paxville DP 90 nm10/2005
• Xeon 5000 line Dempsey 65 nm5/2006
Dual/Quad-Core Xeon DP-lines
• Xeon 5100 line Woodcrest 65 nm6/2006
• Xeon 5300 line Clovertown 65 nm11/2006
(Netburst based, multi-chip, two Irwindale cores)
(Netburst based, multi-chip, two Cedar Mill cores)
(Core based, monolithic, dual-core)
(Core based, multi-chip, two Woodcrest chips)
http://www.xbitlabs.com/articles/cpu/display/opteron-xeon-workstation_5.html
Nocona PaxvilleIrwindaleNocona
(L2 enlarged to 2MB) (2 x Irwindale cores)
6/200410/2004
90 nm112 mm2
125 mtrs
Xeon DP 2.8 – 3.4Xeon DP 2.8J - 3.4J
mPGA 604
2/20059/2005
90 nm135 mm2
169 mtrs
Xeon DP 2.8 – 3.6Xeon DP 3.8
mPGA 604
10/200511/2005
90 nm2 x 135 mm2
2 x 169 mtrs
Xeon DP 2.8Xeon MP 7020-7041
mPGA 604
Figure: Genealogy of the Xeon Paxville core
(DP enhanced Prescott) (DP enhanced Prescott 2M)
http://www.theinquirer.net/default.aspx?article=16879http://www.gamepc.com/labs/view_content.asp?id=x36o252&page=2
Sources:
Intel’s first 64-bit Xeon
In contrast: correspondingdesktop processors have the LGA 775 socket.
10.1.3 Xeon DP 2.8 (Paxville DP) (1)
Heat Sink Die
FC-mPGA4 package
Pin side capacitorsPackage pin
Die size capacitors
Figure: Packaging of the Paxville processor
The FC-mPGA package interfaces with the motherboard via an mPGA604 socket
Source: - „Dual-Core Intel Xeon Processor 2.80 GHz Datasheet,” Oct. 2005, http://download.intel.com/design/Xeon/datashts/30915801.pdf
10.1.3 Xeon DP 2.8 (Paxville DP) (2)
Source: Douglas J., „Intel 8xx series and Paxville Xeon-MP Microprocessors,” http://www.hotchips.org/archives/hc17/3_Tue/HC17.S8/HC17.S8T1.pdf
Figure Connecting the two Irwindale cores in the large Paxville Package (?)
10.1.3 Xeon DP 2.8 (Paxville DP) (3)
Source: Conolly C., „Intel Paxville Dual Core Xeon and the ASsus PVL-D Intel 7520,” Oct. 2005, http://www.gamepc.com/labs/view_content.asp?id=paxville&page=1
Figure: Packaging of the Paxville(two Irwindale dies are mounted on a carrier and the carrier is packaged as a 604 package”
10.1.3 Xeon DP 2.8 (Paxville DP) (4)
Table: Dual-Core Xeon DP-lines (1)
10.1.3 Xeon DP 2.8 (Paxville DP) (5)
Sources: Intel, Wikipedia
PGA 604
135
800
2*2 MB
2.8
2*169 mtrs
2*135 mm2
90 nm
10/2005
2*Irwindale dies
Netburst
Xeon DP 2.8
DC
(Paxville DP)
AMT2
La Grande
EIST
VT
ED
HT
EM64T
Socket
TDP [W]
FSB [MT/s]
L2
fc [GHz]
Nr. of transistors
Die size
Technology
Intro.
Cores
Microarchitecture
Models
Dual/Quad-Core
Series
Figure: Block diagram of the Dempsey (Cedar Mill-based)
Source: Inkley B. and Tetrick S., „Intel Multi-core Architecture and implementations,” IDF, March 2006, http://download.intel.com/pressroom/kits/press/core2/Multicore%20MATS002%20999%20pct.pdf
10.1.3 Xeon 5000 DP-line (Dempsey) (1)
http://www.tecchannel.de/_misc/img/detail1000.cfm?pk=342850&fk=432919&id=il-74145482909021379
Figure: Packaging of the Dempsey
10.1.3 Xeon 5000 DP-line (Dempsey) (2)
Source: Brookwood N., The Role of intellignet Desing i the Evolution of Multi-Core Processors,” Febr. 2006.http://www.insight64.com/downloads/IntelligentDesign.pdf
Figure: The Xeon DP Dempsy with the two FSB capable Blackford chipset
10.1.3 Xeon 5000 DP-line (Dempsey) (3)
Table: Dual-Core Xeon DP-lines (2)
LGA 771
95/130
667/1066
2*2 MB
2.6-3.73
2*188 mtrs
2*81 mm2
65 nm
5/2006
2*Cedar Mill dies
Netburst
5030-5080
DC
5000(Dempsey)
PGA 604
135
800
2*2 MB
2.8
2*169 mtrs
2*135 mm2
90 nm
10/2005
2*Irwindale dies
Netburst
Xeon DP 2.8
DC
(Paxville DP)
AMT2
La Grande
EIST
VT
ED
HT
EM64T
Socket
TDP [W]
FSB [MT/s]
L2
fc [GHz]
Nr. of transistors
Die size
Technology
Intro.
Cores
Microarchitekture
Models
Dual/Quad-Core
Series
Sources: Intel, Wikipedia
10.1.3 Xeon 5000 DP-line (Dempsey) (4)
Figure: Block diagram of the Merom, Conroe and Woodcrest processors
Source: Inkley B. and Tetrick S., „Intel Multi-core Architecture and implementations,” IDF, March 2006, http://download.intel.com/pressroom/kits/press/core2/Multicore%20MATS002%20999%20pct.pdf
10.1.2 Xeon 5100 DP-line (Woodcrest) (1)
Figure: Die shot of the Woodcrest (5100 series) processor (L2: 4 MB)
Source: http://www.intelstartyourengines.com/images/Woodcrest%20Die%20Shot%202.jpg
Woodcrest
10.1.3 Xeon 5100 DP-line (Woodcrest) (2)
Sources: Kubicki K., „Intel 2006 Mobile CPU Roadmap Update,” Mai 2006, http://www.dailytech.com/Article.aspx?newsid=2546
Conroe Merom
Hübner, T., „Intel Core 2 Duo E6700 und E6600,” July 2006, http://www.computerbase.de/artikel/hardware/prozessoren/2006/test_intel_core_2_duo_e6700_e6600/1/
Figure: Contrasting the die shots of Merom, Conroe and Woodcrest
Woodcrest
http://www.intelstartyourengines.com/images/Woodcrest%20Die%20Shot%202.jpg
10.1.3 Xeon 5100 DP-line (Woodcrest) (3)
Table: Dual-Core Xeon DP-lines (3)
LGA 771
95/130
667/1066
2*2 MB
2.6-3.73
2*188 mtrs
2*81 mm2
65 nm
5/2006
2*Cedar dies
Netburst
5030-5080
DC
5000(Dempsey)
PGA 604
135
800
2*2 MB
2.8
2*169 mtrs
2*135 mm2
90 nm
10/2005
2*Irwindale dies
Netburst
Xeon DP 2.8
DC
(Paxville DP)
AMT2
La Grande
(5140 or above)EIST
VT
ED
HT
EM64T
LGA 771Socket
65/80TDP [W]
1066/1333FSB [MT/s]
4 MBL2
1.6-3.0fc [GHz]
291 mtrsNr. of transistors
143 mm2Die size
65 nmTechnology
6/2006Intro.
Single diesCores
CoreMicroarchitekture
5110-5160Models
DCDual/Quad-Core
5100(Woodcrest)
Series
sources: Intel, Wikipedia
10.1.3 Xeon 5100 DP-line (Woodcrest) (4)
Figure: The Xeon 5300 series (Clovertown) dies are built up of two dual core Woodcrest
Source: Li W. and Babayan B., „Extracting The Most Out Of Intel’s Multi-Core Platforms with Software,” http://idfemea.intel.com/moscow/download/keynotes_and_tis/Li_Babayan_en.pdf
10.1.3 Xeon 5300 DP-line (Clovertown) (1)
Source: Wasson S., „Intel’s Woodcrest procdessor previewed,” May 2006, http://techreport.com/etc/2006q2/woodcrest/index.x?pg=2
Figure: Packaging the Clowertown
10.1.3 Xeon 5300 DP-line (Clovertown) (2)
Table: Dual-Core Xeon DP-lines (4)
Sources: Intel, Wikipedia
LGA 771
95/130
667/1066
2*2 MB
2.6-3.73
2*188 mtrs
2*81 mm2
65 nm
5/2006
2*Cedar dies
Netburst
5030-5080
DC
5000(Dempsey)
PGA 604
135
800
2*2 MB
2.8
2*169 mtrs
2*135 mm2
90 nm
10/2005
2*Irwindale dies
Netburst
Xeon DP 2.8
DC
(Paxville DP)
AMT2
La Grande
(5140 or above)EIST
VT
ED
HT
EM64T
LGA 771LGA 771Socket
80/12065/80TDP [W]
1066/13331066/1333FSB [MT/s]
2*4 MB4 MBL2
1.6-2.661.6-3.0fc [GHz]
2*291 mtrs291 mtrsNr. of transistors
2*143 mm2143 mm2Die size
65 nm65 nmTechnology
11/20066/2006Intro.
2*Woodcrest diesSingle diesCores
CoreCoreMicroarchitekture
E5310-5345/X53555110-5160Models
QCDCDual/Quad-Core
5300(Clovertown)
5100(Woodcrest)
Series
10.1.3 Xeon 5300 DP-line (Clovertown) (3)
10.1.3 Dual/quad-core server processors
• Xeon 7000 line Paxville MP 90 nm11/2005
• Xeon 7100 line Tulsa 65 nm8/2006
Dual-Core Xeon MP-lines
(Netburst based, multi-chip, two Irwindale dies)
(Netburst based, monolithic, Cedar Mill based)
Table: Dual-Core Xeon MP-lines (1)
1 Concerning the L2 cache size, there is a contradiction in Intel’s documentation; whereas according to the datasheets models of the 7000 series include 1 or 2 MB L2 caches the comparison charts for all models 1 MB large L2 caches.
Sources: Intel, Wikipedia
Xeon 7000 line (Paxville MP) (1)10.1.3 Xeon 7000 MP-line (Paxville MP) (1)
AMT2
La Grande
EIST
VT
ED
HT
EM64T
PGA604Socket
95/150TDP [W]
667/800FSB [MT/s]
L3
2*1/2 MB 1L2
2.66-3.0fc [GHz]
2*169 mtrsNr. of transistors
2*135 mm2Die size
90 nmTechnology
11/2005Intro.
2*Irwindale diesCores
NetburstMicroarchitecture
7020-7041Models
DCDual/Quad-Core
7000(Paxville MP)
Series
Figure: Block diagram and die shot of Tulsa
Source: Rusu S., „Circuit Technologies for Multi-Core Processor Design,” April 2006, http://www.ewh.ieee.org/r6/scv/ssc/April06.pdf
10.1.3 Xeon 7100 MP-line (Tulsa) (1)
Figure: Detailed block diagram of Tulsa (Cedar Mill-based)
Source: Inkley B. and Tetrick S., „Intel Multi-core Architecture and implementations,” IDF, March 2006, http://download.intel.com/pressroom/kits/press/core2/Multicore%20MATS002%20999%20pct.pdf
10.1.3 Xeon 7100 MP-line (Tulsa) (2)
Figure: Die shot of Tulsa (L3: 16 M)
Source: Vance A., „Intel completes Operation Catch up with Tulsa release,” The Register, Aug. 2006, http://www.theregister.co.uk/2006/08/29/intel_tulsa_out/
10.1.3 Xeon 7100 MP-line (Tulsa) (3)
(81 mm2)
(435 mm2)
Cedar Mill
Tulsa
2 x 1 MB L” + 16 MB L32 x 2 MB L2
Vance A., „Intel completes Operation Catch up with Tulsa release,” The Register, Aug. 2006, http://www.theregister.co.uk/2006/08/29/intel_tulsa_out/
Sources: Huynh T., „Pressler: Intel Extreme Edition 955,” Dec. 2005, http://www.sudhian.com/index.php?/articles/show/pressler_intel_extreme_edition_955_prescotts_last_hurrah/,
Figure: Contrasting the Cedar Mill and Tulsa die shots
10.1.3 Xeon 7100 MP-line (Tulsa) (4)
Table: Dual-Core Xeon MP-lines (2)
1 Concerning the L2 cache size, there is a contradiction in Intel’s dokumentation; whereas according to the datasheets models of the 7000 series include 1 or 2 MB L2 caches the comparison charts for all models 1 MB large L2 caches.
AMT2
La Grande
EIST
VT
ED
HT
EM64T
PGA604PGA604Socket
95/15095/150TDP [W]
667/800667/800FSB [MT/s]
4/8/16 MBL3
2*1 MB 2*1/2 MB 1L2
2.5-3.52.66-3.0fc [GHz]
1328 mtrs2*169 mtrsNr. of transistors
435 mm22*135 mm2Die size
65 nm90 nmTechnology
8/200611/2005Intro.
Cedar Mill-based single die2*Irwindale diesCores
NetburstNetburstMicroarchitekture
7110M-7140M / 7110N-7150N7020-7041Models
DCDCDual/Quad-Core
7100(Tulsa)
7000(Paxville MP)
Series
Sources: Intel, Wikipedia
10.1.3 Xeon 7100 MP-line (Tulsa) (5)
Category Code Name Cores Cache Market
Desktop KentsfieldDual core multi-die
4 MB Mid 2007
Desktop ConroeDual core single die
4 MB shared End 2006
Desktop AllendaleDual core single die
2 MB shared End 2006
Desktop Cedar Mill (NetBurst/P4) Single core 512 kB, 1 MB, 2 MB Early 2006
Desktop Presler (NetBurst/P4) Dual core, dual die 4 MB Early 2006
Desktop/Mobile Millville Single core 1 MB Early 2007
Mobile Yonah2 Dual core, single die 2 MB Early 2006
Mobile Yonah1 Single core 1/2 MB Mid 2006
Mobile Stealey Single core 512 kB Mid 2007
Mobile Merom Dual core, single die 2/4 MB shared End 2006
Enterprise Sossaman Dual core, single die 2 MB Early 2006
Enterprise Woodcrest Dual core, single die 4 MB Mid 2006
Enterprise Clovertown Quad core, multi-die 4 MB Mid 2007
Enterprise Dempsey (NetBurst/Xeon) Dual core, dual die 4 MB Mid 2006
Enterprise TulsaDual core single die
4/8/16 MB End 2006
Enterprise WhitefieldQuad core single die
8 MB, 16 MB shared Early 2008
Figure 5.7: Future 65 nm processors (Overview)Source: P. Schmid: Top Secret Intel Processor Plans Uncovered
www.tomshardware.com/2005/12/04/top_secret_intel_processor_plans_uncovered
10.1.3 Guessed road map of Intel processors (1)
Codename Cores Cache Market
Desktop Wolfdale Dual core, single die 3 MB shared 2008
Desktop RidgefieldDual core single die
6 MB shared 2008
Desktop Yorkfield8 cores multi-die
12 MB shared 2008+
Desktop Bloomfield Quad core, single die - 2008+
Desktop/Mobile
Perryville Single core 2 MB 2008
Mobile PenrynDual core single die
3 MB, 6 MB shared 2008
Mobile Silverthorne - - 2008+
Enterprise Hapertown8 cores multi-die
12 MB shared 2008
Figure 5.8: Future 45 nm processors (overview)
Source: P. Schmid: Top Secret Intel Processor Plans Uncovered www.tomshardware.com/2005/12/04/top_secret_intel_processor_plans_uncovered
10.1.3 Guessed road map of Intel processors (1)
Source: Thrax, „ Core 2 Duo and the future of Intel,” Nov. 2006, http://www.short-media.com/review.php?r=343
Figure: Roadmap of Intel’s lines
10.1 Published road map of Intel processors
• Dual-core Itanium 2 Montecito 90 nm7/2006
• Quad-core Itanium 2 Tukwila 65 nm2008
Dual/quad-core Itanium 2 lines
10.1.4 Dual/quad-core Itanium processors
(Itanium 2 based, monolithic)
(Itanium 2 based, monolithic)
Figure: Block diagram and basic floor plan of the Montecito
Source: Rusu S., „Circuit Technologies for Multi-Core Processor Design,” April 2005, http://www.ewh.ieee.org/r6/scv/ssc/April06.pdf
10.1.4 Dual-core Itanium 2 (Montecito) (1)
10.1.4 Dual-core Itanium 2 (Montecito) (2)
Source: McNairy C. and Soltis D. „ Itanium 2 Processor Microarchitecture,” IEEE Micro, March-April 2003, pp. 44-55
Figure: Block diagram of the Itanium 2 processor
10.1.4 Dual-core Itanium 2 (Montecito) (3)
McNairy C. and Bhatia R., „Montecito,” IEEE Micro, March-April 2005, pp. 10-20
Figure: Block diagram of the Montecito
10.1.4 Dual-core Itanium 2 (Montecito) (4)
Figure: New features of Montecito
Source: Intel
Source: Naffziger S. et al., „The Implementation of a 2-core Multi-Threaded Itanium-Family Processor,” Proc. ISSCC, 2005, pp. 182-183, 592
Figure: Floor plan of Montecito
Core
10.1.4 Dual-core Itanium 2 (Montecito) (5)
Madison (130 nm) Montecito (90 nm)
L2: 256 KB, L3: 9 MB L2I: 1 MB, L2D: 256 KB, L3: 12 MB
(Inthe figure reduced to 90 nm)
Figure: Contrasting Itanium 2 Madison and Montecito (at the same feature size)Source: Krewell K., „Best Servers of 2004,” Microprocessor Report, Jan. 2005, http://h10018.www1.hp.com/wwsolutions/misc/docs/2004_Server_Processor_of_Year.pdf
Naffziger S. et al., „The Implementation of a 2-cre Multi-Threaded Itanium-Family Processor,” Proc. ISSCC, 2005, pp. 182-183, 592
10.1.4 Dual-core Itanium 2 (Montecito) (6)
Source: DeMone P., Sizing Up the Super hevyweights,” Real World Technologies, Sept. 2004, http://h21007.www2.hp.com/dspp/files/unprotected/Itanium/sizingsuperheavys.pdf
Figure: Contrasting die sizes and floor plans of Itanium processors
10.1.4 Dual-core Itanium 2 (Montecito) (7)
Table: Main features of the dual-core Itanium 2 line
10.1.4 Dual-core Itanium 2 (Montecito) (8)
Sources: Intel, Wikipedia
104
533
2*4 MB
1.6
9030
1 MB I$ + 256 KB D$ per coreL2
Dual-Core Itanium 2(Montecito)
Series
75
2*3 MB
1.6
9010
104
400
2*6 MB
1.40
9015
DBS
(Silvervale)
PAC 611
104
533
2*6 MB
1.42
1720 mtrs
596 mm2
90 nm
7/2006
9020
104
533
2*9 MB
1.6
9040
EIST
Cache safe
VT
ED
HT
64-bit
Socket
104TDP [W]
533FSB (16 B wide) [MT/s]
f HT
2*12 MBL3
1.6fc [GHz]
Nr. of transistors
Die size
Technology
Introduced
Stepping
9050Models
Figure: Expected features of the quad-core Tukwila
10.1.5 Quad-core Itanium 2 (Tukwila) (1)
Source: Intel
Figure: Preliminary die shot of Tukwila
Source: Hoyler G., „Intel Itanium Architecture Roadmap and Technology Update,” 2004, http://www.decus.de/sig/vms/TUD_2004/INTEL.PDF
10.1.5 Quad-core Itanium 2 (Tukwila) (2)
10.1 Literature (1)
x86 multicore processors
Shimpi A. L. and Wilson D., Intel Pentium 4 6xx and 3.73EE,” Febr. 2005, http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2353&p=3
Smith, S.L. and Valentine, B.:”Intel Core Microarchitecture,” March 2006, http://download.intel.com/pressroom/kits/press/core2/ NGMA%20IDF%20Press%20Mar%208%20PDF%20Set.pdf
Douglas J., „Intel 8xx series and Paxville Xeon-MP Microprocessors,” http://www.hotchips.org/archives/hc17/3_Tue/HC17.S8/HC17.S8T1.pdf
Brookwood N., The Role of intellignet Desing in the Evolution of Multi-Core Processors,” Febr. 2006. http://www.insight64.com/downloads/IntelligentDesign.pdf
Li W. and Babayan B., „Extracting The Most Out Of Intel’s Multi-Core Platforms with Software,” http://idfemea.intel.com/moscow/download/keynotes_and_tis/Li_Babayan_en.pdf
Bhandarkar D. „Energy Efficient Performance: The Next Frontier,” Oct. 2006, http://download.intel.com/technology/eep/fall_microprocessor_forum_2006.pdf
Rusu S., „Circuit Technologies for Multi-Core Processor Design,” April 2006, http://www.ewh.ieee.org/r6/scv/ssc/April06.pdf
- Related Intel Datasheets, http://www.intel.com/design
- Wikipedia
10.1 Literature (2)
Montecito
Rusu S., „Circuit Technologies for Multi-Core Processor Design,” April 2006, http://www.ewh.ieee.org/r6/scv/ssc/April06.pdf
Naffziger S. et al., „The Implementation of a 2-core Multi-Threaded Itanium-Family Processor,” Proc. ISSCC, 2005, pp. 182-183,
DeMone P., Sizing Up the Super hevyweights,” Real World Technologies, Sept. 2004, http://h21007.www2.hp.com/dspp/files/unprotected/Itanium/sizingsuperheavys.pdf
Hoyler G., „Intel Itanium Architecture Roadmap and Technology Update,” 2004, http://www.decus.de/sig/vms/TUD_2004/INTEL.PDF
McNairy C. and Soltis D. „ Itanium 2 Processor Microarchitecture,” IEEE Micro, March-April 2003, pp. 44-55
Naffziger S. et al., The Implementation of a 2-Core, Multi-threaded Itanium Family Processor, IEEE Journal Solid-State Circuits, Vol. 41, No. 1, Jan. 2006, pp. 197-209
- „Inside the Intel Itanium 2 Processor,” Technical White Paper, July 2002, HP Corp.
- Related Intel Datasheets, http://www.intel.com/design/itanium2/documentation.htm
McNairy C. and Bhatia R., „Montecito: A Dual-Core, Dual-Thread Itanium Processor,” IEEE Micro, March-April 2005, pp. 10-20