II11 Zero - ziyang.eecs.umich.edu

Advanced Digital Logic Design – EECS 303

http://ziyang.eecs.northwestern.edu/eecs303/

Teacher: Robert DickOffice: L477 TechEmail: [email protected]: 847–467–2298

Implementation technologiesHomework

Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS

5:32 decoder/demultiplexer

5 :32Decoder

Subs ys tem

\EN

S4 S3 S2 S1 S0

.

.

..

\Y31

\Y0

2Y2

1Y1

1Y0

1Y3

1Y2

2Y1

2Y0

2Y3

1G

1B

1A

139

2G

2B

2A

S4

S3

G1

G2A

G2B

CC

BB

AA

Y7

Y6

Y5

Y4

Y1

Y0

Y3

Y2

138

G1

G2A

G2B

CC

BB

AA

Y7

Y6

Y5

Y4

Y1

Y0

Y3

Y2

138

G1

G2A

G2B

CC

BB

AA

Y7

Y6

Y5

Y4

Y1

Y0

Y3

Y2

138

G1

G2A

G2B

CC

BB

AA

Y7

Y6

Y5

Y4

Y1

Y0

Y3

Y2

138

\EN

S2

S1

S0

S2

S1

S0

S2

S1

S0

S2

S1

S0

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

\Y

\Y

4 Robert Dick Advanced Digital Logic Design



5:32 decoder/demultiplexer implementation details

Why is G1 connected to an inverted active-low enable signal?

Why are 2A, 2B, and 2G not connected on the 74139 part?

What would happen if this design were used and the parts wereTTL (I don’t expect you to know this one already)?

How about CMOS?




Tally circuit example

Given n-input circuit

Count number of 1s in input

I1 Zero One

0 1 01 0 1





I1 Zero One

0 1 01 0 1

Can implement using logic gates

One

Zero





I1 Zero One

0 1 01 0 1

Can implement using TGs

"0"

Zero

II11

One"0"

"1"





I1 Zero One

0 1 01 0 1

Can implement using TGs

Zero

One

"0"

"0"

"1"

II11




TG tally circuit

"0"

Zero

II11

One"0"

"1"

"0"

Zero

II11

One"0"

"1"

"0"

Zero

II11

One"0"

"1"

"0"

Zero

II11

One"0"

"1"




TG tally circuit

Zero

One

"0"

"0"

"1"

II11

Zero

One

"0"

"0"

"1"

II11

Zero

One

"0"

"0"

"1"

II11

Zero

One

"0"

"0"

"1"

II11




4-input tally

I1 I2 Zero One Two0 0 1 0 00 1 0 1 01 0 0 1 01 1 0 0 1




4-input tally

I1 I2 Zero One Two0 0 1 0 00 1 0 1 01 0 0 1 01 1 0 0 1

"0"

Zero

II11

One"0"

"1"

"0"

Zero

One

II22

"0" Two




4-input tally

I1 I2 Zero One Two0 0 1 0 00 1 0 1 01 0 0 1 01 1 0 0 1

Zero

One

"0"

"0"

"1"

II11

Zero

One

"0"

II22

Two"0"




TG tally circuit

"0"

Zero

II11

One"0"

"1"

"0"

Zero

One

II22

"0" Two

"0"

Zero

II11

One"0"

"1"

"0"

Zero

One

II22

"0" Two

"0"

Zero

II11

One"0"

"1"

"0"

Zero

One

II22

"0" Two

"0"

Zero

II11

One"0"

"1"

"0"

Zero

One

II22

"0" Two

"0"

Zero

II11

One"0"

"1"

"0"

Zero

One

II22

"0" Two

"0"

Zero

II11

One"0"

"1"

"0"

Zero

One

II22

"0" Two

"0"

Zero

II11

One"0"

"1"

"0"

Zero

One

II22

"0" Two

"0"

Zero

II11

One"0"

"1"

"0"

Zero

One

II22

"0" Two

"0"

Zero

II11

One"0"

"1"

"0"

Zero

One

II22

"0" Two

"0"

Zero

II11

One"0"

"1"

"0"

Zero

One

II22

"0" Two

"0"

Zero

II11

One"0"

"1"

"0"

Zero

One

II22

"0" Two

"0"

Zero

II11

One"0"

"1"

"0"

Zero

One

II22

"0" Two




TG tally circuit

Zero

One

"0"

"0"

"1"

II11

Zero

One

"0"

II22

Two"0"

Zero

One

"0"

"0"

"1"

II11

Zero

One

"0"

II22

Two"0"

Zero

One

"0"

"0"

"1"

II11

Zero

One

"0"

II22

Two"0"

Zero

One

"0"

"0"

"1"

II11

Zero

One

"0"

II22

Two"0"

Zero

One

"0"

"0"

"1"

II11

Zero

One

"0"

II22

Two"0"

Zero

One

"0"

"0"

"1"

II11

Zero

One

"0"

II22

Two"0"

Zero

One

"0"

"0"

"1"

II11

Zero

One

"0"

II22

Two"0"

Zero

One

"0"

"0"

"1"

II11

Zero

One

"0"

II22

Two"0"

Zero

One

"0"

"0"

"1"

II11

Zero

One

"0"

II22

Two"0"

Zero

One

"0"

"0"

"1"

II11

Zero

One

"0"

II22

Two"0"

Zero

One

"0"

"0"

"1"

II11

Zero

One

"0"

II22

Two"0"

Zero

One

"0"

"0"

"1"

II11

Zero

One

"0"

II22

Two"0"




ROMs, FPGAs, and multi-level minimization

Programmable read-only memories (PROMs)

Field-programmable gate arrays (FPGAs)

Programmable devices for prototyping





2-D array of binary values

Input: Address

Output: Word




PROM

Dec

00 n− 1

Address

2 −1n

00

+5V +5V +5V +5V

Word Line 0011

Word Line 1010

Bit Lines

jj

ii




Implementing logic with PROMs

F0 = A B C + A B C + A B C

F1 = A B C + A B C + A B C

F2 = A B C + A B C + A B C

F3 = A B C + A B C + A B C




Truth table

A B C F3 F2 F1 F0

0 0 0 0 1 0 00 0 1 0 1 1 10 1 0 0 0 1 00 1 1 1 0 0 01 0 0 1 1 0 11 0 1 0 0 0 11 1 0 1 0 0 01 1 1 0 0 1 0

Address Word




PROM suitable for implementing example

8 words x4 bits

addresses

outputs




Memory composition

2764 EPROM

8K x 8

2764

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

O0

O1

O2

O3

O4

O5

O6

O7

OE

CS

PGM

VPP

A10

A11

A12

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

O0

O1

O2

O3

O4

O5

O6

O7

OE

CS

PGM

VPP

A10

A11

A12




Memory composition

++++

2764

A0A1

A2A3A4

A5A6A7A8

A9

O0

O1O2O3

O4O5O6

O7

OE

CS

P GM

VP P

A10A11A12

2764

A0A1

A2A3A4

A5A6A7A8A9

O0

O1O2O3O4O5O6

O7

OE

CS

P GM

VP P

A10A11A12

2764

A0A1

A2A3

A4A5A6A7

A8A9

O0O1O2O3O4O5O6O7

OECS

P GM

VP P

A10A11A12

2764

A0A1

A2A3A4

A5A6A7

A8

A9

O0O1O2O3

O4O5O6

O7

OECS

P GM

VP P

A10A11

A12

++ ++

A13

/OE

A12:A0

D7:D0D15:D8

U3 U2

U1 U0

++++

2764

A0A1

A2A3A4

A5A6A7A8

A9

O0

O1O2O3

O4O5O6

O7

OE

CS

P GM

VP P

A10A11A12

2764

A0A1

A2A3A4

A5A6A7A8A9

O0

O1O2O3O4O5O6

O7

OE

CS

P GM

VP P

A10A11A12

2764

A0A1

A2A3

A4A5A6A7

A8A9

O0O1O2O3O4O5O6O7

OECS

P GM

VP P

A10A11A12

2764

A0A1

A2A3A4

A5A6A7

A8

A9

O0O1O2O3

O4O5O6

O7

OECS

P GM

VP P

A10A11

A12

++ ++

A13

/OE

A12:A0

D7:D0D15:D8

U3 U2

U1 U0

16K x 16Chip select




PLA/PAL vs. PROM

PLA

Takes advantage of don’t-cares

Good at random logic

Good when product terms shared

PAL

More area-efficient for certain designs

OR-plane can’t be programmed, usually no sharing




PLA/PAL vs. PROM

PROM

Design trivial

Can’t take advantage of don’t-cares

Area-inefficient

Product/sum terms not shared




Field-programmable gate arrays (FPGAs)

PLAs

10–100 gate equivalent

FPGAs

AlteraActelXilinx100–1,000,000 gate equivalent




Altera EPLDs

Each has from 8–48 macrocells

Macrocell behavior controlled with EPROM bits

Can be used sequentially

Has synchronous and asynchronous modes




Altera erasable programmable logic devices (EPLDs)

Composed of many macrocells – 8 product term AND/OR array withprogrammable MUXs

C lk

MUX

Output

MUXQQ

F/B

MUX

Invert

Contro l

AND

ARRAY

pad

Programmab le po larity

I/O P in

Seq. Log ic

B lock

Programmab le feedback




Multiple array matrix (MAX)

Altera macrocells quite limited

Can’t share product terms between macrocells

Workaround: Connect together macrocells with programmableinterconnect




Multiple array matrix (MAX)

Array

8 Fixed Inputs

52 I/O P ins

8 LABs

16 Macroce lls /LAB

32 Expanders /LAB

EPM5128:

LAB A LAB H

LAB B LAB G

LAB C LAB F

LAB D LAB E

P

I

AA

Log ic

Array

B locks

(s im ilar to

macroce lls )

Globa l Routing :

Programmab le

Interconnect




MAX expander terms

Macroce ll

ARRAYI/O

Block

Expander

Product

Term

ARRAY

I

NN

PP

UU

TT

SS

P

I

AA

I/O Pad

I/O Pad




MAX expander terms

Macroce ll

P− Term s

Expander

P− Term s

Expander product terms shared among all macrocells




Altera 22V10 PAL

00AS YNCHRONOUS RE S E T

(TO ALL RE GIS TE RS )

23AR

88132176220264308352396

44

22

22

OUTP UT

LOGIC

MACROCE LL

P − 5810R − 5811

528572616660704748792836

484

880

440

21

33

OUTP UT

LOGICMACROCE LL

P − 5812

R − 5813

10561100114411881232127613201364

1012

1408

924

968

1452

20

44

OUTP UT

LOGICMACROCE LL

P − 5814R − 5815

16721716176018041848189219361980

1628

2024

1496

1584

2068

1540

2112

19

55

OUTP UT

LOGICMACROCE LL

P − 5816R − 5817

23762420246425082552259626402684

2332

2728

2156

2288

2772

22442200

28162860

11

11

00

00

11

00

00

11

DD QQ

QQS P

1100

5808

PP

RR

5809

1100 44 88 12 16 20 24 28 32 36 40

INCREMENT

FIRSTFUSENUMBERS

15

99

OUTP UT

LOGICMACROCE L

LL

P − 5824R − 5825

49725016506051045148519252365280

4928

5324

4884

17

77

OUTP UTLOGIC

MACROCE LLL

P − 5820R − 5821

38283872391639604004404840924136

3784

4180

3652

3740

4224

3696

4268

16

88

OUTP UTLOGIC

MACROCE LLL

P − 5822R − 5823

44444488453245764620466447084752

4400

4796

4312

4356

4840

18

66

OUTP UTLOGIC

MACROCE LLL

P − 5818R − 5819

31243168321232563300334433883432

3080

3476

2904

3036

3520

29922948

35643608

14

10

OUTP UTLOGIC

MACROCE LLL

P − 5826R − 5827

54125456550055445588563256765720

5368

11

5764

13

S YNCHRONOUSP RE S E T

00 44 88 12 16 20 24 28 32 36 40INCREMENTT




Altera 22V10 PAL

Many product terms per output

Latches and MUXs associated with outputs

22 IO pins

10 may be used as outputs




Actel programmable gate arrays

Rows of programmable logic blocks

Rows of interconnect

Columns of interconnect

Attach to rows using antifuses





Each combinational logic block has 8 inputs, 1 output

No built-in sequential elements

Build flip-flops using logic blocks




Actel logic block

2:1 MUX

D0

D1

S OA

2:1 MUX

D2

D3

S OB

2:1 MUX

S 0

YY

S 1

Modified 4:1 MUX




Actel logic block

2:1 MUX

"0"

RR

2:1 MUX

"1"

SS

2:1 MUX QQ

"0"

Cross-couple for sequential use





IO buffers, programming & test logic

IO buffers, programming & test logic

IO b

uf.

, p

rog

. &

test

log

ic

IO b

uf.

, p

rog

. &

test

log

icLogic modules

Wiring tracks




Actel interconnect

Log ic Module

Horizontal

Track

Vertical

Track

Anti− fuse




Antifuse routing

Build long routing lines from short segments




Actel routing example

Log ic Modu le

Log ic Modu leLog ic Modu le

Output

Input

Input

Minimize number of antifuse hops for critical path

2-3 hops for most interconnections




Xilinx logic cell arrays (LCAs)

CMOS static RAM

Run-time programmable

Serial shift-register based programming

Program on power-up (external PROM)




Xilinx LCA components

Configurable logic blocks (CLBs)

IO blocks (IOBs)

Wiring channels




Xilinx LCAs

IOB IOB IOB IOB

CLB CLB

CLB CLB

IOB

IO

BIO

BIO

B

W iring Channe ls




Xilinx LCA features

Inputs

Input variables

Tri-state (high-Z) enable bit for output

Output clocks




Xilinx LCA features

Output the input bit

Contains internal flip-flops for inputs and outputs

Fast and slow outputs available, e.g., 5 ns vs. 30 ns

Slower option limits slew rateLower noiseLower power consumption




Xilinx LCA

DD QQ

OUT

INV

TS

INV

OUTPUT

S OURCE

S LEW

RATE

PAS S IVE

PULLUP

MUX

RR

DDQQ

RR

Vcc

PAD

Output

Buffer

TTL or CMOS

Input Buffer

Globa l ResetClocks

Enable

Output

Out

Direct In

Reg is tered In

Program Contro lled Options




Xilinx CLB

2 flip-flops

General function of 4 variables

2 non-general functions of 5 variables

Certain special-case functions of 6 variables

Global reset

Clock

Clock enable

Independent input, DIN




Xilinx CLB

Com b inationa l

Func tion

Generator

DD RD

QQ

CEMux

DD RD

QQCE

Mux

Mux

Mux

Mux

A

B

C

D

EE

Q1

Q2

Res e t

DIN

Clock

Clock

Enab le

FF

GG

XX

YY




Function generator

Function

of 5

Variables

FF

GG

Mux

Mux

AA

BB

CC

DD

EE

Q1

Q2Two constrained functions of five variables




Function generator

Func tion

o f 4

Variab les

FF

Mux

Mux

AA

BB

CC

DD

EE

Q1

Q2

Mux

Func tion

o f 4

Variab les

GG

Mux

Mux

AA

BB

CC

DD

EE

Q1

Q2

Mux

Two arbitrary functions of four variables




Function generator

Func tion

o f 4

Variab lesEE

Mux

Mux

AA

BB

CC

DD

Q1

Q2

Func tion

o f 4

Variab les

Mux

Mux

AA

BB

CC

DD

Q1

Q2

Mux

FF

GG

Certain limited functions of 6 variables




PARITY5 CLB cost example

Determine whether the number of 1s is even or odd

F = A � B � C � D � E

Implement using 1 CLB




2-bit comparator CLB cost example

A B = C D or A B > C D

GT = A C + A B D + B C D

EQ = A B C D + A B C D + A B C D + A B C D

Only 1 CLB required




Majority CLB cost example

High whenever ⌈n/2⌉ outputs are high

CLB

5− input Majority Circuit

CLB

CLB

CLB

7− input Majority Circuit




Large parity CLB cost example

2 levels allow up to 25 inputs

CLB

CLB

9 Input Parity Log ic




4-bit adder CLB cost example

Full adder, 4 CLB delays to final carry out (CO), 4 CLBs

CLB

A0 B0 Cin

S 0

CLB

A1 B1

S 1

CLB

A2 B2

C1S 2

CLB

A3 B3

C2S 3 C0Cout




4-bit adder CLB cost example

Composition from 2 2-bit adders give 2 CLB delay, 6 CLB cost

S 0

S 1

C2

A1 B1 CinA0 B0

CLBS 2

S 3

Cout

A3 B3 A2 B2

CLB




Xilinx interconnect

Short direct connections

Global long lines

Horizontal/vertical long lines

Switching matrix connections




Xilinx interconnect

Hierarchical routing organization

Some designs are constrained by routing resources

Can use logic CLBs to control routing

Substantial communication power consumption




Xilinx interconnect

Interconnect

Direct Connections

Globa l Long Line

Horizonta l/Vertica l

Long Lines

Sw itch ing Matrix

Connections

XX

YY

CLB3

AA

DD

DI

BBCC

KK

EE RR

CE

XX

YY

CLB1

AA

DD

DI

BBCC

KK

EE RR

CEXX

YY

CLB0

AA

DD

DI

BBCC

KK

EE RR

CE

Direc t

Connec tions

Horizonta l

Long Line

Vertica l

Long LinesGloba l

Long Line

Switch ing

Matrix

Horizonta l

Long Line

XX

YY

CLB2

AA

DD

DI

BBCC

KK

EE RR

CE




Example Xilinx parts

Parameter XC4024 XC3195 XC2018

Number of FFs 2,560 1,320 174Number of IOs 256 176 74Number of logic inputs per CLB 9 5 4Function generators per CLB 3 2 2Fast carry logic yes no noNumber of logic outputs per CLB 4 2 2RAM bits 32,768 0 0




Dynamic reconfiguration

Serial configuration slow

Parallelize

Full reconfiguration slow

Partial reconfiguration

Reconfiguration slow

Use configuration cache




FPGA application examples

Prototyping

Constant coefficient multiplication

Direct HW implementation of problem instance, e.g.,

3SATDesign rule checking (DRC)




Prototype designs

Discrete packages

SlowError-prone

Custom layout requires circuit fabrication

SlowExpensive for small runsCan’t be changed




Programmable devices in prototyping

Multiplexers (MUXs) and demultiplexers (DMUXs)

Wiring them up is tedious and error-prone

Programmable array logic (PAL) and programmable logic array(PLA)

Fuses blown, write-once

Generic array logic (GAL)

Electrically reprogrammable






Inefficient for implementing random logicWrite-once

Erasable programmable read-only memories (EPROMs)

Can be erasedErasure slow (UV)Expensive package window





Electrically erasable programmable read-only memories(EEPROMs)

Erasure fastPackaging less expensivePotential for in-circuit erasure

Field-programmable gate arrays (FPGAs) are ideal

If market size small, ship FPGAs

In-circuit programming practical




DeMorgan’s Law for CMOS

(A + B) = A B

(AB) = A + B

A + B = A B

AB = A + B




DeMorgan’s Law for CMOS

OR is the same as NAND with complemented inputs

AND is the same as NOR with complemented inputs

NAND is the same as OR with complemented inputs

NOR is the same as AND with complemented inputs




DeMorgan’s Law for OR/NAND

A A B B A + B (A B ) A + B (AB)

0 1 0 1 0 0 1 10 1 1 0 1 1 1 11 0 0 1 1 1 1 11 0 1 0 1 1 0 0




DeMorgan’s Law for AND/NOR

A A B B A B (A + B ) A B (A + B)

0 1 0 1 0 0 1 10 1 1 0 0 0 0 01 0 0 1 0 0 0 01 0 1 0 1 1 0 0




AND/OR → NAND/NOR

A

B

C

D




AND/OR → NAND/NOR

A

B

C

D

A

B

C

D

AND

AND

OR




AND/OR → NAND/NOR

A

B

C

D

AND

AND

OR

A

B

C

D

NAND

NAND

NAND




AND/OR → NAND/NOR

A

B

C

D

NAND

NAND

NAND

A

B

C

D

NAND

NAND

NAND




AND/OR/NOT network to NAND/NOR

=

=

=

=



Homework

Review for midterm exam on Thursday

Will post solutions to homework tonight

Responsible for all reading, assignments, labs



Review

Two-level transformations and minimization

Multi-level minimization

Design with various implementation technologies


II11 Zero - ziyang.eecs.umich.edu

Documents

Transcript of II11 Zero - ziyang.eecs.umich.edu