IeMRC Flagship Project: Power Electronics · 5/22/06 CONFIDENTIAL What is Driving Future Power...
Transcript of IeMRC Flagship Project: Power Electronics · 5/22/06 CONFIDENTIAL What is Driving Future Power...
5/22/06 CONFIDENTIAL
IeMRCIeMRC Flagship Project: Flagship Project: Power Electronics Power Electronics
5/22/06 CONFIDENTIAL
What is Driving Future Power Electronics?What is Driving Future Power Electronics?
• Power electronics holds the key to annual energysavings of around $400 billion!
• Lightweight, high performance products such asmobile computing, home entertainment and powertools
• High efficiency, high power density electric drives inproducts such as air conditioning
• Proliferation of automotive and aerospace electronicsystems
• Increased use of power electronics in transmissionand distribution systems
• Energy storage systems• Pulsed power
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Common ThemesCommon Themes• Increased power densities• Lower electromagnetic
emissions• Plug-and-go systems• Extreme operating
environments• Higher levels of integration• Lower cost
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0.4kV, 0.08kA
1kV, 0.15kA
2.5kV, 0.5kA12kV, 1.5kA
2.5kV, 1.5kA
4kV, 3kA
8kV, 4kA
0.6kV, 0.2kA
2.5kV, 0.6kA
4.5kV, 3kA
6kV, 6kA
1kV, 25A
0.5kV, 0.2kA
1kV, 0.3kA
1.2kV, 0.6kA
1.7kV, 1.2kA
3.3kV, 1.2kA
6.5kV 0.9kA
4.5kV, 2.1kA
4.5kV, 4kA
6kV, 6kA
0.01
0.1
1
10
100
1960 1970 1980 1990 2000
Year
Sw
itc
he
d P
ow
er
(MV
A)
ETT
LTT
GTO
IGBT
IEGT
GCT
Power Semiconductor DevicesPower Semiconductor Devices
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Power Electronic PackagingPower Electronic Packaging• Physical containment for one or more basic
component building blocks e.g. semiconductor dies,capacitors, inductors, resistors
• Protection from environment e.g. ingress of liquids,dust etc.
• Circuit interconnections (internal and external)• Electromagnetic management – EMC issues• Thermal Management
Semiconductor dies
Passive components
Power Module
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Power Electronic PackagesPower Electronic Packages
4.5kV, 2.1kAIEGT
Powerthyristor
30V, 50AMOSFET
600V, 30AMOSFET
600V, 200AHalf-bridgeIGBTmodule
Lighttriggeredthyristor
1200V, 200Amodule foraircraft flightsurface actuation
Integratedpowermodule
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Why Manufacture Power Electronics in UK?Why Manufacture Power Electronics in UK?
• UK based technology and manufacturing capability iscurrently relatively strong
• UK is internationally competitive across the wholesupply chain
• Many systems are application specific, highlycustomised and tend to have a relatively high addedvalue
• Suited to a technologically advanced manufacturingbase and can absorb the relatively high UK labourcosts
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Power Electronic Performance LimitationsPower Electronic Performance Limitations
• Semiconductor devices– Silicon max. power device die temperatures from 125°C
to 200°C– Silicon Carbide, Gallium Nitride and Diamond > 300°C
• Passive devices– Capacitors
• Packaging– Thermal cycling– Power density– Environmental
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HeatsinkThermal GreaseCopper baseplate
Anatomy of Typical Package and Anatomy of Typical Package and HeatsinkHeatsink
SolderDirect bonded copperCeramicDirect bonded copper
Lead-out interconnect
SolderDieBond wire
EncapsulationHousing
Thermal stack has 9 layers, 8 interfaces!
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IeMRCIeMRC Flagship Project in Power Electronics Flagship Project in Power Electronics
Aim:
To enhance the competitiveness of the UK powerelectronics industry through improvements to thedesign and manufacturing capability for high powerdensity systems and in particular those intended forhigh reliability applications and challengingenvironments.
Programme started 1st July 2005Duration 42 monthsTotal IeMRC funding £811 k, 5 Academic partners
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ObjectivesObjectives1. Establish and maintain a roadmap for power
electronics modules and associated thermalmanagement systems.
2. Maintain a “technology watch” on emergingtechnologies for power electronic modules andassociated thermal management systems.
3. Develop an enhanced physics of failure approach tothe design and qualification of power electronicmodules.
4. Establish the feasibility of a range of advanced powerelectronic module manufacturing technologies andapply selected technologies in a manufacturingenvironment.
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Academic PartnersAcademic Partners
power electronics,module design andfailure analysis
point analysis tools,physics-of-failure reliabilitypredictions, multi-physicsmodelling and numericaloptimisation
partial dischargeeffects
high-permittivitydielectrics and SiliconCarbide devicefabrication
heat transferand thermalmanagement
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Industrial PartnersIndustrial Partners• Dynex Semiconductor• Goodrich• International Rectifier• Morgan Technical Ceramics• QinetiQ• Raytheon Systems• Rohm and Haas• Rolls-Royce• SELEX• Semelab• SR-Drives• TRW Automotive
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Work PackagesWork Packages
• WP0 – Management
• WP1 – Road mapping
• WP2 – Technology watch
• WP3 – Reliability and physics of failure
• WP4 – Advanced packaging
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Management StructureManagement Structure
Shef. PI
Project SteeringCommittee
Team 1
WP 3
Team 2
Team 3
WP2 WP4Team 4WP1
WP1: Cyril Buttay
Team 1: Mark Johnson
Team 2: Ian Cotton
Team 3: David Newcombe
Team 4: Mark Johnson
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Work-Package and Team CompositionWork-Package and Team CompositionWP1 (Road-Mapping)• Sheffield, Loughborough
Team leaders: Cyril Buttay, Paul PalmerWP3 (Reliability)• Team 1 (substrate-level reliability): Sheffield, Greenwich, Dynex,
Semelab, GoodrichTeam leader: Mark Johnson
• Team 2 (partial discharge): Manchester, Greenwich, Dynex, Rolls-RoyceTeam leader: Ian Cotton
• Team 3 (whole module): Sheffield, Greenwich, Manchester, Dynex,Semelab, GoodrichTeam leader: David Newcombe
WP2/4 (Advanced Packaging)• Team 4 (technology watch/advanced packaging): Sheffield,
Greenwich, Oxford, Newcastle, Dynex, Semelab, Goodrich, Rolls-RoyceTeam leader: Mark Johnson
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WP1 Road MappingWP1 Road Mapping
• Two events held:– workshop during November 2005– on-line follow-up event in January
• Data captured in a database using a spreadsheet-based form
• Results from the workshop (keywords, issues andmetrics) circulated to delegates and discussed at theon-line workshop in January
• Consensus that more application focussed eventsneeded
• Future event on power electronics for the moreelectric aircraft is planned for May 2006
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Drivers, Metrics and KeywordsDrivers, Metrics and Keywords
Power Electronic System, Power Electronic Converter
Hardware Software
Active
Components
Sensor/ control
Topology
Cost/kVA
Power density (kVA/m 3,
kVA/kg)
Top-Down Drivers
Customer requirements
Application requirements
Societal demands
Standards
Legislation
Global economics
Obsolescence
Cost/unit
Cost/ kVA
Lifetime
Environment
On-state loss
Off-state loss
Switching loss
Thermal
performance
Cost/unit
Lifetime
Environment
Losses
Accuracy
Cost/function
Passive
Components
Lifetime (years, cycles)
Environment (thermal,
vibration radiation)
Efficiency
Bottom-Up Drivers
Materials technologies
Assembly technologies
New concepts
Standards
Legislation ( RoHS etc.)
Global economics
Obsolescence
Cost/unit
Cost/ µF, µH etc.
Lifetime
Environment
Losses
Functionality
Integrity
Security
GUI
Power Electronic System, Power Electronic Converter
Hardware Software
Active
Components
Sensor/ control
Topology
Cost/kVA
Power density (kVA/m 3,
kVA/kg)
Top-Down Drivers
Customer requirements
Application requirements
Societal demands
Standards
Legislation
Global economics
Obsolescence
Cost/unit
Cost/ kVA
Lifetime
Environment
On-state loss
Off-state loss
Switching loss
Thermal
performance
Cost/unit
Lifetime
Environment
Losses
Accuracy
Cost/function
Passive
Components
Lifetime (years, cycles)
Environment (thermal,
vibration radiation)
Efficiency
Bottom-Up Drivers
Materials technologies
Assembly technologies
New concepts
Standards
Legislation ( RoHS etc.)
Global economics
Obsolescence
Cost/unit
Cost/ µF, µH etc.
Lifetime
Environment
Losses
Functionality
Integrity
Security
GUI
Metrics
Each metric (e.g. cost/unit) will be
influenced by a combination of
quantifiable factors: e.g. materials used,
assembly technology, device design,
thermal management technology etc.
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WP3 Summary of ActivitiesWP3 Summary of Activities
• A series of initial reliability tests were agreed toestablish the capability of the current state-of-the-art.
• Coupons were acquired for thermal cycling testing ofthe substrate tiles
• Experimental work commenced at Sheffield inOctober 2005. An interim report has been producedand further tests are ongoing
• Greenwich has undertaken a number of thermalcycling simulations to help identify suitable testprocedures that will be used to gather failureinformation for particular mechanisms.
• Greenwich has also reviewed the CENELEC and IECstandards on semiconductor power modules
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Summary of ActivitiesSummary of Activities
• Manchester is working to describe problems relatingto partial discharge in power electronic modules
• Provide techniques for minimising its likelihood• Provide a physics of failure model• Modelling of modules has been carried out in FEA
simulation software
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Thermal Cycling LimitationsThermal Cycling Limitations
Copper baseplateSolderDirect bonded copperCeramicDirect bonded copperSolderDieBond wire
Flexing of bond wirescauses fatigue failure(de-bonding) at heel
CTE mismatchcauses fatigue failureat interfaces
Repeated heating and cooling of assembly leads torepetitive mechanical stress and eventual failure
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Substrate Wear-OutSubstrate Wear-Out
• DBC substrates are composed of a ceramicinsulator e.g. Al2O3 (aluminum oxide) or AlN(aluminum nitride) onto which pure copper metal isattached
• The different expansion coefficients of copper andceramic lead to mechanical stresses in the ceramic
• Cracks originate at the copper/ceramic interface,propagating at an angle of 45 0
• As the crack reaches about one third of the waythrough the ceramic, the crack direction turnsparallel to the substrate surface resulting inconchoidal fracture
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Fatigue failure: Conchoidal fractureFatigue failure: Conchoidal fracture%conchoidal fracture vs temperature cycles
0
10
20
30
40
50
60
70
80
90
100
temperature cycles
% fr
actu
re Front of tile
Back of tile
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Failure rate of tiles due to temp cyclingFailure rate of tiles due to temp cycling
nu
mb
er
of
cy
cle
s t
o f
ail
ure
1 2 3 4 5 6 7 8 9
substrate tiles
-60 to 150 C
-10 to 200 C
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Ultrasonic Wire Bonding MechanismUltrasonic Wire Bonding Mechanism
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Failure: Crack at the Bonding InterfaceFailure: Crack at the Bonding Interface
Substrate (Si)
AlWire
Substrate (Si)
Heating processinduces
compressive Stress
Cooling processinduces
tensile StressCrackpropagation
Substrate (Si)coated with Al
AlWire
Coefficient of thermalexpansion: αAl ≈ 12x αSi
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Wire Bond DegradationWire Bond Degradation
• Degradation of bond begins immediately• Crack propagates in the bond wire close to the weld• After 3000 cycles virtually all bond wires have lifted
100 cycles -55 to+125 deg C
1500 cycles
3000 cycles
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Wire Bond LifeWire Bond Life
• Number of cycles tofailure can berepresented by Coffin-Mason law
• K ~ 6.5• Rapid degradation in
performance with ΔT
0.1
1.0
10.0
100.0
1000.0
10000.0
10 100 1000
delta T (K)T
ho
usan
ds o
f C
ycle
s
K
T
T
N
N!
""#
$%%&
'
(
(=
1
2
1
2
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Multi-Physics Modelling at GreenwichMulti-Physics Modelling at Greenwich
CFD, FEA, Optimisation…
Manufacturing Testing Field
Failure Mechanisms, Reliability
Temperature Stress
MODELLING TO HELP ESTABLISH DESIGN RULES
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Project ManagementProject Management
• Greenwich Team– Chris Bailey– Hua Lu– Tim Tilford
IeMRC
POWER ELECTRONICSFLAGSHIP PROJECT
DTI
MODELLING POWERMODULES (MPM)
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IeMRCIeMRC - Reliability - Reliability
Accelerated Life Testing
InterconnectFatigue, etc
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Solder InterconnectSolder Interconnect
Chip 330 microns
Solder 100 microns
Cu 0.3 mm
Alumina 1 mm
Cu 0.3 mm
13.5 mm
Symmetryplane
• thermal load profiles
• design parameters:
• geometry, material properties
Predict effects of:
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Thermal CyclesThermal Cycles
• 4 temperature cycles are investigated• Each cycle consists of 15 min ramps and dwells at both low
and high temperature extremes.
-60
-10
40
90
140
190
0 10 20 30 40 50 60
time(minutes)
T(d
egre
e C
)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
150140-104
150110-403
180155-252
180125-551
dTTmaxTminCycle
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Model Dimension and MaterialsModel Dimension and Materials
Alumina
Cu
CuSilicon
Solder330µm100µm300µm
1mm
300µm
Thickness 6.75mm
Symmetry plane
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Results: Results: Sn3.8Ag0.7Cu(SAC)Sn3.8Ag0.7Cu(SAC)
crack
Plastic work dW distribution at the end of a thermal cycle
1778.0941655.0811374.1931315.789Nf*
0.2960.3180.3830.4Max(dW)/Mpa
CYC4CYC3CYC1CYC1
*Nf is actually the life time of an element with a length of 73 microns.The lifetime of the whole solder joint is much greater.
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Life-time Prediction (Life-time Prediction (SnPbSnPb))
Number of cycles to crack initiation and crack propagationrate
* L10000 is the crack length after 10000 cycles.
0.8150.081196150140-10
1.0110.101162150110-40
1.1050.111150180155-25
1.3460.135126180125-55
SnPbSnAgSnPbSnAgSnPbSnAgdTTmaxTmin
L10000(mm)*dl/dN (µm/cycle)N0Cycles
1. For SnPb, FEA results can be correlated to crack initiationtime and crack propagation time
2. For SAC solder this is not available.3. No lifetime model for SnAg at the moment.
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Residual Stress in Substrate TilesResidual Stress in Substrate Tiles
• Simple models have been used to calculate the stressdistribution in tiles
• The effects of the following parameters on the stressdistribution in a round tile have been investigated:– gap width– radius– ceramic thickness– margin
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Tile with Patterned CopperTile with Patterned Copper
Sym
met
ry p
lane
CuAlN
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Von Von MisesMises Stress Distribution Stress DistributionS
ymm
etry
pla
ne
Sym
met
ry p
lane
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Partial Discharge PhenomenaPartial Discharge Phenomena
• Research student appointed October 2005• Two day visit to Dynex for student to experience
manufacturing techniques / design issues• Literature review completed• FEA Modelling of in-use versus test conditions• Experimental activity commenced
– Investigation of acoustic monitoring– Testing of specific materials
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Key Literature Review FindingsKey Literature Review Findings
• For substrates:– Voids within substrates typically dominant failure
mechanism– DC breakdown strength of ALN typically double that of
DC– Breakdown strengths appear to be non-linear– No significant temperature effect noted
• For gels:– Gels also strongly degraded by PD but evidence of self-
healing exists– Large influence of humidity on strength of gels– Inverse relationship of temperature with strength of gels
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FEA ModellingFEA Modelling
• Electrostatic modelling of a module has been carriedout for conditions where the module is under test andin-use
• When tested in production, all HV terminals bondedto each other and raised in voltage while baseplate isearthed
• In use, voltage differences exist between HV terminals• Does the production test actually stress all
components of the module?
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Comparison of Test and In-Service E-FieldsComparison of Test and In-Service E-Fields
Substrate in test Substrate in use
Gel in test Gel in use
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WP2/4 (Team 4)WP2/4 (Team 4)
• A meeting of Team 4 was held on 17th October 2005to define the future activities of WP2/4. A range ofactivities were discussed and the following wereidentified for further action:– Baseplate materials: survey of alternatives– Baseplate-less designs: utilising direct cooling of the
substrate tile– Substrate tiles: survey of alternatives– Interconnect: evaluation of alternative techniques such
as soldered Cu strip and TLP-bonded Ag foil– Cooling technologies: survey of heat-lane coolers
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Summary of ActivitiesSummary of Activities
• A survey of base-plate and substrate materials hascommenced under the “technology watch” theme
• Oxford has performed an extensive review of heatlane literature to furnish understanding of thispotentially promising cooling technology– A simple demonstration unit has been designed and is
undergoing trials.• Newcastle has initiated work on using deposition
techniques for forming substrate-level high-k baseddecoupling capacitors
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Closed Loop Pulsating Heat PipesClosed Loop Pulsating Heat Pipes
• Constant volume system• Filled with working fluid at saturation
(boiling) conditions• Serpentine arrangement of channels or
pipes• Hot and Cold side; evaporator and
condenser
• Boiling of water at the evaporator and bubble formation• Condensing of water at the cold end and bubble collapse• Heat stored in latent heat, transferred by oscillations and
condensation• Push and pull of fluid leads to oscillations• Instabilities cause circulations
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Closed Loop Pulsating Heat PipesClosed Loop Pulsating Heat Pipes
• Improved design built and tested• Narrower channels, 2mm => 1.6mm• More loops, 12 => 24• Non-moving part valves incorporated
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Closed Loop Pulsating Heat PipesClosed Loop Pulsating Heat Pipes
• Non-moving part valves encourage fluid circulation• A number of valve designs were tested using air flow
through a stereolith model in ABS plastic.• Teslar non-moving part valve design chosen.
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Closed Loop Pulsating Heat PipesClosed Loop Pulsating Heat Pipes
• Testing• Successful operation in vertical orientation• Difficultly maintaining oscillations when the device is horizontal
Droplets of waterfeed the evaporator
Pulsating channels
Vapour and boilingwater droplets
Pulsating channels migratefrom left to the right
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Closed Loop Pulsating Heat PipesClosed Loop Pulsating Heat Pipes
• Thermal resistance decreases as heat input is increased• An effective conductivity for the device of 4990W/mK• Twelve times higher than silver
Vertical Wet - 100mm PHP
Thermal Resistance vs Heat Transferred
y = 28.13x-0.8292
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
0.00 50.00 100.00 150.00 200.00
Heat Transferred (Watts)
Th
erm
al R
esis
tan
ce (
K/W
)
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Integrated Capacitor TechnologyIntegrated Capacitor Technology
• The capacitor is deposited in a series of layers on a DBC (orsimilar ceramic) substrate.
• A multi-layer structure offers higher capacitance (energy storage)per unit volume.
• Area: 60 mm x 20 mm.• Total height: around 600 microns.• Voltage rating: 1000 V• Leakage current less than 1 mA / mm2 at 200°C and 1000 V
High-k dielectric
Metal (e.g. Au/Al)
DBC copper layer
DBC ceramic layer
~500-
600 mµ
~200-
300 mµ
~500-
600 mµ
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Initial Results for a Initial Results for a SiCSiC-based structure-based structure
• Fabricated on 5x1015cm-3 n-type Cree wafers• Thermally oxidised layer (25nm)• 50nm Ti layer deposited and oxidised at 800oC to give
75 nm TiO2 layer• Palladium gate (50nm thick) deposited• Tested in air in a light-tight box on a hotplate
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CapacitanceCapacitance
100 200 300 400 500
Temperature (oC)
50
70
90
110
130
150
170
190
210
230
250
Capacitance (
pF
)
1kHz
10kHz
100kHz
1MHz
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Power Electronics Flagship SummaryPower Electronics Flagship Summary
• All academic partners now “up to speed” with staff inplace
• Technical work packages underway– Road mapping– Reliability and physics of failure– Advanced packaging
• Initial progress is promising• Need to maximise gearing through other initiatives
e.g. DTI technology programme• Additional industrial partners are welcome to join
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Summary of Current and Potential Future LinksSummary of Current and Potential Future Links
Packagingtechnologyqualification
Design forqualification
Advancedpackaging
IeMRC
DTI-fundedresearch intoimproved bondingtechnology(IMPECT)
EPSRC-fundedresearch in SiC(ASCENT)
DTI-fundedprogrammes inpowerelectronics (5th
Call)
EPSRC-fundedresearch inpower moduletechnology
EPPICFaraday
DTI/RDAfunded activities(TBA)
Powerelectronicsroadmap
AerospaceInnovation andGrowth Team:AIN, TVP
Foresight Vehicle
DTI-fundedresearch intomodelling of powermodules (MPM)
5/22/06 CONFIDENTIAL
Web Site, Further InformationWeb Site, Further Information
• http://eeepro.shef.ac.uk/iemrc• Public section has information on the project, its work
packages, dissemination of key results etc.• Project partner forum will be used to keep minutes of
meetings, project reports etc.