IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 9, SEPTEMBER 2017 3639

A Study on Practically UnlimitedEndurance of STT-MRAM

Jimmy J. Kan, Chando Park, Chi Ching, Jaesoo Ahn, Yuan Xie, Fellow, IEEE,Mahendra Pakala, and Seung H. Kang

Abstract— Magnetic tunnel junctions integrated for spin-transfer torque magnetoresistive random-access memoryare by far the only known solid-state memory element thatcan realize a combination of fast read/write speed and highendurance. This paper presents a comprehensive validationof high endurance of deeply scaled perpendicular mag-netic tunnel junctions (pMTJs) in light of various poten-tial spin-transfer torque magnetoresistive random-accessmemory (STT-MRAM) use cases. A statistical study is con-ducted on the time-dependent dielectric breakdown (TDDB)properties and the dependence of the pMTJ lifetime onvoltage, polarity, pulsewidth, duty cycle, and tempera-ture. The experimental results coupled with TDDB modelsproject >1015 write cycles. Furthermore, this work reportssystem-level workload characterizations to understand thepractical endurance requirements for realistic memoryapplications.The results suggest that the cyclingenduranceof STT-MRAM is “practically unlimited,” which exceedsthe requirements of various memory use cases, includinghigh-performance applications such as CPU level-2 andlevel-3 caches.

Index Terms— Cache memory, practically unlimitedendurance, spin-transfer torque magnetoresistive random-access memory (STT-MRAM), time-dependent dielectricbreakdown (TDDB), unified memory.

I. INTRODUCTION

THE growing demand in the computing community fora memory that can be both fast and nonvolatile has

led researchers to investigate a slew of new technologies.Amongst several nonvolatile memory (NVM) candidates thatare emerging, spin-transfer torque magnetoresistive random-access memory (STT-MRAM) is considered attractively posi-tioned for unified memory and cache memory applications dueto its high speed and superior cycling endurance [1]. In partic-ular, the endurance is often conveniently cited as “unlimited”

Manuscript received May 1, 2017; revised June 17, 2017; acceptedJuly 18, 2017. Date of current version August 21, 2017. The review ofthis paper was arranged by Editor Y.-H. Shih. (Corresponding author:Seung H. Kang.)

J. J. Kan, C. Park, and S. H. Kang are with Qualcomm Technolo-gies, Inc., San Diego, CA 92121 USA (e-mail: jkan@qti.qualcomm.com;chandop@qti.qualcomm.com; seungk@qti.qualcomm.com).

C. Ching, J. Ahn, and M. Pakala are with Applied Materials, Inc.,Sunnyvale, CA 94085 USA (e-mail: mahendra_pakala@amat.com).

Y. Xie is with the Department of Electrical and Computer Engineering,University of California at Santa Barbara, Santa Barbara, CA 93111 USA(e-mail: yuanxie@ece.ucsb.edu).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2017.2731959

Fig. 1. 1-Mbit array in packaged perpendicular STT-MRAM chipsubjected to continuous cycling for 2.5 months with no failures(write 0 → read → write1 → read in each cycle). This indicatesthat it will take >1 year of continuous cycling to test the endurance upto 1010 cycles, practically unfeasible to run testing beyond this range.

in terms of lifetime or cycle count [2]–[5], similar to thecase of static random-access memory (SRAM) or dynamicrandom-access memory. However, the term “unlimited” isneither precise nor provable. In essence, no memory canachieve truly unlimited endurance due to factors such asbias temperature instability or time-dependent dielectric break-down (TDDB) [6]. Furthermore, it is not feasible to test mem-ory arrays to such commonly referred lifetimes as 1015 or 1016

cycles within a realistic time frame. For example, shownin Fig. 1 is a packaged 1-Mbit perpendicular STT-MRAMchip which was subjected to consecutive write cycles for2.5 months. In this duration, this chip was able to reach only1.7 × 109 write cycles (without any endurance failure). Thisimplies that, to reach 1016 cycle as an unlimited endurancecriterion, over a million years of continuous testing would berequired. The testing time will increase further if the memorydensity is larger or the write speed is slower. Taking thesefactors into consideration, it becomes more appropriate todescribe an endurance lifetime or a cycle count that equatesto “practically unlimited endurance.”

Provided that STT-MRAM is to fulfill its predicted roleas a robust and customizable memory technology aimed atdisrupting the conventional memory hierarchy, the oxide tun-nel barrier reliability of scaled perpendicular magnetic tunnel

0018-9383 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

3640 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 9, SEPTEMBER 2017

Fig. 2. (a) Representative current versus voltage of pMTJ and transistor. (b) TEM image of the pMTJ and bias polarity definitions.

junction (pMTJ) devices needs to be thoroughly understoodand validated. Though extensive studies have been conductedon the intricacies of oxide breakdown in transistors, theymay not be applicable for the failure kinetics of the MgObarrier because pMTJs are designed to transmit a high-densityspin-polarized current to enable switching while the gateoxide is designed to produce low leakage current, as shownin Fig. 2(a). In pMTJs, consequently, breakdown behaviorsdepend not only on the voltage or electric field stress, but alsoon the magnetotransport and self-heating (SH) effects whichare absent in typical dielectric barriers.

In our recent work [7], we reported an experimental study ofthe influences of STT-MRAM functional parameters such aswrite voltage, polarity, pulsewidth, duty cycle, and temperatureon the TDDB properties of advanced pMTJs of various sizes.In this paper, we expand the study by examining the details ofthe results; in particular, in light of the system-level workloadsimulation results that can help understand the essence andimplication of practically unlimited endurance. To the best ofour knowledge, this paper is the first of its kind linking com-prehensive experimental results to the endurance requirementsof practical STT-MRAM use cases.

The contribution of this paper includes the following:1) we demonstrate that a large write voltage window (>1 V) isobtainable through MgO barrier engineering and that the bar-rier reliability drastically improves through pMTJ size scalingand 2) we present the results of workload characterizationsand write traffic calculations that establish the criteria forpractically unlimited endurance in broad use cases rangingfrom unified embedded NVM to high-performance cache.In combination, these results confirm that STT-MRAM withhigh-quality pMTJs can exceed the endurance requirements ofa variety of applications, including level-2 and level-3 cachesbuilt on sub-10-nm FinFET process technologies.

II. DEVICES FABRICATION AND CHARACTERIZATION

Co-/Pt-based pMTJ stacks with dual free layer MgO inter-faces [Fig. 2(b)] were deposited on 300-mm wafers by anApplied Materials Endura sputtering system. The resistance-area product (RA) of these films was 10 �·μm2. 1-Gbit arraysof devices with diameters of 70–25 and 200–130 nm pitchwere fabricated. Details of these arrays and characterization oftheir temperature-dependent properties have been described inour prior work [8]–[9]. Further optimizations of materials and

processes have enabled 45-nm diameter pMTJs with highercoercivity (median Hc = 3500 and 2000 Oe at 25 and 125 °C,respectively) and thermal stability parameter (median � = 133at 25 °C) [7].

In order to accurately assess the intrinsic reliability ofthe pMTJ devices, it is necessary to fabricate statisticallyvalid groups of devices that are free from extrinsic barrierdefects or etching damage. Such extrinsic factors can causethe broadening of TDDB lifetime dispersions or the emergenceof bimodal distributions that may lead to misinterpretation ofthe reliability physics. For this work, the parallel (P) stateresistance, tunneling magnetoresistance (TMR), and size vari-ations in the arrays are well controlled, with σRp/μRp = 7.5%,σTMR/μTMR = 5.5%, and σCD = 1.7 nm [7].

TDDB measurements under constant voltage stress (CVS)and pulsed voltage stress were carried out to study the MgObarrier endurance. Constant-stress studies, which do not relyon any underlying assumption of appropriate TDDB accelera-tion models (E, 1/E, and V), were chosen over ramp-to-failureinvestigations. These models were evaluated through fittingand will be described in the following section. Voltage stress isprovided directly to the pMTJs through ground-signal-groundRF probes. In all magnetotransport and voltage stress testsdescribed in this paper, the positive polarity direction is definedas an electron transport from the free layer into the referencelayer [P → antiparallel (AP) switching], accordingly, resultingin oxide breakdown in the AP state [shown in Fig. 2(b)].

III. RESULTS AND DISCUSSION

A. Constant Voltage Stress

The variation in breakdown times of a group of pMTJs canbe described by a well-known Weibull distribution

F(tbd) = 1 − exp(−tbd/t63

)β(1)

where β represents the dispersion parameter (Weibull slope)and t63 is the characteristic time to breakdown at the failurepercentage of 63.2%. The cumulative failure probability canbe visualized in Weibull plots of the time to breakdown (tbd)

Wdef= ln[− ln (1 − F(tbd)] (2)

where β is represented by the straight line slope of Wversus ln(tbd) [10]. The Weibull plots that depict the pMTJ

KAN et al.: STUDY ON PRACTICALLY UNLIMITED ENDURANCE OF STT-MRAM 3641

Fig. 3. Weibull plots of integrated breakdown time for different processes.Improved breakdown voltage and higher β achieved through processoptimization (75–480 samples for each plot) [7].

TDDB distributions for varying processes are shown in Fig. 3.Each breakdown distribution contains at least 75–480 samplesrandomly selected from 1-Gbit arrays, allowing for an accurateextraction of t63 and β. In all distributions described, β wasbetween 1 and 1.4 except for poorly controlled process condi-tions. This indicates a low prevalence of premature or extrinsicfailures leading to a relatively tight dispersion, especiallyconsidering that the dielectric thickness is only ∼1 nm.

Assuring that process-related extrinsic defects do notdegrade β is of great significance because the reliable life (TR)at a specified population fraction (R)

TR(R) = t63[− ln (R)]1/β (3)

is strongly affected by β. For example, when considering thetime to failure for the worst 1 ppm, a mild reduction in β from1 → 0.75 results in a 100× decrease in the reliable life. In ourpMTJs, substantial reliability improvements were achieved bybarrier deposition and etching process optimization. As shownin Fig. 3, a relatively constant t63 could be maintained forhigher stress voltages while β increased by a factor of ∼3 from0.37 to 1.10.

B. Pulsewidth and Duty-Cycle Effects

The presence of fast oxide-trap generation and detrappingeffects can lead to drastically different failure times dependingon the pulsewidth and duty cycle of the voltage stress [11].Given that one of the likely writing scenarios for STT-MRAMis fast pulsed operation with relatively low duty cycle, CVSTDDB characterization may underestimate the lifetime.

The integrated time to breakdown (Npulses × ton) for 200 nsto 20 ms pulses using the voltage stress at 1.13 V is com-pared to CVS in Fig. 4(a) (Weibull distributions shown for200 ns, 20 ms, and CVS). A slight increase in t63 appearsonly for pulses shorter than 500 ns, and all longer pulsesdemonstrate an equivalence of integrated time to breakdownand CVS [Fig. 4(a) inset]. Regardless of the pulsing condi-tions, the Weibull plots of the breakdown distributions arenearly overlapping each other. By comparing all distributionsusing a matrix of two-sample Kolmogorov–Smirnov tests fordistribution equivalence, no statistically significant difference

Fig. 4. (a) Weibull plots of integrated breakdown time for pulsed stressand CVS. (Inset) t63 versus pulse widths. (b) Weibull plots of integratedbreakdown time for various duty cycles (%). (Inset) t63 versus dutycycle [7].

Fig. 5. (a) Ramped breakdown distributions showing the polarity depen-dence, with (+) possessing a higher Vbd than (−). (Inset) representativeresistance versus voltage plot. (b) Weibull plots with positive, negative,and bipolar bias voltage (1.15 V CVS).

Fig. 6. Voltage window (Vbd, 50 ns − Vc, 50 ns) distributions.

is found between 200 ns and 20 ms pulses and CVS (typicalP values >0.2).

The same procedure was implemented for comparing theimpact of voltage stress duty cycle on the time to failure.Pulses with Vstress = 1.18 V were applied with duty cyclesbetween 1% and 90% (defined as dc = ton/[ton + toff ])until devices failed due to a hard breakdown. All WeibullTDDB distributions were again found to be overlapped asshown in Fig. 4(b), and no statistically significant differenceswere observed between 1% and 90% (typical P values >0.5).

3642 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 9, SEPTEMBER 2017

Fig. 7. (a) Weibull TDDB plots of pMTJ breakdown between 25 °C and 125 °C with 1.05-V CVS. (b) Temperature versus time from 3-D thermalsimulation at 25 °C showing a rapid heating within 25 ns of bias application. (Inset) cross section view of pMTJ simulation.

Fig. 8. (a) t63 for (+) and (−) polarity fit by E and 1/E breakdown models. (b) t63 and t1 ppm fit and extrapolated to operating conditions, indicatingan endurance of more than 1015 cycles [7].

Combined, the equivalence of assorted pulse widths and dutycycles suggest a progressive wear-out mechanism withoutstrong contributions from fast detrapping effects over thepulsewidth and duty cycle ranges examined.

C. Polarity Effects

A significant difference in breakdown behavior is observedbetween positive and negative bias polarities. This effectcan be seen in the breakdown voltage (Vbd) distributions inFig. 5(a) and in the Weibull TDDB plots in Fig. 5(b). ACVS degrades the barrier of the pMTJ over time, resultingin an increase of the tunneling current before reaching hardbreakdown. The polarity dependence manifests as a differencebetween the positive and negative Vbd. Fig. 5(a) shows Vbddistributions from the voltage ramp-to-breakdown testing forboth polarities. The Vbd of positive polarity is 70 mV higherthan that of negative polarity (4.5% difference in Vbd with Pvalue <10−28). The proposed reason involves the modulationof the tunneling current due to the pMTJ state and thestrong bias dependence of Rap. For a ramped stress, the

breakdown occurs when a set of (+) and (−) voltages producesapproximately the same absolute current.

The polarity effect can be observed in the time domain, suchas in Fig. 5(b), by comparing the +1.15 and −1.15 V time tobreakdown distributions and noting ∼20 times greater t63 forpositive polarity stress. For the example device in Fig. 5(b),I (−1.15 V) = 220 μA but I (+1.15 V) = 186 μA, resultingin substantially more SH for the (−) bias and leading to afaster breakdown. The t63 is worse for the bipolar pulse stresscompared with the unipolar cases as shown in Fig. 5(b), whichappears to be consistent with other studies [11]. The physicalmechanism of this reduced lifetime needs further investigationdespite the fact that the applied bipolar duty cycle of this workdoes not represent a realistic memory use case.

D. Write Voltage Window

We have measured a large operating window in 45-nmpMTJ devices, which possess a median Vbd, 50 ns−Vc, 50 ns >1 V for both polarities (Vc: switching voltage). As shownin Fig. 6, the separation between the median Vc and the medianVbd is 18 σ and 25 σ for AP → P and P → AP, respectively.

KAN et al.: STUDY ON PRACTICALLY UNLIMITED ENDURANCE OF STT-MRAM 3643

This margin is adequate to cover the temporal and spatialvariations of switching. When the switching and breakdowndistributions on identical devices are considered, the worst bitout of 1 Gbit (∼6 σ) still maintains ample write-to-breakdownseparations of 0.44 and 0.68 V for AP → P and P → APswitching, respectively [7].

E. Temperature Dependence and Self-Heating Effects

Temperature has a substantial impact on the time to failuredue to thermally enhanced bond breakage above critical fields.CVS TDDB properties between 25 °C and 125 °C wereinvestigated and shown in Fig. 7(a). β remained relativelyindependent of temperature (1.1–1.4) but a substantial reduc-tion of t63 was observed, with t63, 25 °C ∼ 250 × t63, 125 °C.Due to the several orders of magnitude difference betweenthe transistor gate dielectric leakage current and typical pMTJswitching current densities [Fig. 2(a)], the Joule heating of theMgO barrier needs to be considered. The 3-D finite-elementmodeling results of Joule heating in a pMTJ, its top andbottom electrodes, and its encapsulation are shown in Fig. 7(b).In Fig. 7(b), a 50-nm pMTJ subjected to typical operatingvoltages (e.g., 0.25–0.5 V) at room temperature would experi-ence relatively a mild barrier temperature increase of ∼20 °Cwithin 25 ns. But, this heating increases quadratically withbias voltage. The barrier temperature can reach 120 °C at1 V, negatively impacting the time to failure substantially. Thisclearly shows the importance of controlling switching voltageas a critical design parameter.

F. Acceleration Models and Endurance Extrapolation

Even though a large write margin was demonstrated,the voltage window value itself does not provide a con-crete description of the time-to-failure at specific operatingpoints. To understand the reliability at typical write voltages,breakdown statistics from a wide range of stress voltages(0.95–1.50 V) were collected, with t63 spanning 9 orders ofmagnitude in time. The resultant t63 values are shown inFig. 8(a) along with fitting comparisons to two commonlyknown TDDB acceleration models. It is apparent that theexponential E-model provides a poor fit over this voltagerange, failing to fit both the low and high voltage rangessimultaneously. The best fits for the positive and negativepolarity lifetimes are provided by the 1/E model. This modeland the average β for all these distributions were used toextrapolate the t63 and t1ppm lifetimes. As shown in Fig. 8(b),the ten year, 50% duty-cycle reliability (> 1015×50-ns cycles)can be achieved over the range of operating voltages. As notedin Section I, it is virtually impossible to test this level ofcycling endurance on a realistic memory array. In our priorwork [7], however, a representative single device was subjectedto cycling (±0.65 V, 50 ns) at 90% duty cycle for more thantwo months, achieving an endurance of >1014 without anydegradation (test eventually aborted due to time constraints).

G. Use Cases and Practically Unlimited Endurance

We have projected that even the weakest 1 ppm ofpMTJs possess an endurance of more than 1015 write cycles

Fig. 9. Calculated ten year endurance requirements for L2 and L3SRAM or MRAM based on cache access frequency (obtained throughSPEC CPU2006 workload simulations).

(Fig. 8(b)), a range that is often considered unlim-ited [12]–[14]. However, the actual endurance requirementsof various applications are not aligned with this description,as shown in Table I. For example, one of the highly soughtimplementations of STT-MRAM is the replacement of theSRAM level-3 (L3) or level-2 (L2) cache in a processor. Weconducted system-level workload characterizations with deeplearning and memory-intensive SPEC CPU2006 benchmarksrunning on a modern processor (Quad-Core Intel Skylake,256 KByte/core L2, 1.5 MByte/core L3, 64 Byte cache line).The frequency of cache accesses was found to be 1–20 millionaccesses per core per second for L3 and 10–100 millionaccesses per core per second for L2. If ten years of 100%system uptime is assumed, the memory cells in the L2 cachewould need to be resilient against as many as 1013 write cycles.An iso-area implementation of STT-MRAM in this scenarioenables a denser cache due to STT-MRAM’s smaller bitcellfootprint and allows the writes to be more sparsely distrib-uted. In this case, devices in L2 and L3 would experienceapproximately 1012 and 1010 writes, respectively, as shown inFig. 9. For unified embedded NVM implementations of STT-MRAM [15]–[16], such as in wearables and Internet-of-Thingsdevices, the ten year write access estimation is also well below1015 cycles. Depending on the density and performance, onlybetween 109 and 1010 cycles are expected. Precise estimationsare dependent on specific applications and usage patterns.However, the results of our work provide a useful upperbound on the classification of practically unlimited endurancethrough the conservative assumption of relatively high writeduty cycles with 100%, uninterrupted system utilization.

The most unlikely, but an extreme write case occurs duringa “repeated address attack” (R.A.A), where an attacker stressesa single cache line repeatedly in hopes of causing a harderror [17], [18]. For an AP–P write voltage of −0.55 V,the worst 1 ppm still survives this attack for 7.2 years anda typical device survives for 107 years.

As summarized in Table I, the use case simulations indicatethat STT-MRAM can be used for target applications withoutthe concern of endurance failure. Furthermore, the ability fordevices to sustain well beyond the required 1012 cycles forpractically unlimited endurance can enable greater flexibilityin write driver design for more efficient write operation byminimizing write error rates.

3644 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 9, SEPTEMBER 2017

TABLE ISTT-MRAM EXAMPLE USE CASES AND ENDURANCE REQUIREMENTS

Fig. 10. (a) t63 versus voltage plots for 25-, 45-, and 70-nm diameter devices. Dashed lines represent area scaled data to 25 nm. By combiningarea scaling and SH, all data match the reference (bold black line). (Inset) example Weibull plots for several different diameter devices. (b) Barriertemperature versus voltage from 3-D thermal simulation at 25 °C for three different pMTJ sizes with the same barrier RA product [7].

H. Device Size Scaling

Scaling down the size of pMTJs can reduce the switchingcurrent substantially to enable fast switching in compactbitcells. By reducing the diameter of devices below 30 nm,the switching current can be compatible with the currentdrivability of sub-10 nm FinFET access transistors. Alongwith relevant power, performance, and area benefits, we nowshow that the endurance also significantly improves as pMTJsare scaled down [Fig. 10(a)]. It is worth noting that β ismaintained around ∼1 even in small devices (25 nm) as shownin the inset of Fig. 10(a). For device areas corresponding to70-, 45-, and 25-nm diameter, the t63 at 1.25 V increasesdramatically by ∼57 000 times (from 0.01 → 0.2 → 570 s).It is observed that the average Vbd also increases from 1.63 to1.91 V by shrinking the pMTJ diameter from 45 to 25 nm.This improvement rate is greatly beyond the range attributableto the Poisson area scaling

t63,1

t63,2=

(A2

A1

)1/β

(4)

or defect clustering due to oxide variations [19]. Instead,the measured improvement can be attributed to the effectof reduced SH in smaller pMTJs, as shown in Fig. 10(b).By considering both the SH and Poisson area scaling effects,a consistent set of lifetimes was found for all sizes as shownin Fig. 10(a). The observation that Vbd increases as pMTJs arescaled implies a larger write window for advanced technologynodes.

IV. CONCLUSION

In this paper, a comprehensive study on the enduranceof the MgO tunnel barrier of STT-MRAM was conductedwith respect to several operating parameters such as writevoltage, polarity, pulsewidth, duty cycle, and temperature.The experimental results and TDDB models of this workproject >1015 write cycles. Furthermore, through system-levelworkload characterizations and write traffic calculations fora variety of memory applications, we have found that writeendurance in the range of 1012 cycles would be sufficientfor practically unlimited operations. The results of this paper

KAN et al.: STUDY ON PRACTICALLY UNLIMITED ENDURANCE OF STT-MRAM 3645

suggest that a large write voltage window along with practi-cally unlimited endurance can be obtained in advanced pMTJs.In addition, the TDDB and breakdown voltage studies ofdeeply scaled devices down to 25-nm diameter revealed thatthe endurance improved further with reduction in device size,presenting a favorable prospect for embedded STT-MRAM forsub-10 nm CMOS nodes.

ACKNOWLEDGMENT

The authors would like to thank L. Xue, R. Wang,A. Kontos, S. Liang, M. Bangar, H. Chen, and S. Hassan fromApplied Materials, Inc., Sunnyvale, CA, USA, and S. Kim,W. N. Hsu, and X. Lu from Qualcomm Technologies, Inc.,San Diego, CA, USA, for their valuable support and discus-sions.

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Jimmy J. Kan received the Ph.D. degree in mate-rials science from the University of California atSan Diego, San Diego, CA, USA.

In 2013, he joined Qualcomm TechnologiesInc., San Diego, CA, USA, as a Senior Engineerin research and development, where he special-izes in materials and device engineering, bitcelldesign/optimization, and spintronic technologypathfinding.

Chando Park received the Ph.D. degree in mate-rials science and engineering from Carnegie Mel-lon University, Pittsburgh, PA, USA, in 2004.

He joined Qualcomm Technologies Inc., SanDiego, CA, USA, as a Senior Staff Engineer,in 2013, responsible for materials, process, anddevice characterization for MRAM. Prior to Qual-comm, he was with HGST, San Jose, CA, USA,and Western Digital, Fremont, CA, USA, wherehe developed advanced read sensors.

Chi Ching received the Ph.D. degree in nuclearphysics from the University of Michigan, AnnArbor, MA, USA.

In 2005, he joined Applied Materials, Sunny-vale, CA, USA, and has expertise in plasma etch-ing, doping, and ion implantation. He is currentlya member of the PVD Core Technology Divisionspecializing in commercialization of spintronicfilm deposition tools.

Jaesoo Ahn received the B.S. and M.S. degreesfrom Seoul National University, Seoul, SouthKorea, in 2001 and 2003, respectively, and thePh.D. degree from Stanford University, Stanford,CA, USA, in 2013.

He is currently a Senior Engineer with theAdvanced Product and Technology DevelopmentGroup, Applied Materials, Sunnyvale, CA, USA,where he is involved in next generation memoryprocess development and integration.

3646 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 9, SEPTEMBER 2017

Yuan Xie (F’15) received the Ph.D. degree fromPrinceton University, Princeton, NJ, USA.

He is currently a Professor with the Universityof California at Santa Barbara, Santa Barbara,CA, USA. His current research areas includecomputer architecture, design automation, andVLSI design.

Dr. Xie was elevated to IEEE Fellow in 2015due to the contribution in architecture and designautomation for 3-D ICs.

Mahendra Pakala is currently responsible forMRAM process development at Applied Materi-als, Sunnyvale, CA, USA. Prior to joining in 2012,he was the Director of Process Development withWestern Digital from 2005 to 2012, where hewas responsible for the development and transferof magnetic tunnel junctions in disk drives tomanufacturing, and the Director of AdvancedMaterials with Grandis Inc., Milpitas, CA, USA.

Seung H. Kang received the Ph.D. degree fromthe University of California at Berkeley, Berkeley,CA, USA.

He is currently a Director of Engineering,with Corporate Research and Development,Qualcomm Technologies Inc., San Diego,CA, USA, where he has led MRAM andadvanced memory research. He has authored orco-authored 100 papers and delivered over50 keynote and invited speeches. He holds over500 patents granted globally.