IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 3, MARCH 2015 1063

Modeling and Separate Extraction Technique forGate Bias-Dependent Parasitic Resistances

and Overlap Length in MOSFETsJungmin Lee, Hagyoul Bae, Jun Seok Hwang, Jaeyeop Ahn, Jun Tae Jang, Jinsoo Yoon, Sung-Jin Choi,

Dae Hwan Kim, Senior Member, IEEE, and Dong Myong Kim, Member, IEEE

Abstract— We report a technique for separate extraction ofextrinsic source/drain (S/D) resistances (RSe/RDe) and gatebias (VGS)-dependent but channel length (L)-independentintrinsic source/drain (RSi/RDi) resistances for the over-lap region in MOSFETs. For extraction of the overlaplength (Lov) in the heavily doped S/D regions, an analyti-cal capacitance model for the depletion region is employedwith the gate-to-source and gate-to-drain capacitance–voltage(CG-S, CG-D) characteristics. After verifying the extractedoverlap length through a 2-D technology computer-aideddesign simulation, we successfully extract VGS-dependentRSi = 0.9∼3.7 � and RDi = 1.0∼3.9 � in an n-channelMOSFET with W = 140 μm and L = 0.35 μm. In addition,VGS- and L-independent extrinsic S/D resistances are separatelyextracted to be RSe = 5.1 � and RDe = 5.0 �, respectively.

Index Terms— Drain resistance, extrinsic resistance, intrinsic,MOSFET, overlap length (Lov), source resistance.

I. INTRODUCTION

AS MOSFETs are scaled down to establish improvedelectrical performance and integration density, the

source (RS) and drain (RD) resistances become increasinglyimportant in terms of long-term performance and reliability inintegrated circuits. Therefore, accurate modeling and extrac-tion of RS and RD considering gate bias (VGS) dependenceis necessary for prediction of the drive current degrada-tion [1], [2]. RS and RD are generally regarded as symmetricand VGS-independent parameters, but practical asymmetryand VGS-dependence can be induced by asymmetric layout,process variation, and/or long-term degradation caused byhot carriers. Even with symmetrical device structure and

Manuscript received June 9, 2014; revised October 17, 2014 andDecember 5, 2014; accepted January 3, 2015. Date of publicationJanuary 19, 2015; date of current version February 20, 2015. This work wassupported in part by the National Research Foundation of Korea through theMinistry of Education, Science and Technology, Korean Government underGrant 2013R1A2A2A05005472, in part by the Brain Korea 21 Program forLeading Universities and Students, and in part by the IC Design EducationCenter, Korea Advanced Institute of Science and Technology, Daejeon, Korea.The review of this brief was arranged by Editor D. Esseni.

J. Lee, J. S. Hwang, J. Ahn, J. T. Jang, J. Yoon, S.-J. Choi, D. H. Kim, andD. M. Kim are with School of Electrical Engineering, Kookmin University,Seoul 136-702, Korea (e-mail: dmkim@kookmin.ac.kr).

H. Bae was with the School of Electrical Engineering, Kookmin University,Seoul 136-702, Korea. He is now with the Department of Electrical Engineer-ing, Korea Advanced Institute of Science and Technology, Daejeon 305-701,Korea.

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2015.2388704

fabrication through the same process, hot carriers duringlong-term operation cause asymmetry in RS and RD . Theasymmetry observed in RS and RD can also be used as anindicative parameter of physical mechanisms on degradationby hot carrier stress or long-term operation. In particular,RS is more influential on the electrical performance of thetransconductance, the cutoff frequency over RD .

Although there have been various methods for separateextraction of RS and RD [3]–[7], both asymmetry andVGS-dependence have not been fully considered.There have been useful works for the extraction ofVGS-dependent RS and RD combining the additionalresistance method [8], [9]. Even if these methods haveconsiderable accuracy, additional external resistance and/ornonlinear fitting process with a body contact is required forthe extraction of VGS-dependent RS and RD .

We propose a technique for separate extraction ofVGS-dependent intrinsic source/drain (S/D) resistances(RSi/RDi) and VGS-independent components (RSe, RDe).As RSi and RDi are predominantly influenced by the verticalfield through the overlapped S/D regions, we first obtainedthe overlap length (Lov) from the analytical capacitancemodel of the depletion region and verified it through a2-D Sentaurus TCAD simulation. To completely extractRS separated from RD , we combined two methods. First,the transfer length method (TLM) was used for extractionof RS + RD including both VGS-dependent (RSi, RDi)and -independent (RSe, RDe) components. Second, thedual-sweep combinational transconductance technique [12]combined with the channel resistance method (CRM) [10]was utilized for VGS-independent RS + RD and VGS-dependentRS − RD .

II. EXTRACTION OF OVERLAP LENGTH WITH

ANALYTICAL CAPACITANCE MODEL

IN MOSFETS

Fig. 1 shows a cross-sectional structure associated withresistances and capacitances of an n-channel MOSFET forcharacterization through the equivalent circuit.

The VGS-dependent overlap capacitance Cov is defined asthe capacitance between the gate and the S/D overlap regionto be

Cov(VGS) = εoxW · Lov(VGS)/tox (1)

0018-9383 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

1064 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 3, MARCH 2015

Fig. 1. Cross-sectional structure and associated equivalent circuit model withresistances and capacitances in n-channel MOSFETs.

with εox as the permittivity and tox as the thickness of theinsulating gate oxide with W as the gate width of the MOSFETunder characterization.

In [13], even though VGS-dependent Lov was proposedas an empirical model, the analytical model is lacking inVGS-dependent Lov modeling. When the gate is biased atVi < VGS < VFB,ov, as a bias condition for a deple-tion of the overlapped region (Vi ≡ the gate voltage forthe surface potential to be equal to the Fermi potential(ϕSD,ov = φ f ), VFB,ov = the flat band voltage for the overlapregion), charges in the overlapped region are dominated bythe depleted acceptors in the p-type substrate and accumulatedelectrons in the highly doped (n+) S/D region. Consequently,Cov can be modeled as

1

Cov(VGS)

∣∣∣∣Vi<VGS<VFB,ov

= tox

εox(W · Lov)+ 1

Cd (VGS) + Cn

(2)

with Cd (VGS) and Cn as capacitances for depleted acceptorsand accumulated electrons, respectively.

Equation (2) can be modified by the well-known chargemodel [14] described as

Cov(VG)|Vi<VG<VFB,ov= Cox (W · Lov)

1 + k(

1√|ϕSD,ov|+ 1√Vth

eϕSD,ov

2Vth

)

k ≡√

2C2ox/qεsiNSD,ov,

Cox ≡ εox/tox (3)

with ϕSD,ov as the surface potential, NSD,ov as the dopingconcentration in the n+ S/D overlap region, Vth as the thermalvoltage, and Cox (≡ εox/tox) as the oxide capacitance per unitarea.

The gate-to-drain capacitance (CGD = Cov + Cof) in Fig. 1for Vi < VGD < VFB,ov is described as

CGD|Vi<VGD<VFB,ov= Cox(W · Lov,D)

1+ k(

1√−ϕSD,ov+ 1√

Vthe

ϕSD,ov2Vth

)

+ Cof

(4)

with Cof as the VGS-independent capacitance associated withthe fringing field between the sidewall of the gate and the S/Dedge. We note that Cof becomes more significant and compa-rable with other capacitances in MOSFETs with scaling down.

Fig. 2. (a) Simulated CGD–VGD characteristics for various Lov,D in ann-channel MOSFET with W/L = 1/0.13 [μm/μm] when VGD < VFB,ov.(b) Comparison of the physical (obtained from experimental data) Lov,D andLov,D calculated by the analytical charge model for various Lov,D .

As mentioned above, however, it is well known that Cofis independent of VGS. Consequently, by eliminating Cofthrough (4) with the boundary condition at VGD = VFB,ov, theoverlap length in the drain (Lov,D) can be extracted through

Lov,D = CGD|VGD=VFB.ov− CGD|Vi<VGD<VFB,ov

(1 − 1/λ(ϕSD,ov)) · Cox · W

λ(ϕSD,ov) ≡ 1 + k(

1√−ϕSD,ov+ 1√

Vthe

ϕSD,ov2Vth

) . (5)

Through the 2-D TCAD simulation, we confirmed thatLov,D decreases with decreasing VGD. This is due to theadditional capacitance component (CSD,add) away from theS/D overlap region which is indirectly influenced by VGS.We define the physical Lov as the maximum value of exper-imentally obtained overlap length at VGS ∼= VFB,ov for min-imizing the effect of CSD,add. Fig. 2(a) shows the simulatedCGD–VGD characteristics for various Lov,D in an n-channelMOSFET with W/L = 1/0.13 [μm/μm] and parameterssummarized in Fig. 2(b). From the proposed analytical capac-itance model, we simulated various cases of physical Lov,D

and confirmed good agreement between the physical Lov,D

(defined in the simulation) and analytical Lov,D (obtained fromexperimental data), as shown in Fig. 2(b).

After verifying the validity of the proposedmodel, we extracted Lov from the experimental data.

LEE et al.: MODELING AND SEPARATE EXTRACTION TECHNIQUE 1065

Fig. 3. Measured (a) CG-DS–VG-DS, (b) CG-S–VG-S characteristics of ann-MOSFET with W/L = 140/0.35, 0.7, 1.05, 1.75 [μm/μm]. (c) ExtractedLov, Lov,D , and Lov,S with various gate lengths.

Combining three different capacitance–voltage measurementconfigurations [CG-DS–VG-DS, CG-D–VG-D,CG-S–VG-S ,as shown in Fig. 3(a) and (b)], overlap lengths(Lov, Lov,D , and Lov,S) were extracted for various gatelengths (Lg), as shown in Fig. 3(c). It shows good consistencybetween Lov and Lov,D + Lov,S .

III. SEPARATE EXTRACTION OF GATE BIAS-DEPENDENT

S/D RESISTANCES

As shown in Fig. 1 for the MOSFET biased in the linearoperation, the resistance model for the drain-to-sourcecurrent (IDS) path includes VGS-dependent intrinsic

Fig. 4. (a) RTOT − Lg for the extraction of RS + RD withVGS = 1.6 ∼ 3.6 V. (b) RTOT − VG for the extraction of RSe + RDe inn-MOSFET with W/L = 140/0.35 [μm/μm]. (c) Extracted RD − RS usingthe dual-sweep combinational transconductance technique. Inset shows gm inforward and reverse modes.

source (RSi) and drain resistances (RDi), VGS-independentextrinsic source (RSe) and drain (RDe) resistances as follows:

RTOT(VGS) ≡ VDS/IDS = RS(VGS) + RD(VGS)

+ Rch(VGS, Lg) (6)

RS(VGS) = RSi(VGS) + RSe, RD(VGS)

= RDi(VGS) + RDe. (7)

As the first step for separate extraction of each component,we employ the TLM technique for Rsum ≡ RS(VGS) +RD(VGS). The TLM has been generally used for extraction ofRSD = RS + RD from the VGS-dependent total resistanceextrapolated to VGS − VT ∼= ∞ under the assumption ofVGS-independent RS and RD . However, RS and RD are clearly

1066 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 3, MARCH 2015

TABLE I

VGS-DEPENDENT AND INDEPENDENT S/D RESISTANCES IN A MOSFET

WITH W/L = 140/0.35 [μm/μm]

VGS-dependent by the overlap region directly influenced bythe vertical field. Therefore, we extract VGS-dependent but thechannel length (L)-independent (RS + RD) with Lov obtainedfrom the analytical capacitance model. It can be described as

RTOT|Lg=Lov = RSi(VGS) + RSe + RDi(VGS) + RDe. (8)

Fig. 4(a) shows extracted RTOT(VGS) = RS(VGS) + RD(VGS)as a function of VGS.

As the next step, we use the CRM for extractionof VGS-independent RSe + RDe. As VGS increases more,VGS-dependent resistance components get smaller. Therefore,RSe + RDe is obtained at VGS � VT through

RTOT|VGS�VT= RSe + RDe. (9)

Fig. 4(b) shows the extrapolated RTOT (= RSe + RDe) ina MOSFET with W/L = 140/0.35 [μm/μm]. By sub-tracting (9) from (8), RSi(VGS) + RDi(VGS) is obtained.RSi(VGS) + RDi(VGS) can be separated by Lov,D and Lov,S

extracted from the analytical capacitance model through

RSi(VGS) = Lov,S

Lov,S + Lov,D× (RSi(VGS) + RDi(VGS)) (10)

RDi(VGS) = Lov,D

Lov,S + Lov,D× (RSi(VGS) + RDi(VGS)). (11)

By the dual-sweep combinational transconductance tech-nique as the next step, Rdif ≡ RD(VGS) − RS(VGS) canbe experimentally obtained from the forward and reversetransconductances in the saturation region. As shown inFig. 4(c), we extracted Rdif ≡ RD(VGS) − RS(VGS) from theforward and reverse transfer characteristics for the same draincurrent (IDo) ≡ ID,FWD(VGS,FWD) = ID,REV(VGS,REV) of theMOSFET through

Rdif ≡ RD(VGS) − RS(VGS) = VGS,REV − VGS,FWD

IDo. (12)

We separated RD(VGS) from RS(VGS) combining Rsum ≡RD(VGS) + RS(VGS), obtained from the TLM, with Rdif ≡RD(VGS) − RS(VGS) from the dual-sweep combinationaltransconductance technique. Finally, using the separated S/Dresistances with (10) and (11), RSe and RDe are separated.

Table I shows separated resistances for various VGS in then-channel MOSFET with W/L = 1/0.13 [μm/μm]. As VGSdecreases, VGS-dependent resistances increase significantly incontrast to VGS-independent resistances. As a verification ofthe proposed method in asymmetric MOSFET structures, weintentionally loaded a resistance (RL = 3.9 �) in drain contact

TABLE II

VGS-DEPENDENT AND INDEPENDENT S/D RESISTANCES IN A MOSFET

HAVING AN EXTERNAL DRAIN RESISTANCE RD,ext = 3.9 [�]

WITH W/L = 140/0.35 [μm/μm]

to make the device asymmetric for the extrinsic drain resis-tance. As expected, the extracted results show good agreementwith the increase in VGS-independent RD .

Expecting intentional asymmetric structure betweenRS and RD , due to a limited availability of asymmetricS/D MOSFETs, we added an intentional load resistance(RD,ext = 3.9 �) to the drain contact. Consequently, theextracted results show good agreement with the increase inVGS-independent RDe, as shown Table II.

IV. CONCLUSION

Considering the asymmetry and VGS-dependence in theS/D resistances caused by layout, process variation, andlong-term device degradation by hot carriers, we proposeda technique for separate extraction of VGS-dependent butL-independent S/D resistances (RSi, RDi) related to the overlapregion and VGS-independent S/D resistances (RSe, RDe) inMOSFETs. For extraction of VGS-dependent RSi and RDi, theextraction technique based on the analytical capacitance modelfor the overlap length (Lov) was also reported. Verifying thevalidity of the extraction technique for Lov through a2-D TCAD simulation, we successfully extractedVGS-dependent RSi and RDi applying the extractedLov from the experimental results. We expect that theproposed technique for separate extraction of VGS-dependentS/D resistances and the overlap length Lov as well asVGS-independent S/D resistance components is useful foraccurate modeling, characterization, and robust design ofCMOS-based integrated circuits and systems.

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Jungmin Lee received the B.S. degree in electri-cal engineering from Kookmin University, Seoul,Korea, in 2014, where he is currently pursuingthe M.S. degree with the Department of ElectricalEngineering.

Hagyoul Bae received the B.S. and M.S. degreesfrom Kookmin University, Seoul, Korea, in 2007 and2009, respectively, where he is currently pursuingthe Ph.D. degree with the Korea Advanced Instituteof Science and Technology, Daejeon, Korea.

His current research interests include characteriza-tion and modeling of silicon nanostructure devices,flash memory devices, amorphous oxide semicon-ductor thin-film transistors, and their device physics.

Jun Seok Hwang received the B.S. degree in elec-trical engineering from Kookmin University, Seoul,Korea, in 2013, where he is currently pursuingthe M.S. degree with the Department of ElectricalEngineering.

Jaeyeop Ahn received the B.S. degree inelectrical engineering from Kookmin University,Seoul, Korea, in 2013, where he is currently pur-suing the M.S. degree with the Department ofElectrical Engineering.

Jun Tae Jang received the B.S. degree in elec-trical engineering from Kookmin University, Seoul,Korea, in 2014, where he is currently pursuingthe M.S. degree with the Department of ElectricalEngineering.

Jinsoo Yoon received the B.S. degree in electri-cal engineering from Kookmin University, Seoul,Korea, in 2014, where he is currently pursuingthe M.S. degree with the Department of ElectricalEngineering.

Sung-Jin Choi received the M.S. and Ph.D. degreesin electrical engineering from the Korea AdvancedInstitute of Science and Technology, Daejeon, Korea,in 2012.

He is currently an Assistant Professor with theSchool of Electrical Engineering, Kookmin Univer-sity, Seoul, Korea.

Dae Hwan Kim (M’08–SM’14) received the B.S.,M.S., and Ph.D. degrees in electrical engineeringfrom Seoul National University, Seoul, Korea, in1996, 1998, and 2002, respectively.

He joined the School of Electrical Engineering,Kookmin University, Seoul, in 2005, where he iscurrently an Associate Professor.

Prof. Kim is a member of the Society for Infor-mation Display and the Institute of ElectronicsEngineers of Korea.

Dong Myong Kim (S’86–M’88) received the B.S.(magna cum laude) and M.S. degrees in electronicsengineering from Seoul National University, Seoul,Korea, in 1986 and 1988, respectively, and thePh.D. degree in electrical engineering from theUniversity of Minnesota, Twin Cities, MN, USA,in 1993.

He has been with the School of ElectricalEngineering, Kookmin University, Seoul, Korea,since 1993.