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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 6, JUNE 2008 1055

An Optimal Network-Flow-Based SimultaneousDiode and Jumper Insertion Algorithm

for Antenna FixingZhe-Wei Jiang, Student Member, IEEE, and Yao-Wen Chang, Member, IEEE

Abstract—As technology enters the nanometer territory, theantenna effect plays an important role in determining the yieldand reliability of a VLSI circuit. Diode and jumper insertions arethe most effective techniques to fix the antenna effect. However,due to the increasing design complexity and the limited routingresource, applying diode or jumper insertion alone cannot achievea high antenna fixing rate. In this paper, we give a polynomial-time antenna violation detection/fixing algorithm by simultaneousdiode and jumper insertion with minimum cost, which is basedon a minimum-cost network-flow formulation. Experimental re-sults show that our algorithm consistently achieves much higherantenna fixing rates than the state-of-the-art jumper and diodeinsertion algorithms alone.

Index Terms—Design for manufacturability, interconnect,network flow algorithm, physical design.

I. INTRODUCTION

MANUFACTURING reliability and yield in VLSI designsare becoming a crucial challenge as the feature sizes

shrink into the nanometer scale. The antenna effect arising inthe plasma process is an important problem in achieving ahigher reliability and yield.

A. Antenna Effect

The antenna effect is caused by the charges collected on thefloating interconnects which are connected to only a gate oxide.During the metallization, long floating interconnects act astemporary capacitors and store charges gained from the energyprovided by fabrication steps such as plasma etching, chemicalmechanical polishing, etc. If the collected charges exceed athreshold, Fowler–Nordheim tunneling current will dischargethrough the thin oxide and cause gate damage. On the otherhand, if the collected charges can be released before exceeding

Manuscript received August 4, 2007; revised November 6, 2007. Thispaper was presented in part at IEEE/ACM International Conference onComputer-Aided Design (ICCAD’06), November 2006. This work was sup-ported in part by SpringSoft Inc., under Contracts NSC 94-2215-E-002-005,NSC 94-2215-E-002-030, and NSC 94-2752-E-002-008-PAE. This paper wasrecommended by Associate Editor J. Hu.

Z.-W. Jiang is with the Graduate Institute of Electronics Engineering,National Taiwan University, Taipei 106, Taiwan, R.O.C. (e-mail: [email protected]).

Y.-W. Chang is with the Department of Electrical Engineering and the Grad-uate Institute of Electronics Engineering, National Taiwan University, Taipei106, Taiwan, R.O.C., and also with Waseda University, Kitakyushu 808-0135,Japan (e-mail: [email protected]).

Digital Object Identifier 10.1109/TCAD.2008.923246

Fig. 1. Illustration of antenna effect: (a) An example routing. (b) Late stageof metal 1 layer pattern etching of figure (a). The collected charges on the rightside of the metal 1 pattern may cause damage to the connected gate oxide.(c) Late stage of metal 2 layer pattern etching of figure (a). All the collectedcharges can be released through the connected diffusion on the left side.

the threshold through a low impedance path, such as a diffusion,the gate damage can be avoided. For example, considering therouting in Fig. 1(a), the interconnects are manufactured in theorder of poly, metal 1, and metal 2. After manufacturing metal 1[see Fig. 1(b)], the collected charges on the right metal 1 patternmay cause damage to the connected gate oxide. The dischargingpath is constructed after manufacturing metal 2 [see Fig. 1(c)],and thus, the charges can be released through the connecteddiffusion on the left side.

There are three popular solutions proposed to reduce theantenna effect [5].

1) Jumper insertion: Break the signal wires with antennaviolation and route them to the top metal layer. Thisapproach reduces the collected charges during the man-ufacturing process but incurs two vias for each jumper.

2) Embedded protection diode: Add a protection diode onevery input port for every standard cell. This approachprevents all input ports from the charge damage butconsumes unnecessary areas when there is no antennaviolation at the embedded input port.

3) Diode insertion after routing: Fixing only the wires withantenna violations will not waste routing resources. Dur-ing wafer manufacturing, all the inserted diodes are float-ing (or ground). Since the input ports are high impedance,the charge on the wire flows through the inserted floating/ground diode.

0278-0070/$25.00 © 2008 IEEE

1056 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 6, JUNE 2008

The difference between diode and jumper insertions is theconsumed resources of the fixed circuit. For jumper insertion,each jumper needs free spaces to route to the top metal layer,and it incurs at least two vias for each jumper. For diodeinsertion, the consumed resources are the free spaces on thesubstrate. If a violating wire lies above a space that can insert adiode, the diode is directly inserted below the wire. Otherwise,if there is no free space under the wire, extension wires arenecessary to connect the violating wire to a diode insertionspace [7], [8]. Both the vias and the extension wires willincrease the driving load of the antenna violating wire, and thus,the incurred RC delay will reduce the circuit performance. Incurrent nanometer technology, the induced RC delay of a viais several tens of times larger than that of 1-µm metal wire.Therefore, in order to minimize the cost of fixing the antennaviolations, we shall apply both diode and jumper insertions andconsider the interaction between them to minimize the cost forthe fixing.

B. Previous Work

Maly et al. [11] translated the antenna condition detectionproblem into a layout analysis problem. It can be solved by ageneral-purpose design-rule checking program. However, themethod does not indicate any measure to feedback the antennainformation to the diode or jumper insertion. Shirota et al. [12],[13] proposed a rip-up and reroute method in a traditionalrouter to reduce the antenna effect damage. Ho et al. [6]proposed full-chip routing with antenna avoidance. Theseworks [6], [12], [13] reduce the antenna effects during therouting stage, whereas the works presented in [5], [7], [8], and[16]–[18] try to fix the antenna violations in the postlayoutstage. Chen et al. [5] presented a heuristic to insert the diodeunder the wire with antenna violation. However, in modernhigh-density VLSI circuit, there is little free space for the“under-the-wire” diode insertion. Wu et al. [18] proposed alayer assignment technique to handle antenna avoidance by atree-partitioning algorithm, but routing blockages are not con-sidered in their algorithm. Su and Chang [14], [15] presentedan optimal greedy jumper insertion algorithm that uses theminimum number of jumpers to fix the antenna violation on aspanning tree. Recently, Su et al. [16], [17] further presented agreedy optimal jumper insertion algorithm, called the bottomup jumper insertion with obstacles (BUJIO), which uses theminimum number of jumpers to fix the antenna violation on aSteiner tree with obstacles. Huang et al. [7], [8] solved the diodeinsertion and routing problem by a minimum-cost network-flow-based algorithm, called the diode insertion and routingby min-cost flow (DIRMCF). The violating wires, the routinggrids, and the feasible diode positions are transformed into aflow network, and then, the problem is solved by the minimum-cost network-flow algorithm. Both the positions of inserteddiodes and the extension wires can be determined through theresulting flow.

C. Motivation

In all the previous works [6]–[8], [14]–[18], the antennaviolations are fixed by jumper or diode insertion alone, and

Fig. 2. Illustration of the consumed resources by jumpers and extensionwires. Three violating wires, nets 1, 2, and 3, need to be fixed. (a) Threeviolating wires: Net 1 (2 jumpers needed), Net 2 (1 jumper needed), and Net 3(2 jumpers needed). (b) Fix by jumper insertion: no. of jumpers = 2 + 1 + 2 =5. (c) Fix by diode insertion: length of extension wire: = 1 + 2 + 4 = 7.(d) Fix by simultaneous diode/jumper insertion: no. of jumpers = 1, lengthof extension wire = 2.

the interaction between jumper and diode insertions is ignored.Considering the routing topology in Fig. 2(a) and the antennabound of five unit length,1 we need two jumpers for net 1,one jumper for net 2, and two jumpers for net 3 to fix theantenna violation. It requires totally five jumpers by jumperinsertion alone [see Fig. 2(b)] or seven units of extension wireby diode insertion alone [see Fig. 2(c)] to fix the antennaviolation. If we consider the interaction between diode andjumper insertions and fix the violations by simultaneous diodeand jumper insertion (SDJI), however, the antenna effects canbe fixed by merely one jumper and two units of extension wire[see Fig. 2(d)], which consumes much fewer resources thandiode or jumper insertion alone.

In [5], [7], and [8], one inserted diode is assumed to protectall input ports that are connected to the same output port. Thisassumption is not always true in real circuits. Such as the treerepresentation of a given net in Fig. 3, both antenna weights(which could be wire-area-to-gate-size ratios, wire areas, or anyother antenna measure) of segments s1 and s2 exceed Lmax,where Lmax denotes the upper bound for antenna (i.e., anyantenna measure larger than Lmax will violate the antenna rule).If we insert only a diode on s1 or s2, after the metallizationof metal layer 1, s1 and s2 are still two individual segments,and thus, the collected charges on the other segment will stillcause damage to the connected input port. That means, in thecase of Fig. 3, we must insert at least two diodes to fix theantenna violation. Thus, a more accurate algorithm is needed

1Note that the antenna bound could also be measured by wire-area-to-gate-size ratios, wire areas, or any other antenna measure.

JIANG AND CHANG: NETWORK-FLOW-BASED SIMULTANEOUS DIODE AND JUMPER INSERTION ALGORITHM 1057

Fig. 3. Example that a net needs multiple diodes to fix the antenna violation.If both L1 and L2 exceed the antenna threshold Lmax, at least two diodes mustbe connected to s1 and s2 separately to fix the antenna violation.

to analyze the number of diodes needed to fix the antennaeffect.

D. Our Contributions

In this paper, we propose a minimum-cost network-flow-based algorithm by SDJI to aviod/fix antenna violation. Theproposed algorithm can find an optimal solution in polynomialtime. In particular, it guarantees to fix the antenna violationsif one feasible solution exists. We also present a more ac-curate model to analyze the exact number of diodes neededfor antenna fixing. Experimental results show that our workachieves higher antenna fixing rates and incurs lower costs forantenna avoidance/fixing. Compared with the state-of-the-artjumper insertion algorithm, BUJIO, alone in [16] and [17], ouralgorithm achieves more than 99.6% fixing rate even with adense 95% diode blockage rate, whereas BUJIO obtains only63.4% fixing rate on average (due to the significant blockagesfor jumper insertion), based on a set of MCNC layouts obtainedby the publicly available router MR [4], [10]. Our algorithmalso consistently achieves higher antenna fixing rates than thediode insertion algorithm, DIRMCF, alone, under various diodeblockage rates.

The remainder of this paper is organized as follows.Section II formulates the problem of detecting/fixing the an-tenna effects with SDJI. Section III presents an optimal al-gorithm for the proposed problem. Section IV reports theexperimental results. Finally, the conclusions are given inSection V.

II. PROBLEM FORMULATION

To detect/fix antenna violations, we have to check if the ef-fective conductor connecting to a gate oxide exceeds a thresholdLmax. Here, Lmax can be measured in wire-area-to-gate-sizeratio, wire area, wirelength, or any model of the strength ofantenna effect caused by conductors, same as that in [16] and[17]. To simplify the discussion, we assume that all sinks ona net are connected to a gate terminal, whereas the source isconnected to diffusion (those sinks connecting to diffusion canbe ignored since they will not cause any antenna violation forcurrent technology). Aside from checking the existence of theantenna violation, we have to know where the diodes shouldbe connected to protect the gate terminals. A violating-wire

set (VWS) is defined as a group of connected wire segments,where exactly one diode needs to be connected to one of thesewire segments to fix the antenna violation. Alternately, we canfix a VWS by one or more jumpers instead of one diode. Notethat one net can be divided into several VWSs since a net mayneed multiple diodes to fix the antenna effect, as mentioned inSection I. Take Fig. 3 as an example. The given net containstwo VWSs: One contains s1, and the other s2. Thus, exactlytwo diodes are needed for the given net.

Vias and metal wires can interplay with each other in manydifferent ways. In this paper, we try to minimize the totaldelay induced by extra vias and metal wires. To evaluate thetotal induced delay when we fix the antenna violation, wedefine the cost function Φ composed of the total wirelength ofextension wires (for diodes) and the total number of jumpers asfollows:

Φ = µ × (β × mJ + lE) (1)

where mJ is the number of jumpers inserted to fix the antennaviolations, lE is the total wirelength of extension wires inducedby diode insertion, β is a user-specified parameter for the ratioof the jumper induced delay to the unit-length extension-wireinduced delay, and µ is the unit-length extension-wire induceddelay. Note that the extension wire does not lie on a signalpropagation path since it always connects to a diode. Accordingto the Elmore delay model, only the capacitance of the exten-sion wire is considered, and thus, the induced delay is linearlyproportional to the length of the extension wire. This conceptis similar to that in [7] and [8], which minimizes the totalwirelength. It should be noted that (1) is merely an examplemodeling of the interplay of diode and jumper insertions; itwill be clear that our algorithm also applies to the cases withdifferent cost models.

With the aforementioned definitions, we can formulate theaddressed problem as follows:

• Problem ASDJI: Given a routing topology T , an antennathreshold Lmax, and a set of diode insertion positions D,identify all the antenna violations in T and find a set offeasible jumper positions, a set of diode positions D′ ⊂ D,and a set of paths P connecting some VWSs to thecorresponding diode positions, such that the total inducedcost is minimized, and all the VWSs are either brokeninto smaller antenna-safe segments by inserted jumpers orconnected to inserted protection diodes.

III. ALGORITHMS

We propose a two-phase method to solve the antenna effectdetection/fixing with SDJI (ASDJI) problem. The first phaseapplies the wire violation detection (WVD) algorithm, andthe second uses the SDJI algorithm. In the WVD algorithm,all VWSs in the given routing topology are identified, andthen, in the SDJI algorithm, the identified VWSs are fixed byeither diode or jumper insertion with the minimum delay cost.We explain the two algorithms in Sections III-A and III-B,respectively.


Fig. 4. Illustration of different cases of the connected component Ci inWVD algorithm. (a) Ci is connected to diffusion. The collected charges canbe discharged through the diffusion. (b) Ci is connected to another VWS.The collected charges may be discharged through the inserted diode of theconnected VWS. (c) Ci is not connected to any diffusion or VWSs. Thecollected charges will cause damage to connected gates.

A. WVD

We explain how to identify all the VWSs in this section. Inour assumption, the antenna violation happens when the col-lected charges connected to a gate terminal exceed the antennathreshold during the metallization. Thus, the VWS should beidentified by analyzing the intermediate topologies betweenthe metallization of each metal layer. For example, after themetallization of metal layer 2, only segments in metal layers1 and 2 are fabricated. At this intermediate stage, we shouldcompute the collected charges on the segments in metal layers1 and 2 and check whether the summation of the collectedcharges exceeds the antenna threshold. With the nature ofmetallization, the metal layers are fabricated from the bottomto the top layers. Thus, the proposed algorithm makes use ofthis nature and analyzes the intermediate topologies betweenthe completeness of each metal layer.

The WVD algorithm is summarized in Fig. 5. The graphG is used to record the intermediate topologies between themetallization of each metal layer, and the set Sviol records theidentified VWSs. For the main loop in lines 3–10, the segmentsin each metal layer are added into G in the increasing order oflayers. In lines 5–8, since only the collected charges connectedto a sink may cause the antenna violation, the connected com-ponents which contain at least one sink are extracted from G,and the total antenna weight WCi of each extracted connectedcomponent Ci is then computed. If WCi > Lmax, the collectedcharges of Ci exceed the antenna threshold, and three casesneed to be checked (see lines 7–8 and an illustration in Fig. 4).

Case 1) Ci is connected to a source node [Fig. 4(a)]. If theconnected component Ci is connected to a sourcenode, the collected charges of Ci can be dischargedthrough the diffusion terminal, and thus, no antennaviolation will occur.

Case 2) Ci is not connected to any source nodes but is con-nected to another VWS [Fig. 4(b)]. For this case, ifthe connected VWS is fixed by diode insertion, thecollected charges of Ci can be discharged throughthe inserted diode and, thus, will not cause any

Fig. 5. WVD algorithm.

antenna violations. However, if the connected VWSis fixed by jumper insertion, the collected chargesmay still cause the antenna violation, since jumperinsertion will not create any discharging paths. Inthis phase, the case discussed here is treated asantenna-safe segments, and an enhanced techniqueis applied to solve this case in the second phase.

Case 3) Ci is not connected to any source nodes or anyother VWSs [Fig. 4(c)]. In this case, the collectedcharges would damage the gate terminals, and thus,an antenna violation is identified. The connectedcomponent Ci is classified as a VWS and is addedinto Sviol.

We have the following theorem for the time complexity ofour WVD algorithm.Theorem 1: The time complexity of the WVD algorithm is

O(|T |2 · nlayer), where |T | is the total number of segments forthe given topology T and nlayer is the number of layers.

Proof: As shown in Fig. 5, lines 1–2 take constant time.For the loop between lines 3 and 10, line 4 spends at mostO(|T |2) time to add all segments into G. The inner loop (lines5–9) needs O(|T |) time since every segment is checked at mostonce to compute the corresponding antenna weight WCi. Sincethe loop between lines 3 and 10 executes nlayer times, we canconclude that the time complexity of the WVD algorithm isO(|T |2 · nlayer).

B. SDJI

In this phase, we fix every VWS identified in the first phaseby SDJI with the minimum cost. Since the optimal jumperinsertion solution for a VWS can be computed by the BUJIOalgorithm [16], [17], we make use of the optimal solution ofeach VWS to minimize the cost induced by antenna fixing.

Inspired by the DIRMCF algorithm [7], [8], we also considerthe jumper cost in the flow network, and thus, the jumper costsand the extension wire costs (for diodes) can be handled at the


Fig. 6. Example to consider diodes and jumpers at the same time. A jumperedge is added for each VWS node, and the jumper cost is modeled as the edgecost.

Fig. 7. Example to illustrate the interaction between diode and jumper inser-tions. (a) All VWSs are fixed by diode insertion. The charges on the remainderof the net can be discharged through the inserted diodes. (b) All VWSs are fixedby jumper insertion. The charges on the remainder of the net may still cause theantenna effect.

same time. For every VWS identified in the first phase, theBUJIO algorithm is applied to compute the number of jumpersmJ needed to fix the antenna violation. The jumper cost iscalculated by β × mJ . Then, we add a jumper edge for eachVWS to model the jumper cost. Consider the example shownin Fig. 6 with two VWSs, which are represented by the VWSnodes vs1 and vs2. The edges with unit capacity and zero costare constructed from vs1 and vs2 to the routing grids, andthus, the resulting flow which goes through the routing gridsdetermines the diode positions and the routing of extensionwires connected to the protected VWS. Integrating the jumpercosts into the flow network, one jumper edge with unit capacityis added from each VWS node to the sink of the network.The costs of the jumper edges are assigned to the optimaljumper costs computed by the BUJIO algorithm. Instead ofgoing through the routing grids, the resulting flow now canalternately go through the jumper edge, which means that lowercosts can be achieved if the corresponding VWS is fixed byjumper insertion.

However, even if the preceding algorithm is applied, someantenna violations may remain in the routing topology. Consid-ering the example shown in Fig. 7, the tree representation ofa net contains two identified VWSs. As mentioned in Case 2)of Section III-A, for a given net N , if at least one of thecontained VWSs is fixed by diode insertion [see Fig. 7(a)],the collected charges of the remainder of N can be dischargedthrough the inserted diodes, and thus, no antenna violationremains. In contrast, if all the contained VWSs of N are fixed

Fig. 8. Flow network to handle the extra jumper costs. A penalty node vp,a free edge, and a penalty edge are added for each net. The extra cost δN ismodeled as the edge cost of the penalty edge.

by jumper insertion [see Fig. 7(b)], no discharging path iscreated, and thus, some antenna violation may remain on N ifthe collected charges of the remainder of N exceed the antennathreshold Lmax. Through this example, it is obvious that anextra jumper cost δN is needed for the remainder of N when allthe contained VWSs are fixed by jumper insertion. Consider anet N with m identified VWSs. We define cJ(N) as the optimaljumper cost for fixing net N , and cJ(x) as that for fixing aVWS, x. The extra cost δN for net N can be computed byδN = cJ(N) − (

∑mi=1 cJ(xi)).

In the SDJI algorithm, the extra cost δN should be added intothe fixing cost when all the contained VWSs of net N are fixedby jumper insertion. To achieve this objective, a penalty nodevp is constructed for each net. Considering the example shownin Fig. 8, the flow network models a net N with m = 2 VWSs,represented by vs1 and vs2. The jumper edges are connected tovp instead of the sink of the flow network. Two edges, a freeedge and a penalty edge, are connected from vp to the sink ofthe network. For the free edge, the capacity is m − 1 and thecost is zero. For the penalty edge, the capacity is one, and thecost is δN for net N . With this flow network, if the resultingflow finds fewer than m VWSs to be fixed by jumper insertion,no extra cost will be induced. If the resulting flow finds exactlym VWSs to be fixed by jumper insertion, however, the extracost δN will be induced.

C. Overall Design Flow

Given the routing topology T , the antenna threshold Lmax,and a set of diode insertion positions D, the ASDJI problem canbe solved by the design flow shown in Fig. 9. First, for the givenT and Lmax, the VWSs can be identified by the WVD algorithmproposed in Section III-A. Second, the optimal jumper positionsand costs to fix each VWS and the extra costs δN for each net Nare computed by the BUJIO algorithm. Then, the flow networkG(V,E) is constructed as follows.

1) Construct a flow source, a flow sink, a representing nodevs for each VWS, and a grid node for each routing gridpoint. The grid nodes can be categorized into three types:vx represents the grid point occupied by a violating wire;vd represents the grid point feasible for diode insertion;and vf represents the other grid point not occupied bythe routed segments or routing blockages. The capacityof each grid node is equal to one.


Fig. 9. Overall design flow.

Fig. 10. Modeling the grid node capacity.

2) For each net containing at least one VWS, construct apenalty node vp.

3) Construct the grid edges (vxi,vfj

), (vfi, vfj

), and (vfi,

vdj) between neighboring grid points. These edges repre-

sent all the possible routing directions of extension wires.All the grid edge capacities are equal to one, and allthe costs are equal to the distance between the two gridpoints.

4) Construct the edges (source, vsi), (vsi

, vsj), and (vdi

,sink). All the edge capacities are equal to one, and allthe costs are equal to zero.

5) Construct the jumper edges from each vsito the cor-

responding vpiwith unit capacity and corresponding

jumper cost. The free edge and the penalty edge fromvpi

to the flow sink are constructed as described inSection III-B.

In particular, the capacity of a grid node (in step 1) can bemodeled as in the example shown in Fig. 10. For a grid nodevg , we decompose it into two nodes, v′

g and v′′g , and connect

from v′g to v′′

g . All incoming edges of vg are now connected tov′

g , and all outgoing edges are connected from v′′g . The cost and

capacity of the edge between v′g and v′′

g are set to zero and one,respectively. By this model, we can ensure that no more thanone extension wire will go through vg , and thus, the extensionwires will not cross each other.

After constructing the flow network G, the optimal antennafixing result can be determined by the minimum-cost network-flow algorithm. The diode and jumper positions can be ex-tracted by checking the resulting flows on the edges (vsi

, vpi)

and (vdi, sink). The extension wire routing can be extracted by

checking the flows on the grid edges. The antenna fixing resultwith SDJI can be concluded in the following theorem.Theorem 2: For a routing topology T with m identified

VWSs, if the value of the resulting flow f of the SDJI algorithmis equal to m, all the antenna violations can be fixed with theminimum cost. In contrast, if the value of the resulting flow fis less than m, no feasible solution exists to completely fix theantenna effect in T by SDJI.

For modern VLSI designs, there are two commonly useddesign rules for antenna violation checking, namely, partialantenna ratio (PAR) and cumulative antenna ratio (CAR) [2],[18]. The antenna ratio is defined as the antenna area dividedby the connected gate area. The difference between PAR andCAR is that PAR considers antenna damage to gates on onlyone layer, whereas CAR accumulates the effect to gates fromeach metallization step [2]. Since the proposed WVD algorithmanalyzes the intermediate topologies between the metallizationsteps, our algorithm can easily handle the CAR by treating itas the antenna upper bound. Furthermore, our algorithm canalso handle the PAR problem with minor modifications for ourdesign flow. For example, if we consider PAR on metal layer 3,we first group the gates and the connected metal wires onmetal layers 1 and 2 as pseudogates. Then, applying the WVDalgorithm, we set the antenna upper bound to the given PARand perform the loop between lines 3 and 10, as shown inFig. 5, only once on metal layer 3. Therefore, the VWSs aredetected according to the given PAR. We can finally ungroupall pseudogates and apply the SDJI algorithm to fix all antennaviolations with the PAR consideration as well.

We have the following theorem for the time complexity ofour SDJI algorithm.Theorem 3: The time complexity of the SDJI algorithm

is O(V E lg(V 2/E)lg(V )), where V is the number of gridpoints and E is the number of edges among grid points.

Proof: The time complexity for BUJIO to compute thejumper positions for each VWS is O((V ′ + D)lgD) in [16]and [17], where D is the number of jumper obstacles andV ′ is the number of tree nodes in the tree representation ofthe VWS. In a grid-based routing model, the number of treenodes and the number of obstacle points are smaller than thatof grid points. Let V be the number of grid points in thegiven routing topology. The time complexity can be rewritten asO(V lgV ) since V ′ = O(V ) and D = O(V ). The constructionsteps of the flow network can be performed in O(E) time,and solving the minimum-cost network-flow problem requiresO(V E lg(V 2/E)lg(V )) time [3]. Therefore, the time com-plexity of the SDJI algorithm is dominated by the minimum-cost network-flow algorithm.

D. Flow Network Pruning Technique

In the constructed flow network, the jumper cost is the costupper bound to fix a VWS, and thus, it can be used to reducethe search space of the minimum-cost network-flow problem.Evaluating the worst case of jumper insertion, the cost upperbound δ̂s for a VWS s of net N can be computed by

δ̂s = δN + cJ(s) (2)

where δN is the extra jumper cost of the net N and cJ(s) isthe optimal jumper cost for fixing s. With this upper bound, wehave the following theorem.Theorem 4: For every grid node v in the flow network

G(V,E) of SDJI, if the distance from v to every VWS s islarger than the corresponding δ̂s, v can be pruned without lossof the solution optimality for the ASDJI problem.


Fig. 11. Illustration of the proposed algorithm: (a) The given routing topology. (b) Calculation of the jumper cost for each VWS and the extra jumper penalty.(c) The constructed network graph and the resulting flow. The grid nodes are extracted from the grid points in layer 1 of figure (a). (d) The resulting layoutby SDJI.

Proof: For a VWS s, with its representing node vs, of thenet N , we will connect vs to a penalty node through a jumperedge and grid nodes through grid edges during the constructionof the flow network G. Thus, for a resulting flow that enters vs,it must leave vs through either the connected jumper edge orgrid edges. If the resulting flow goes through the jumper edge,the largest possible cost is δ̂s = δN + cJ(s) since the flow maygo through both the jumper edge (cost cJ (s)) and the penaltyedge (cost δN ). That means, for a grid node v, if the distancefrom vs to v is larger than δ̂s, the flow that enters vs will resultin a larger cost if it goes to the grid node v rather than leavevs through the jumper edge. Since the SDJI algorithm finds theminimum-cost network-flow on G, the optimal flow that entersvs will not go through v since it can easily choose to go throughthe jumper edge and get a smaller cost. In other words, if thedistance from v to every VWS s is larger than the correspondingδ̂s, we can remove v and all its connected edges from G sinceno optimal flow will go through v.

E. Complete Example

Fig. 11 shows an example to illustrate the overall design. Weassume that both a jumper and a unit-length extension wireinduce one unit delay. Consider the given routing topologywith exactly one net in Fig. 11(a) and the tree representationin Fig. 11(b). Applying the WVD algorithm, two VWSs areidentified. By the BUJIO algorithm, each VWS needs onejumper to fix the antenna violation, and thus, both the costs ofthe jumper edges are set to one. The number of jumpers neededto fix the whole routing tree is three, and the extra jumper costδN is equal to one. In Fig. 11(c), to construct the flow network,

TABLE IMCNC BENCHMARK STATISTICS

the grid nodes and edges are first extracted from the grid pointsin layer 1 of Fig. 11(a). Then, the jumper edges are constructedfor each VWS, and the penalty nodes, the penalty edges, andthe free edges are constructed for each net. Since the number ofVWSs in the given net is two, both the capacities of the penaltyedge and the free edge are set to one, and the cost of the penaltyedge is set to δN = 1. After we construct the flow network, theminimum-cost network-flow algorithm is applied, and boththe value and the cost of the resulting flow are equal to two.The optimal fixing solution is finally shown in Fig. 11(d).

IV. EXPERIMENTAL RESULTS

The proposed algorithm was implemented in the C++ lan-guage on a 1.2-GHz SUN Blade 2000 machine with 8-GBmemory.

The statistics of the benchmark circuits are listed in Table I.Six test cases are chosen from the MCNC benchmarks sinceonly these test cases record the source and sink information foreach net. The column “Circuit” denotes the circuit name, “Size”denotes the circuit dimension, “# Layers” denotes the numberof routing layers, “# Nets” denotes the number of nets, and “#Pins” denotes the number of pins.


TABLE IICOMPARISON WITH BUJIO

TABLE IIICOMPARISON WITH DIRMCF FOR THE 80% DIODE BLOCKAGE RATE

The minimum-cost network-flow solver used is LEDA 4.1[1]. The input routing results of the test cases were taken fromthe multilevel routing results [10]. According to the TSMC0.25-µm technology file, the jumper-to-wire ratio β in (1) wasset to 15 for all the experiments. The antenna threshold Lmax

set in [6] is 100 µm, and in our experiments, 50 and 100 µmwere both tested. To reflect modern design complexity, werandomly increase the diode blockage rate of each circuit to80%, 85%, 90%, and 95%. We compared our work with thejumper insertion algorithm BUJIO [16], [17] and the diodeinsertion algorithm DIRMCF [7], [8]. We integrated both workswith our WVD algorithm to identify the antenna VWSs. Theexperimental results show that our work achieves very highantenna violation fixing rates even in high-density circuits. Wealso performed several experiments to analyze the empiricalruntime and induced delays of our algorithm and the effective-ness of the pruning technique proposed in Theorem 4.

A. Effectiveness of SDJI Algorithm

Table II gives the comparison of the antenna violation fixingrates between BUJIO and our work. Columns 1, 2, and 3 givethe circuit name of each test case, the antenna threshold Lmax,and the numbers of antenna violations, respectively. Columns4, 7, 10, 13, and 16 give the numbers of fixed antenna violation;columns 5, 8, 11, 14, and 17 give the fixing rates; and columns6, 9, 12, 15, and 18 give the fixing costs of BUJIO and our

work with different diode blockage rates. Note that for jumperinsertion alone, the diode blockage rate would not influencethe fixing result since jumper insertion only consumes thefree spaces in the routing layers above the violating wires.The fixing rate is calculated by (# fixed antenna violations)/(# antenna violations). It is not surprising that BUJIO achievesonly 63.38% fixing rate on average, since the routing layouts areusually too dense to find feasible jumper positions. In contrast,our work achieves more than 99.6% fixing rate even with the95% diode blockage rate. It should also be noted that the fixingcosts of BUJIO and our work cannot be compared directly sinceBIJIO usually fixes significantly fewer antenna violations thanour work.

Tables III and IV give the comparison of the antenna-fixingresults between DIRMCF and our work in 80% and 90% diodeblockage rates, respectively. In the tables, column “# diodes”gives the numbers of diodes used to fix the antenna violations,column “E. Wire Cost” gives the total length of extensionwires, and column “Jumper Cost” gives the jumper cost to fixthe antenna violations, which is calculated by β× (number ofjumpers used). Column “Total Cost” gives the cost to fix theantenna violations, which is the summation of the jumper costand the extension wire cost. Note that the total cost in DIRMCFis equal to the extension wire cost. Column “CPU Time” givesthe runtime for both algorithms.

As shown in the table, our work completely fixes all an-tenna violations for all test cases except for “s38417,” whereas


TABLE IVCOMPARISON WITH DIRMCF FOR THE 90% DIODE BLOCKAGE RATE

TABLE VAVERAGE FIXING RATE COMPARISON WITH DIRMCF

Fig. 12. Diode and jumper insertion result of our algorithm for “s15850.”The inserted diodes and jumpers are highlighted by orange squares and pinktriangles, respectively.

DIRMCF cannot for most cases. For those cases with the100% fixing rate, our work always achieves lower fixing costthan DIRMCF. Table V summarizes the average fixing rates ofDIRMCF and our work for 80%, 85%, 90%, and 95% diodeblockage rates. Column “Fixing Rate 80” gives the averagefixing rates with the 80% diode blockage rate, and so on. It isnatural that the fixing rate of both works decreases as the diodeblockage rate increases since less space is available for diodeinsertion. The results show that our work consistently achievesvery high fixing rates at more than 99.69% even for 95% diodeblockage rate, whereas the average fixing rate of DIRMCFdecreases to 94.04% at the same blockage rate. Fig. 12 showsthe diode and jumper insertion result of our algorithm for“s15850.”

B. Empirical Runtime Analysis

Fig. 13 shows the empirical runtime trend of our program.First, the runtimes were derived from all test cases with the80% blockage rate and the 50-µm antenna upper bound. Then,

Fig. 13. Runtime is plotted as a function of chip sizes for the 80% block-age rate.

we applied the regression analysis based on the least-squaremethod to derive the relationship between the runtimes andchip sizes. We found that the empirical time complexity of ourprogram is about O(n1.937) to the chip size n, which is muchlower than the theoretical bound shown in Theorem 3.

C. Net Delay Impact

Table VI summarizes the delay penalty rates of antennaviolating nets due to the antenna fixing. The delay penalty rateis computed by the increased delay over the original net delay.Columns 2, 3, and 4 give the maximum, minimum, and averagedelay penalty rates of all test cases with the 80% blockage rateand the 50-µm antenna upper bound, whereas columns 5, 6, and7 give those with the 90% blockage rate. As shown in the table,fixing antenna violations by the SDJI algorithm resulted in onlyabout 1% average delay penalty with the 80% blockage rates.If the blockage rate increases to 90%, the average delay penaltyalso increases to about 3% since the resources for antenna fixingare reduced. It should be noted that the minimum delay penaltyof all test cases is zero. The reason is that, in most situations,


TABLE VIDELAY PENALTIES FOR ANTENNA FIXING

TABLE VIIEXPERIMENT ON THE EFFECTIVENESS OF THE PRUNING TECHNIQUE

the inserted diode or jumper might be located on a noncriticalpath, and thus, it will not increase the critical-path delay, or ithas only an insignificant impact.

D. Effectiveness of the Pruning Technique

In Table VII, we compare the CPU times and memoryusages of the SDJI algorithm without and with the pruningtechnique proposed in Theorem 4. The experimental data wereobtained from all test cases with the 80% blockage rate andthe 50-µm antenna upper bound. Note that the CPU times andmemory usages for “s38417” and “s38584” without the pruningare not available since they need more than 4-GB memory,which exceeds the limitation of our 32-b machine. As shownin the table, pruning unnecessary nodes and edges in the flownetwork can reduce about 95% memory of the SDJI algorithmon average. Furthermore, due to the decrease of nodes andedges, the SDJI algorithm can also save about 91% CPU timeon average to fix antenna violations. This experiment has shownthat the proposed pruning technique is effective and necessaryfor solving the ASDJI problem.

V. CONCLUSION

We have proposed an optimal algorithm to solve the ASDJIproblem. Our algorithm guarantees to find the optimal antennafixing solution with diode/jumper insertion if such a solutionexists. The experimental results have shown that our workachieves higher fixing rates and lower delay costs even for high-density circuits compared with the state-of-the-art previousworks.

REFERENCES

[1] The LEDA Package. [Online]. Available: http://www.mpi-sb.mpg.de/LEDA/

[2] LEF/DEF 5.5 language reference.[3] R. K. Ahuja, T. L. Magnanti, and J. B. Orlin, Network Flows. Englewood

Cliffs, NJ: Prentice-Hall, 1993.

[4] Y.-W. Chang and S.-P. Lin, “MR: A new framework for multilevel full-chip routing,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.,vol. 23, no. 5, pp. 793–800, May 2004.

[5] P. H. Chen, S. Malkani, C.-M. Peng, and J. Lin, “Fixing antenna problemby dynamic diode dropping and jumper insertion,” in Proc. IEEE Int.Symp. Quality Electron. Des., Mar. 2000, pp. 275–282.

[6] T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, “Multilevel routing with antennaavoidance,” in Proc. ACM Int. Symp. Phys. Des., Apr. 2004, pp. 34–40.

[7] L.-D. Huang, X. Tang, H. Xiang, D. F. Wong, and I.-M. Liu, “Apolynomial time optimal diode insertion/routing algorithm for fixingantenna problem,” in Proc. ACM/IEEE Des. Autom. Test Eur., Mar. 2002,pp. 470–475.

[8] L.-D. Huang, X. Tang, H. Xiang, D. F. Wong, and I.-M. Liu, “A poly-nomial time-optimal diode insertion/routing algorithm for fixing antennaproblem,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.,vol. 23, no. 1, pp. 141–147, Jan. 2004.

[9] Z.-W. Jiang and Y.-W. Chang, “An optimal simultaneous diode/jumperinsertion algorithm for antenna fixing,” in Proc. IEEE/ACM Int. Conf.Comput.-Aided Des., Nov. 2006, pp. 669–674.

[10] S.-P. Lin and Y.-W. Chang, “A novel framework for multilevel routingconsidering routability and performance,” in Proc. IEEE/ACM Int. Conf.Comput.-Aided Des., Nov. 2002, pp. 44–50.

[11] W. Maly, C. Ouyang, S. Ghosh, and S. Maturi, “Detection of an antennaeffect in VLSI designs,” in Proc. IEEE Int. Defect Fault Tolerance VLSISyst., Nov. 1996, pp. 86–94.

[12] H. Shirota, T. Sadakane, and M. Terai, “A new rip-up and reroute al-gorithm for very large scale gate arrays,” in Proc. IEEE Custom Integr.Circuit Conf., May 1996, pp. 171–174.

[13] H. Shirota, T. Sadakane, M. Terai, and K. Okazaki, “A new router forreducing ‘antenna effect’ in ASIC design,” in Proc. IEEE Custom Integr.Circuit Conf., May 1998, pp. 601–604.

[14] B.-Y. Su and Y.-W. Chang, “An exact jumper insertion algorithm forantenna effect avoidance/fixing,” in Proc. ACM/IEEE Des. Autom. Conf.,Jun. 2005, pp. 597–602.

[15] B.-Y. Su and Y.-W. Chang, “An optimal jumper-insertion algorithm forantenna avoidance/fixing,” IEEE Trans. Comput.-Aided Design Integr.Circuits Syst., vol. 26, no. 10, pp. 1818–1829, Oct. 2007.

[16] B.-Y. Su, Y.-W. Chang, and J. Hu, “An optimal jumper insertion algorithmfor antenna avoidance/fixing on general routing trees with obstacles,” inProc. ACM Int. Symp. Phys. Des., Apr. 2006, pp. 56–63.

[17] B.-Y. Su, Y.-W. Chang, and J. Hu, “An exact jumper-insertion algorithmfor antenna violation avoidance/fixing considering routing obstacles,”IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 4,pp. 719–734, Apr. 2007.

[18] D. Wu, J. Hu, and R. Mahapatra, “Antenna avoidance in layer assign-ment,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25,no. 4, pp. 734–738, Apr. 2006.

Zhe-Wei Jiang (S’05) received the B.S. degreein electronics engineering from the National ChiaoTung University, Hsinchu, Taiwan, in 2003. He iscurrently working toward the Ph.D. degree at theGraduate Institute of Electronics Engineering, Na-tional Taiwan University, Taipei, Taiwan.

His current research interests focus on large-scale mixed-size placement and design formanufacturability.


Yao-Wen Chang (S’94–M’96) received the B.S.degree from National Taiwan University, Taipei,Taiwan, in 1988, and the M.S. and Ph.D. degreesfrom the University of Texas at Austin in 1993 and1996, respectively, all in computer science.

He is a Professor in the Department of ElectricalEngineering and the Graduate Institute of Electron-ics Engineering, National Taiwan University. He iscurrently also a Visiting Professor at Waseda Uni-versity, Kitakyushu, Japan. He was with the IBMT. J. Watson Research Center, Yorktown Heights,

NY, in the summer of 1994. From 1996 to 2001, he was on the faculty ofNational Chiao Tung University, Taiwan. His current research interests includeVLSI physical design, design for manufacturability and reliability, designautomation for biochips, and FPGA. He has been working closely with industryon projects in these areas. He has coauthored one book on routing and over 130ACM/IEEE conference/journal papers in these areas.

Dr. Chang received an award at the 2006 ACM ISPD Placement Contest,Best Paper Awards at ICCD-95 and the 2007 VLSI Design/CAD Sympo-sium, and 11 Best Paper Award Nominations from DAC (2000, 2005, 2007,2008), ICCAD (2002, 2007), ISPD (two in 2007), ACM TODAES (2003),ASP-DAC (2004), and ICCD (2001). He has received many awards for re-search, such as the 2007 Distinguished Research Award, the inaugural 2005First-Class Principal Investigator Award, and the 2004 Dr.Wu Ta You MemorialAward from the National Science Council of Taiwan, the 2004 MXIC YoungChair Professorship from the MXIC Corporation, and for excellent teachingfrom National Taiwan University (2004, 2006, 2007) and National ChiaoTung University (2000). He is currently an Associate Editor of the IEEETRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS

AND SYSTEMS (TCAD) and an editor of the Journal of Information Sci-ence and Engineering (JISE). He currently serves on the ICCAD ExecutiveCommittee, the ACM/SIGDA Physical Design Technical Committee, and theISPD Organizing Committee and has served on the technical program commit-tees of ASP-DAC (topic chair), DAC, DATE, FPL, FPT (program co-chair),GLSVLSI, ICCAD, ICCD, IECON (topic chair), ISPD, SOCC (topic chair),TENCON, and VLSI-DAT (topic chair). He is currently an independent boarddirector of Genesys Logic, Inc., a member of the board of governors of theTaiwan IC Design Society, and a member of the IEEE Circuits and SystemsSociety, ACM, and ACM/SIGDA.

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