Zero-Current Transition Interleaved Boost Converter

Mahdi Rezvanyvardom, Ehsan Adib, Member, IEEE and Hosein Farzanehfard, Member, IEEE

Department of Electrical and Computer Engineering Isfahan University of Technology

Isfahan, Iran m.rezvanyvardom@ec.iut.ac.ir, e.adib@cc.iut.ac.ir and hosein@cc.iut.ac.ir

Abstract— In this paper, a new ZCS PWM auxiliary circuit for the interleaved boost converter is introduced which uses only one auxiliary switch to provide soft-switching condition. In the proposed interleaved converter, soft switching is obtained for all semiconductor devices. The main and auxiliary switches turn on and off under zero-current condition. Thus, the reverse-recovery losses of boost diodes are reduced and also, high efficiency is achieved due to reduction of switching losses. In addition, the proposed circuit is controlled by pulse-width modulation (PWM) method. The converter is analyzed and the design procedure is discussed. Simulation results are presented to verify the validity of theoretical analysis.

Keywords- Interleaved boost converter, soft switching, zero-current switching, zero-voltage switching.

I. INTRODUCTION The boost converter is widely employed in industrial applications. Most renewable power sources, such as fuel cell and solar-cells provide low and unregulated output voltage and their voltage should be boosted and regulated using current fed converters. As power rating increases, it is required to connect converters in parallel to provide the output power [1], [2]. The interleaved structure is used in high-current and high-power applications due to its advantages such as power distribution, fast transient response and reduction of passive component size and current ripple [3]-[6]. Also, interleaved connection of converters reduces switching loss which will result in higher efficiency. Nowadays, in order to obtain soft-switching condition for current-fed converters, Zero-Current Switching (ZCS) PWM and Zero-Voltage Switching (ZVS) PWM techniques are vastly applied. These techniques provide soft switching condition while the control circuit remains PWM. By using these techniques, switching losses and electromagnetic interferences (EMI) are reduced. Therefore, switching frequency can be increased which results in reduction of converter volume and weight [7]-[9] and also increases power handling capability. ZVS technique is a proper technique when MOSFET switches are used to reduce capacitive turn on losses as well as switching losses [10]-[12]. For higher power applications where Isolated-Gate Bipolar Transistor (IGBT) switches are used due to their lower conduction losses and cost, ZCS techniques are preferred to eliminate tailing current losses. Several interleaved ZCS PWM converters are introduced in [13]-[16]. In [13] and [15], two auxiliary switches are used to provide soft switching conditions. In [16], the main switches are turned on under the ZCS condition, but are turned off under hard switching condition. In this paper a new interleaved ZCS

Fig. 1. Proposed interleaved ZCS boost converter.

PWM converter is introduced which uses only one auxiliary switch. Furthermore, in this converter the current stresses of the main switches are low. Fig.1 shows proposed interleaved ZCS boost converter. The main converter is composed of D1, D2, S1 and S2. The auxiliary circuit is composed of Sa, Lr, Cr, Ls1, Ls2, Dp1 and Dp2. The intrinsic anti-parallel diodes of main switches are Ds1 and Ds2. The output capacitance and load resistance are Co and Ro respectively. The proposed converter operates like a conventional interleaved boost converter except during switching instants. Lr, Ls1, Ls2 and Cr are resonant components, while Sa controls the resonant instant. Auxiliary switch Sa is a unidirectional switch while main switches are bidirectional switches.

II. PROPOSED ZCS PWM SWITCH CELL TOPOLOGY FOR INTERLEAVED BOOST CONVERTERS

In order to simplify the converter analysis, the following assumptions are considered: 1- Output capacitor is large enough so that it can be replaced by a DC voltage source. 2- Inductances L1 and L2 are equal (L1=L2). 3- All semiconductor devices are ideal. The converter operation consists of two symmetrical half cycles during each switching period. Therefore, only half the switching cycle is explained. In addition, it is assumed that converter operates at steady state. Converter operation in half the switching cycle can be divided into nine modes. The equivalent circuit for each operating mode and theoretical waveforms are illustrated in Fig. 2 and Fig. 3 respectively.

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Fig.2. (a) Mode 1.

Fig.2. (d) Mode 4.

Fig.2. (c) Mode 3.

Fig.2. (b) Mode 2.

Fig.2. (g) Mode 7.

Fig.2. (h) Mode 8.

Fig.2. (i) Mode 9.

Fig.2. (f) Mode 6.

Fig.2. (e) Mode 5.

Fig.2. Equivalent circuit of each operating mode: (a) Mode 1, (b) Mode 2, (c) Mode 3, (d) Mode 4, (e) Mode 5, (f) Mode 6, (g) Mode 7, (h) Mode 8, and (i) Mode 9.

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Fig. 3. Theoretical waveforms of the proposed interleaved converter.

Before the first mode, the main switch S1 and auxiliary switch Sa are off. Main switch S2 is on and inductor L2 is being charged. Also, D1 is conducting and Cr is charged to Vo. Mode 1: [t0 − t1] [Fig. 2(a)] This mode begins by turning S1 on. Due to L1 and Ls1, the main switch S1 is turned on under ZCS condition. Therefore, the current flowing through S1 increases linearly to L1 current (Iin) and Ls1 current decreases linearly from Iin to zero. At the end of this mode switch S1 current and Ls1 current are Iin and zero respectively. Duration of this mode is

0

101 V

ILtt ins=− (1)

Mode 2: [t1 − t2] [Fig. 2(b)] At t1, current of resonant inductance Ls1 becomes zero. In this mode S1 and S2 are on and L1 and L2 are being charged. Mode 3: [t2 − t3] [Fig. 2(c)] In this mode, Sa is turned on in order to provide soft-switching for S2 turn off. By turning Sa on, a resonance starts between Lr and Cr. Due to Lr, Sa turn on is under ZCS condition. This mode ends when the voltage of Cr reaches zero. Duration of this mode is

223rTtt =− (2)

The current through the auxiliary switch is obtained as following

))(sin()( 211

ttZV

tI oSa −= ω (3)

Where rrCL11 =ω , rr CLZ =1 and rrr CLT π2=

Mode 4: [t3 − t4] [Fig. 2(d)] At t2, diodes Dp1 and Dp2 begin to conduct as Cr voltage goes negative and resonance continues between Cr, Lr, Ls1 and Ls2. The current through the main and auxiliary switches decrease. This mode ends when the current through the main switches reach zero.

))](cos(1[)()( 311

21 ttZV

LL

ItItI eqo

S

eqinSS −−⋅−== ω (4)

))](cos(1[)( 311

ttZV

LL

ZV

tI eqo

r

eqoSa −−⋅−= ω (5)

Where

reqeq CL1=ω and rSSeq LLLL 21=

Since Dp1 and Dp2 are conducting, the voltage across D1 and D2 increase as VCr decreases. Mode 5: [t4 − t5] [Fig. 2(e)] At t4, the currents through main switches S1 and S2 reach zero and tries to go negative. Thus, anti-parallel diodes Ds1 and Ds2 begin to conduct. This mode ends when the current through auxiliary switch Sa reaches zero at t5. Mode 6: [t5 − t6] [Fig. 2(f)] At t5, the current of auxiliary switch reaches zero. Thus, auxiliary switch Sa turns off under ZCS condition. Sum of the Dp1 and Dp2 currents run through Cr, therefore, the voltage of Cr increases. At the end of this mode the anti-parallel diodes Ds1 and Ds2 turn off. During this mode, S2 can be turned off under ZCS condition. Mode 7: [t6 − t7] [Fig. 2(g)] At t6, the anti-parallel diodes Ds1 and Ds2 turn off. In this mode, the current through Ls2 and Dp2 is constant and equal to Iin. The resonance between Ls1 and Cr continues and the current through Ls1 and Dp1 decreases as, the current in the main switch S1 increases. At the end of this mode the current through Ls1 and Dp1 reaches zero and S1 current reaches Iin.

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Fig. 4. Current of input inductors L1, L2 and their sum. Current scale is 2 A/div.

Fig. 5. Current and voltage of the main switch S2. Voltage scale is 100V/div and current scale is 6.6 A/div.

Fig. 6. Current and voltage of the auxiliary switch Sa. Voltage scale is 100V/div and current scale is 3.4 A/div.

Mode 8: [t7 − t8] [Fig. 2(h)] In this mode Cr is charged by the constant current Iin through Ls2 and Dp2. This mode ends when Cr voltage reaches Vo. Mode 9: [t8 − t9] [Fig. 2(i)] Vo, the current and voltage of Dp2 remain zero. In this mode the proposed converter behaves like a regular interleaved PWM boost converter.

III. DESIGN CONSIDRATIONS This section presents design considerations for the proposed converter. Snubber Inductors LS1 and LS2 are the turn on snubbers of S1 and S2. Also Lr is the turn on snubber of Sa. The mentioned snubber inductors can be designed according to the following equations:

in

rss I

tVLL 021 ≥= (6)

1

0

0

ZV

tVL rr ≥ (7)

Where tr is the rise time of switch current and can be obtained from the switch datasheet. In order to provide zero current switching for main switches, the following equation should be satisfied which results to minimum value for Cr.

ino

S

eq IZV

LL

≥⋅11

(8)

The inductance values of L1 and L2 and capacitance value of Co can be obtained exactly like a conventional PWM converter [18].

IV. SIMULATION RESULTS The proposed ZCS interleaved boost converter is simulated by PSPICE for output power of 500W, input voltage of 100VDC and output voltage of 320VDC operating at 100 kHz. According to design procedure section, the circuit elements are calculated as: Lr =1 μH, Ls1=2 μH, Ls2=2 μH, Cr = 8 nF, L1 = L2 = 300 μH, and CO = 100 μF. Fig. 4 shows current of input inductors L1, L2 and their sum. Fig. 5 and Fig. 6 show current and voltage of the main switch S2 and auxiliary switch Sa respectively. Fig. 7 shows voltage of resonant capacitor Cr. Dashed and continuous lines represents current and voltage waveforms respectively. According to SPICE simulation results, efficiency of the proposed interleaved converter is improved by about 3.1% with respect to hard-switching counterpart.

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Fig. 7. Voltage of resonant capacitor Cr. Voltage scale is 200 V/div.

V. CONCLUSION In this paper a new interleaved ZCS PWM boost converter is introduced. This converter uses only one auxiliary switch to provide soft-switching condition for all semiconductor devices. This converter has higher efficiency than the conventional PWM hard-switching converter due to reduced switching losses. According to SPICE simulation results, due to reduced circuit element stresses, efficiency of the proposed interleaved converter is improved by about 3.1% with respect to hard-switching counterpart. This converter is analyzed and design procedure is presented.

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