IEEE Std 1581 is published … Now what? 2011 Board Test Workshop Heiko Ehrenberg.
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Transcript of IEEE Std 1581 is published … Now what? 2011 Board Test Workshop Heiko Ehrenberg.
![Page 1: IEEE Std 1581 is published … Now what? 2011 Board Test Workshop Heiko Ehrenberg.](https://reader036.fdocuments.in/reader036/viewer/2022082422/56649dc75503460f94abcd32/html5/thumbnails/1.jpg)
IEEE Std 1581 is published …Now what?
2011 Board Test Workshop
Heiko Ehrenberg
![Page 2: IEEE Std 1581 is published … Now what? 2011 Board Test Workshop Heiko Ehrenberg.](https://reader036.fdocuments.in/reader036/viewer/2022082422/56649dc75503460f94abcd32/html5/thumbnails/2.jpg)
BTW 2011 Slide #2
Key elements in IEEE Std 1581
• Simple test logic implementation for
complex, slave-type devices
• No extra pins required
• No reliance on complex access cycles
• Fast test execution, small test vector set
• Usable with any access methodology
(Boundary scan, functional, ICT)
![Page 3: IEEE Std 1581 is published … Now what? 2011 Board Test Workshop Heiko Ehrenberg.](https://reader036.fdocuments.in/reader036/viewer/2022082422/56649dc75503460f94abcd32/html5/thumbnails/3.jpg)
BTW 2011 Slide #3
Basic conceptPCB
IEEE 1581 device
IEEE 1149.1 device(s)
Memory Cells
CombinationalTest Logic
Memory Controller
Test Control
TTM (optional)
Input
Bus
Output Bus
Optional
Test Pin
(if no TTM)
x
y
![Page 4: IEEE Std 1581 is published … Now what? 2011 Board Test Workshop Heiko Ehrenberg.](https://reader036.fdocuments.in/reader036/viewer/2022082422/56649dc75503460f94abcd32/html5/thumbnails/4.jpg)
BTW 2011 Slide #4
Test mode control
• One of seven transparent test mode (TTM)
control methods:– Non-functional stimulus (NFS)
– Designated command codes (DCC)
– Simultaneous input/output (SIO)
– Clock frequency (CKF)
– Analog level (ANL)
– Conditional power-up initiation (CPI)
– Default power-up initiation (DPI)
• or a Dedicated test pin (TPN)
These methods may require additional board-level and/or controlling device DFT to be implemented
Test entry or exit is triggered by a condition on the pins that would otherwise never exist under normal functional conditions
![Page 5: IEEE Std 1581 is published … Now what? 2011 Board Test Workshop Heiko Ehrenberg.](https://reader036.fdocuments.in/reader036/viewer/2022082422/56649dc75503460f94abcd32/html5/thumbnails/5.jpg)
BTW 2011 Slide #5
Test logic
• One of three defined test logic
architectures:– XOR (3-input XOR or XNOR gates)
– IAX (XOR, Inverters, and AND gates)
– XOR-2 (2-input XOR or XNOR gates)
• Or a custom test logic that satisfies rules in
IEEE Std 1581-2011
![Page 6: IEEE Std 1581 is published … Now what? 2011 Board Test Workshop Heiko Ehrenberg.](https://reader036.fdocuments.in/reader036/viewer/2022082422/56649dc75503460f94abcd32/html5/thumbnails/6.jpg)
BTW 2011 Slide #6
Optional test functions
• Optional test functions accessible via
Test Pattern Partitioning (TPP)
• Examples include:– Reading a device identification (ID)– Control line continuity test– Built-in self test (BIST) access– Other public or private commands
![Page 7: IEEE Std 1581 is published … Now what? 2011 Board Test Workshop Heiko Ehrenberg.](https://reader036.fdocuments.in/reader036/viewer/2022082422/56649dc75503460f94abcd32/html5/thumbnails/7.jpg)
BTW 2011 Slide #7
Outlook for IEEE Std 1581
• IEEE Std 1581 approved March 2011 and
published in June 2011
• Working group is considering future work:– Description language– Bi-directional test features– …
![Page 8: IEEE Std 1581 is published … Now what? 2011 Board Test Workshop Heiko Ehrenberg.](https://reader036.fdocuments.in/reader036/viewer/2022082422/56649dc75503460f94abcd32/html5/thumbnails/8.jpg)
BTW 2011 Slide #8
Thank you
For more details and questions, or to join
the working group, contact me:
Heiko Ehrenberg ([email protected])