IEEE Standard 1149.6: Boundary-Scan Testing of Advanced Digital Networks
description
Transcript of IEEE Standard 1149.6: Boundary-Scan Testing of Advanced Digital Networks
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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IEEE Standard 1149.6:Boundary-Scan Testing of Advanced Digital NetworksJ. M. Martins FerreiraFEUP / DEEC - Rua Dr. Roberto Frias4200-537 Porto - PORTUGALTel. 351 225 081 748 / Fax: 351 225 081 443([email protected] / http://www.fe.up.pt/~jmf)
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Outline
• Scope and objectives of 1149.6• AC coupling, differential signalling• 1149.6 defect model• Testing AC-coupled / differential networks
(placement of BS cells, new instructions)• 1149.6: test driver and test receiver • Conclusion
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Scope and objectives
• Scope of 1149.6: Structural test of high-speed digital networks
• Objectives– Cope with differential and/or AC-coupled
interconnections, enabling high fault coverage with minimum impact on mission logic
– Reuse as much as possible IEEE 1149.1 tools (ensure compatibility with 1149.1 / 4)
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AC-coupling, differential signalling
R
011010
Receiver
-
+
Negative
Transmitter
C
Vref
Positive
C
011010
R
• Single-ended signalling with AC-coupling
• Differential signalling with AC-coupling and bias provision
TX:
RX:RTX
ReceiverTransmitter
RX
C
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1149.6 defect modelReceiver
1
Transmitter
1
TX1 RX12
1
-
+
2
1
C
delay
delayReceiverTransmitter 1
C
1
RX2
2
TX2 2
R
1 2
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1149.6 defect model (cont.)Receiver
1
Transmitter
1
TX1 RX12
1
-
+
2
1
C
delay
delayReceiverTransmitter 1
C
1
RX2
2
TX2 2
R
1 2
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Testing AC-coupled / differential networks• BS cell placement has an impact on circuit
performance and defect coverage
• Modified BS cells must ensure:– Signal transmission over AC-coupled nets– Logic level detection from AC test signals
C
Positive
R
R
Receiver
-
+
Transmitter
Vref
C
Negative
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1149.6 drivers and receivers
• An AC testing instruction selects the AC Mode, and a test signal suited for AC-coupled networks is applied to the pin
• A test receiver at the input cell derives logic level information from the incoming AC / DC test signal
U
Mission 0
AC Mode
AC Signal
01
1
Mode
UC
Mode
10
TestReceiver
AC Mode
Mission
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1149.6 instructions for AC-coupled differential networks• EXTEST_PULSE generates a transition
even when the new test value at the driver pin retains its previous value
• EXTEST_TRAIN provides multiple additional transitions (to cope with transient conditions, when necessary)
• Both cause the driver pins to change state at least twice in Run-Test / Idle
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EXTEST_PULSE
Inverted Data ...
... Select-DR
Capture PointAC Pin Driver
...
TAP State
TL Reset
AC Test Signal
Update-XR
...
...
Update Point
...
Data Data
Capture-DR
Pulse Width
TCK
Run-Test / Idle
0
Train / Pulse
Update FF
RTI State
Mode
AC Mode
EXTEST_TRAIN
1
UpdateDRD
CLK
Q
TCK
0
EXTEST_PULSE
1
Train / Pulse
Data
1
AC PinDriver
AC Test SignalD
CLK
Q 0
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EXTEST_TRAIN
TCK
...
Pulse Width
...
Capture-DRSelect-DRTL Reset
Data
Run-Test / Idle
AC Test Signal
Inverted Data
Update Point
...
Pulse Width
Data
Capture Point
Data
Update-XR
AC Pin Driver
...
...
...
TAP State
Inverted Data 0
Train / Pulse
Update FF
RTI State
Mode
AC Mode
EXTEST_TRAIN
1
UpdateDRD
CLK
Q
TCK
0
EXTEST_PULSE
1
Train / Pulse
Data
1
AC PinDriver
AC Test SignalD
CLK
Q 0
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General AC pin driver
0
0
Mode
AC Signal
Mission
U
AC Mode
1
C1
1
Data
1
1
EXTEST_PULSE
X
Mission
EXTEST
0
ShiftDR
AC Mode
Update FF
1
Capture FF
D
CLK
Q
D
CLK
Q
TCK
0
RTI State
BYPASS
D
CLK
Q
0
Train / Pulse
1
0
1
1
Shift Out
0
X
Mode
X
Shift In
Train / Pulse
1
Mode
ClockDR
EXTEST_TRAIN 1
AC Mode
UpdateDR
0
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The test receiver
• Extracts test data even in the presence of an unknown offset
• The solution is to look for valid transitions (with a minimum voltage swing ΔV and a maximum transition time Δt)
• Single-ended signal reception:
UC
Mode
10
TestReceiver
AC Mode
Mission
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Operation of the test receiver
• When an AC testing instruction is loaded, the test receiver detects transitions at the input pin and sends the logic level information to the capture / shift stage of the BS cell
• When the current instruction is EXTEST, the test receiver sends the input logic level to the capture / shift stage of the BS cell
UC
Mode
10
TestReceiver
AC Mode
Mission
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The test receiver : transition detection and offset removal• A delay element and an hysteretic
comparator– Detect input signal transitions (by comparing a
signal with a delayed version of itself)– Provide an output at standard logic levels
(removing unknown offsets)
-
+
C
R
In+:
In-:
Out:
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The test receiver (AC Mode / DC Mode test receiver model)• Test receiver model supporting AC Mode
(AC testing instructions) and DC Mode (EXTEST):
Vbias
AC modeR
DC mode
Set
Clear
D
CLK
Q
..
Input
C
+
-
+
Init clock
-
+
+-
Init data
-
or a time-decaying variant:
IEEE std 1149.6, p. 27: “two simple comparators, one to sense rising edges and the other to sense falling edges; two VHyst voltage sources, to set the hysteresis voltage for the comparators; and a D-type flip-flop memory element, to hold the reconstructed signal.”
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Test receiver support for AC testing instructions
The output of the hysteretic comparator FF will also be as shown when the input signal Vin decays over time
-
Vhyst
R
A
Vhyst B
Vin
C
V
V
-
-A=V
+A
Init Data
-B+
V
Init CLK
+
Set
Clear
D
CLK
Q
..
HystereticcomparatorFF
+B
-
+
-
+
Q (HC FF)
Set
V
Clear
=+A
V - Vhyst
VVin
-A
Vhyst
-B
VV
+B
V
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Test receiver support for (DC) EXTEST instruction
The delay network (RC) is replaced by a bias voltage, since transition detection is no longer required
Clear
VVhyst
V
VVbias
Vin
V+B Vbias V
+A
Vhyst
Q (HC FF)
Set
-
+
Vin
A
-B
V
B
+A
- V+
Vbias
-
Vhyst
Set
Clear
D
CLK
Q
..
Vhyst -
++
Init CLKHystereticcomparatorFF
Init Data
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BS cell with test receiver
-
AC mode Set
Clear
D
CLK
Q
..
ShiftDR
DC mode
-
Capture FF Update FF
R
Shift In
Capture-DR
1
TCK
-
+
EXTEST
0
1
Exit2-DR
EXTEST_PULSE
Exit1-DR
+-
+
D
CLK
Q0
EXTEST_TRAIN
+
D
CLK
Q
CHystereticcomparator FF
Vbias
Input
Mode
1149.6 std 6.2: “When an AC testing instruction is in effect, it is the purpose of the test receiver to reconstruct the test waveform driven by the upstream driver when either AC- or DC-coupling is used. It does this by reacting to the edges and not the levels of the input waveform. When (DC) EXTEST is in effect, the test receiver behaves as a level detector.”
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1149.6 std 6.2.2.1-d): “Whenever a test receiver is operating in the level-detection mode on an AC input pin, the test receiver output shall be cleared of prior history on the falling edge of TCK in the Capture-DR TAP Controller state.”
1149.6 std 6.2.2.2-a): “the output of the test receiver is only relevant during the window of time between the falling and rising edges of TCK in the Capture-DR (…) state.”
BS cell with test receiver (DC Mode)
DC mode
Shift InUpdate FF
TCK
+
-
1
Mode
-
D
CLK
Q1
Capture FF
HystereticcomparatorFF
Input+
0
Vbias
ShiftDR
D
CLK
Q
-
+
Capture-DR
Set
Clear
D
CLK
Q
..
EXTEST
-
+
0
A valid input (> Vbias+Vhyst or < Vbias – Vhyst) will force the HC FF into Set or Clear; otherwise the Capt. FF state will be retained
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Test receiver operation (DC Mode)• Valid input: set / clear the HC FF
– Set: Vin–Vhyst > Vbias (i.e. Vin > Vbias+Vhyst)
– Clear: Vin+Vhyst < Vbias (i.e. Vin < Vbias-Vhyst)
• Invalid input (within the test window): the Capture FF will retain the current value
Vbias
Clear
Vbias + Vhyst
Clear
Set
Vbias - Vhyst
Set
Capt. FFstate
/TCK
Vin - Vhyst
HC FF
Vbias
A
Vin + Vhyst
Set
Clear
D
CLK
Q
..
to Capt. FF
-
+
B-
+
fromCapt. FF
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BS cell with test receiver (AC Mode)
-
+
R
1
-
Mode
D
CLK
Q
EXTEST_PULSE
+-
+
0
AC mode
Exit1-DR
Update FF
+
HystereticcomparatorFF
Set
Clear
D
CLK
Q
..
10
TCK
Shift In
Exit2-DR
C
ShiftDR
-Input
D
CLK
Q
EXTEST_TRAIN
Capture FF
Valid transitions will force the HC FF into Set or Clear; if no valid transitions occur, the Capture FF state will be retained
1149.6 std 6.2.3.1-d): “Whenever a test receiver is operating in the edge-detection mode on an AC input signal, the test receiver output shall be cleared of prior history at a time between exiting the Shift-DR TAP controller state and before entering (…) Update-DR (…).”
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Test receiver operation (AC Mode)• Valid input: set / clear the HC FF• Invalid input (within the test window): the
Capture FF will retain the current value
-
+
Set
Clear
D
CLK
Q
..
C
A
HC FF
fromCapt. FF
B
/TCK
to Capt. FF
R
Vin - Vhyst
-
+
Vin + Vhyst
Vin TAP State
TCK
Driver Signal Data N-1
Edge-Detection Intialise Point
Initial State
Run-Test/Idle
Data or Initial State
Detect Edges (if any)
Inverted Data N Data N
Sel.-DR-Scan
Test receiver output
Capture-DR
Data
Exit1-DR Update-DR
Data N
Shift-DR
Inverted Data
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Conclusion
• Industry-driven 1149.6 enables structural testing capability of AC-coupled single-ended or differential networks
• An underlying fault model facilitates high defect coverage
• Compatibility with 1149.1 enables minimal impact on 1149.1 tools