An Interleaved Single-Stage Power-Factor-Correction Electronic Ballast*

Fengfeng Tao and Fred C. Lee Center for Power Electronics Systems

Virginia Polytechnic Institute and State University Blacksburg, VA 24061-01 11

Abstract- An interleaved single-stage power-factor-correction (PFC) electronic ballast is presented in this paper. The proposed ballast is combined by two interleaved boost cells and a conventional half bridge DC/AC inverter. Each boost cell operates in discontinuous conduction mode so that a high power factor is achieved naturally. By exploiting the interleaving technique, the input ripple current of the electronic ballast is reduced. Theoretical analysis and experimental results for two 45-watt fluorescent lamps are presented.

I. INTRODUCTION

High-frequency electronic ballasts for gas discharge lamps are used widely in lighting systems today because of their merits of small size, light weight, hgh light luminous efficiency, no flicker, no audible noise, and long life [l]. Currently, the electronic ballast has to meet the regulation of IEC 61000-3-2 class C to reduce the line rms current and line-current harmonic distortion. The power line then can be utilized more efficiently. Usually, a two-stage approach with a PFC stage followed by a DC/AC inverter stage is used. The two-stage approach has good performances such as a near- unity power factor and wide range of line input voltage variation. Besides, the design procedure is relatively easy. The main problem of the two-stage approach is that it has more components and, thus, a hgh cost. This is not good for cost-sensitive products. Several single-stage PFC electronic ballasts, aimed at reducing the cost, have been proposed previously [4-lo]. In the single-stage approach, the PFC stage is combined with the DC/AC inverter stage into one single stage; one switch and its controller can be saved, and consequently the cost is reduced. The most commonly used method is to combine a boost converter with the DC/AC inverter stage by sharing a common switch [4-71. A high power factor can be achieved by deliberately operating the boost inductor in the discontinuous conduction mode (DCM) with constant duty-cycle control. However, there exist several problems for the DCM operation. It draws pulsating input current and requires a relatively large input filter. Second, the peak switch current of the PFC stage is much higher, so that a

high-current rating device has to be used. In addition, the bus voltage has to be designed high enough to avoid the non- linear term of the averaged line current [12]. High-voltage rating devices may be required. J. Alonso et al. presented a DCM flyback semi-stage as the PFC stage to solve the third problem [9]. However, a DCM flyback converter needs a gaped transformer and usually has a lower efficiency. M. A. CO et al. proposed a good topology where the PFC stage operates in critical conduction mode to solve the above- mentioned problems [lo]. The problem is that a transformer is necessary to couple the bus voltage. Taking into account the transformer ratio, the peak switchng current of the PFC stage is even bigger than that of DCM boost at the same power factor condition. Four fast recovery diodes are also necessary to rectify the boost inductor current. Component counts increase, which may increase the cost.

In this paper, an interleaved single-stage PFC ballast is presented and analyzed. The presented single-stage electronic ballast employs two small capacitors as a voltage divider to half the rectified line voltage. The effective ratio of the bus voltage to line peak can be doubled to reduce the line current distortion [ 121. By employing the interleaving technique, part of the line ripple current can be canceled out. So, the magnitude of the dc-link current is smaller compared with that of [lo]. Smaller current rating devices can be used. The dc-link current frequency is twice the switching frequency like in [lo]. The high frequency and smaller magnitude of ripple dc-link currents are removed easily with a small input filter, and the two voltage-divider capacitors also function as filter capacitors. The presented interleaved single-stage PFC electronic ballast therefore has a good performance and a low cost. In the next section, the interleaved single-stage PFC electronic ballast is fust derived. The operation principle is analyzed in Section 111. Based on the steady-state analysis, design equations are derived. Section IV provides the simulation and experimental results to verify the theoretical analysis. The paper is concluded in Section V.

This work was sponsored by Matsushita Electric Works (MEW), Ltd, JAPAN, and supported in part by the ERC Program of the National Science Foundation under Award Number EEC-973 1677.

0-7803-5864-3/00/$10.00 0 2000 IEEE / 617 /

11. CIRCUIT DERIVATION

Fig. l a shows a conventionally used two-stage PFC electronic ballast with a boost converter followed by a series- resonant parallel-loaded inverter. The boost converter usually operates in DCM for low power applications and in CCM for high power applications. If the PFC stage is split into two cells, the interleaving technique may be applied, which is shown in Fig. l b [ l 13. Two switches, S B ~ and sB2, operate in 180' out of phase. Two diodes, D D ~ and DD2, are inserted in series with the boost inductors to ensure input current unidirectional. This circuit is good for input ripple current reduction. However, two more switches are used, which is not desirable for low-power applications. In the literature, researchers have proposed systematic strategy to integrate a two-stage approach into a single-stage approach to save a switch and control [4-lo]. Actually, two complementary switches already exist in the inverter stage. It is easy to combine the two boost cells with the inverter stage. Fig. 2 shows the proposed circuit. MOSFETs SI and S2 perform the switching function of s B 1 and sB2. The function of boost diodes DB1 and D B ~ is performed by the body diodes of S2 and SI. Two capacitors, Cdl and Ca, function as the two rectified voltage sources, Vhl and V a . So, with this configuration, adding two capacitors and two boost inductors can obtain an interleaved boost converter to achieve PFC to the electronic ballast.

111. PRINCIPLE OF THE CIRCUIT

In order to simplify the analysis, some assumptions are

1)MOSFETs S1 and S2 operate complementarily with a

2)The bus capacitance, CB, is large enough to be

3)Bus voltage, VB, is always higher than the line peak, 4)The voltages across the filter capacitor, Cf, and voltage

divider capacitors, Cdl and Ca, keep constant during a switchmg cycle since switching frequency is high enough that capacitor impedance is much lower than load,

made as follows

fixed frequency of 0.5 duty ratio,

considered a voltage source,

5)The lamps are modeled as a resistor, Rs, at steady state. Based on the above assumption, the proposed circuit can

be de-coupled as two independent circuits, as show: in Fig. 3 and Fig. 4. The circuit shown in Fig. 3 is a series-resonant parallel-load inverter and was well analyzed in [2]. This paper will focus on the steady-state analysis of the circuit in Fig. 4.

In steady stage, four topological stages exist in one switching cycle as shown in Fig. 5. Key waveforms are shown in Fig. 6. The operation principle is as follows.

[to, t lFl inear charging L B ~ and discharging LB2: Switch S2 is turned off at to. Due to the positive inductor current of iLB2, the body diode of SI is

I

2: ZT

. - - 1 DCM Boost PFC DC/AC Inverter

(a)

Vinl

vinz

Interleaved DCM Boost PFC DC/AC Inverter (b)

Fig. 1 Two-stage power-factorcorrection electronic ballast

Fig. 2 Interleaved single-stage power-factorcorrection electronic ballast

forced to turn on, diverting the inductor current from S2 to diode DI. The voltage source, Vhl, is applied to the boost inductor, LB1, and inductor current linearly increases. Meanwhile, the negative voltage of (VB-Vid) is applied to the boost inductor, LB2, and inductor current linearly decreases. The equivalent circuit is shown in Fig. 5a. At some moment, the inductor current of iLBI is bigger than that of iLB2, and D1 is naturally turned off. The drive voltage should apply to SI when the body diode is conducting current, resulting in zero- voltage switching (ZVS). Based on assumption 4, Vhl equals Vw, half of the rectified line voltage, Vh. So, the discharging voltage of (VB-V,) is bigger than the charging voltage of Va. The inductor current of iLBr must touch zero. DCM is ensured.

[tl, t2)-linear charging L B ~ and DCM of LB2:

618

- Fig. 3 Half-bridge series-resonant parallel-load inverter

Vin

Fig. 5 Topological stages within one switching cycle

Since the inductor current of iLBz becomes zero, the series diode, DD2, is off. There is no voltage across the inductor, LB2, and inductor current stays at zero. The voltage source, Vhl, remains applying to the boost inductor, LB1, and inductor current linearly increase.;. The equivalent circuit is shown in Fig. 5b.

Switch S1 is turned off at t2, and inductor current of iLsl linearly decreases by voltage (VB-Vi,,) through the body diode D2. The voltage source V s is applying to the boost inductor LB2 through D2, and inductor current linearly increases. At some moment, the body diode current naturally shifts to

[t2, t3F1inear discharging LBl and charging LB2:

Fig. 4 Simplified interleaved power-factor-correction converter

1 2

- - (2VB

1 - 2 (2V,

Fig. 6 Key switching waveforms of the circuit

the switch. This mode terminates when iLBl decreases to zero.

[t3, b+DCM of LB1 and linear charging LB2: The inductor current of iLBl stays at zero, operating in DCM mode. The voltage source, V s , remains applying to LB2, and inductor current linearly increases. The equivalent circuit is shown in Fig. 5d. This mode ends at t4, where a new switching cycle begins.

From the above analysis, it can be seen that both boost inductors current iLBl and iLB2 operate in DCM and 180' out of phase. The dc-link current iin equals half of the sum of iLB,

619

where and iLB1.. The ripple current is reduced effectively. The line current, power factor, THD, and circuit parameters can be obtained easily as follows.

A.

one switching cycle is given by

Input Current, power factor, and THD From Fig. 6, the boost inductor peak current, Ipk, during

1 - * qn

I =- 2 1

( 1 ) Pk L, *STS

1 -5. 'in) -7 - -

Lb

where Ts is the switching period, and r is the linear discharging time.

From (I), the linear discharging time is given by

TS 'in

2 (2V, - v i , ) I =

The peak current of (iLBI +iLB.J equals Ipk. The minimum current of (iLB1 +iLBz) is given by

The dc-link current ii,, equals to half of the (iLBl + ~ L B I ) . Due to the input filter and rectifier, the instantaneous line current equals the average dc-link current over one switching cycle, which is given by

1 1 2 4 li, I=iin,ove =-Gm + i L B 2 I o v e =-[Ip, + I h ]

(4)

. a sin wit 1 1 - a . sin w,t

= K .

where T V V P

8Lb 2VB linevoltage v g = V , s i n w , t , K = u , a n d a = - .

Equation (4) shows that line current will contain certain

The line rms current is given by [12] distortion due to the non-linear term of 1 / ( 1 - a . sin w,t) .

The input real power is given by

=VpKa- Y a

The power factor is defied as the ratio of real power to appearance power, and is given as

(7)

If displacement is assumed unit, the THD can be obtained by

THD 2. P R Ji-pF2

--.- - 1 - A

f i Y d 7Lz

Fig. 7 and Fig. 8 show the power factor and THD curve as a hnction of a. Compared with [ l o ] , the power factor and THD is better for a given a. This is because the valley of the dc-link current is proportional to the line voltage with certain distortion while that in [ l o ] always touches zero through the line cycle.

B. Circuit parameters The main circuit parameters of the proposed circuit are

boost inductance, Lg, resonant inductance, J+, and resonant capacitance, C,.

Based on the power balance between the input and output, or

where Po is the output power, and 17 is the conversion efficiency, the boost inductance, Lg, can be obtained by

Po = * e.,, (9)

vp' 17-Y 'Ts L, =- 1 6 ~ . Po

By using the fundamental component approximation [ 2 ] , the series-resonant parallel-load circuit can be described by

1 The corner frequency: w, - - -&E

the resonant frequency: w, = w, 1 - - d dt 620

PF . -

a.

Fig. 7 Power factor as a function of a

J

Fig. 8 Total harmonic distortion as a function of a

voltage will be sufficiently high due to the very high quality factor before the fluorescent lamps are turned on. At the steady state, the resonant tank provides lamp current specified by equation (12). The lamp voltage is described by equation (1 1). Choose an operation frequency slightly greater than U,, say W, = ks mo ; the quality factor, QL, and the characteristic impedance, Z,, can be obtained from equation (1 I), which are given by

(14) kS

The resonant inductance and capacitance is obtained as 20 *ks L. =- (16)

For a given bus voltage, VB, switching frequency, cy, lamp power, and ks, the resonant parameters can be calculated from (14) to (17).

Iv. SIMULATION AND EXPERIMENTAL RESULTS

/? the characteristic impedance: Z, =

R, 20

quality factor: QL =-

The rms lamp voltage (output voltage) is given by

The nns lamp current is given by

The peak value of the switch current (only inverter stage is considered) is given by

I

The resonant tank should provide high starting voltage to start up the lamp and current limiting to stabilize lamp operation after start-up. From equation ( l l ) , the output

The proposed interleaved single-stage PFC electronic ballast was simulated using Pspice to verify circuit operation with 200-V, line input and 85 watt lamp power. The simulated waveforms are shown in Fig. 9. The line current is almost sinusoidal with little non-linear distortion. The switching waveforms are in good agreement with the waveforms in Fig. 6 except for some voltage spike. A prototype was built based on the above analysis. The lamp voltage for two lamps in series is about 230 V,, and lamp resistance is 620 Q. If the switching frequency is selected to be 52 kHz, VB =1.1Vp =311 V, ks = 1.05, and q = 85%, the boost inductors, LBI and LBZ, resonant inductor, I, and resonant capacitor, C,, can be calculated using equations (1 0) and (14 -17)

L B ~ =LBZ =757 pH L, = I . 14 mH C, =9.2 nH

The parameters of the input filter and voltage divider are Lf=lmH Cfz0.47 pH Cdl =Ca =0.33 /JH

Fig. 10 shows the measured line current waveform with a 0.994 power factor and 9.2% THD. Each measured harmonic component meets the IEC1000-3-2 Class C requirement, as shown in Fig. 11. The rectified line voltage and boost inductor current waveforms are shown in Fig. 12a. The envelope of the boost inductor current follows the line voltage. The measured switching waveforms of the boost inductor currents are shown in Fig. 12b. It is seen that interleaved current waveforms are obtained. Fig. 13 shows

62 1

..... .......... .... 35 - -pi

F

30 *ow,

2mw-

w .

-2ow-

i i i - ql

.............. ~ .................... .......................... 8o.r 8Slr P l r s P515 3 O R s CD r u(ui":.)-u(ut":-) m . - I(Ui")

Fig. 9 (a) Simulated line voltage and current waveforms and (b) switching waveforms

Tek 2.SOMS/S 477 ACqS I 1 1

L . . . . . . . . . . . . . . . . . . . . .

. . . .

t . . , . . . .,i

i U 0 V M2.00tnS ( h l x -64 9 J u l 1999

t: 2 m / d i v v g : 100 V/div i,: 0.5 A/div 10:14:42

Fig. 10 Measured line voltage and current waveforms

3 5 7 9 11 13 15 17 19

Harmonic order

Fig. 1 1 Measured line current harmonics

Tek m 2SOW/S 244 AcqS I T - 1

- k ' . ' . . ! + '

L 4.

, I . , . . . . . . / . . 9 J u l 1999 C h l 10.0mVR Cl72 ItJU V MZ.00ms i 112 1 3 0 v 10:20:57 1O.OmVR

(a) 1: 2 ms/div v ,": 100 V/div i : I A/div

1 0 . o m v ~ M >.Oops 112 f 234 9 JUl 1999 10:23:06 1 o OmvR

(b) t: 2 mddiv i ,,,: 0.5 A/div

Fig. 12 (a) Measured boost inductor current and @I) switching waveforms

the lamp current waveform with a flat envelope of 1.38 crest factor. Fig. 14 shows the switching-current waveform. It is seen that the ZVS is ensured over line cycle. The maximum

switching current is about 2.8 A. The measured efficiency is 83% except for filament loss.

622

V. CONCLUSION

i , f

10.0mVR MZ OOms Cl12 1 1: 2 ms/div i 0.2 A/div 10:28:23

Fig. 13 Measured lamp current waveform

Tek Emw 2.50MWs 60 Acqs f - . . . .T-- 4

10:59:13 (a) 1: 2 ms/div vg‘ I O 0 V/div is: 2 A/div

in C L ? I I L )Is 9lUl l999 11300329

k.0 vn , I l,o 1 , t n i i ,,,j (b) t . 2 ms/div i ,,,: 2 A/div

Fig. 14 (a) Measured swtching current over line cycle and (b) swtching current near line peak

This paper presented an interleaved single-stage PFC electronic ballast. The circuit was de-coupled into an interleaved PFC stage and DC/AC stage under some assumptions. The operation principle of the interleaved PFC stage was analyzed, and a design procedure was established to optimize the circuit. An 85-watt prototype was implemented to verify the analysis. Experimental results show that by using the voltage divider and interleaving technique, the proposed circuit features low line current distortion and low line current ripple. The circuit also features the low lamp current crest factor, and simple structure with potential low cost.

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