A Transceiver fo

João Gomes Carvalho INESC TEC

Rua Dr. Roberto Frias, 378, 4200-465 Pojoao.p.carvalho@inescporto.p

Abstract — A transceiver for single-linamong sensor nodes of a body-area network meant to operate on a mesh like network interconnected by two conducting-textile linboth power and communication features. Theare sewn directly to the garment in order mobility and comfort. For the same reasonplaced in a central processing module is used tnodes. A low-dropout voltage regulator stransmission-line via a low pass filter ensurerespective 3 V DC power supply. Power-lineperformed using a binary phase shift keying mover a non-zero direct current line voltage at atransceiver includes also line-fault testing to deare likely to occur due to the stress appliedyarns.

Keywords — Transceiver; body-area netwoline-communication (PLC); Binary-phase-shifCMOS; electronic textiles; line-fault detection.

I. INTRODUCTION With the continuous increase of populati

a strong trend emerged in the biomedical awhich consists on pushing health monitoringto the user, in an effort to reduce costs and life quality. This way, the hospital concept into smaller and more distributed healtincluding home, up to the point where some tasks can be done with the patient living his d

With this goal in mind, a significant rebeen made to develop economic yet reliablproviding, as non-obtrusively as possible, poof biological signals. Many of the solutionproposed so far are based on placing sensorscan be worn without any extra special carethese require the implementation of a b(BAN), where information and power flonodes, until data is eventually transmittecomputer for analysis [2].

That has been pursued in the ProLimb a(http://proj.inescporto.pt /prolimb /sivicdeveloping a BAN to capture electrocacardiorespiratory, or electromyographic (EMas inertial data (with accelerometers and composed by a group of sensor nodes interctextile-conductive yarns. Fig. 1 shows an e-to capture EMG and kinematic signals of thgait analysis purposes. It comprises eight nolower limb) interconnected in a mesh topoconnected to a central processing module (Cdata is sent to an external laptop or PDA with

or E-Textile Body-Area

orto, Portugal pt

José MachINESC TEC, Faculdade dePorto; Rua Dr. Roberto Fr

jms@

ne communication k is presented. It is

where nodes are nes, which provide e textile conductors

to enhance user’s n, a single battery to supply all sensor upplied from the s in each node the

e-communication is modulation process

a 10 Mbps rate. The etect hazards which

d to the conductive

ork (BAN); power-ift-keying (BFSK);

on life expectancy applications arena, g procedures closer

provide for better is being translated th care services, health monitoring

daily life [1].

esearch effort has e tools capable of ortable monitoring ns that have been s on garments that e. The majority of ody-area network

ow among sensor ed to an outside

nd SIVIC projects c) which aim at ardiogram (ECG), G) signals, as well gyroscopes). It is connected through legging developed he lower limbs for odes (four in each

ology (Fig. 2) and CPM), from which h a Bluetooth link.

Fig. 1. Photo of the e-legging mock-uamong sensor nodes.

Data is routed in the mcommunication protocol – SouForwarding (SRMCF) [3].

Fig. 2. Interconnection topology of th

The network can be exteprepared to capture different sensor node developed to operaortic surveillance system, cmonitor and an advanced Endovascular Abdominal Aortwhich allows capturing a 1abdominal aorta intra-sac pressu

Fig. 3. Wearable integrated cardiovas

a-Networks

hado da Silva e Engenharia, Universidade do rias, 4200-465 Porto, Portugal

@fe.up.pt

up and diagram of yarn interconnections

mesh network using a custom urce Routing for Minimum Cost

he mesh sensors network.

ended with other sensor nodes signals. That is the case of a rate as a combined cardiac and

comprising a wearable cardiac telemetry system for post-

tic Repair (EVAR) surveillance, 2-lead ECG, as well as the ure [4].

scular surveillance system.

978-1-4799-2921-4/14/$31.00 ©2014 IEEE

Conductive yarns have proved to be convenient from the obtrusiveness point of view, since these allow channels among nodes to be sewn to the garment, improving user’s comfort and mobility. But still, there are some drawbacks associated to this solution, which are essentially due to higher and more variable impedance characteristics, compared to those provided by traditional copper wires. TABLE I. shows the impedance variation observed when stretching or relaxing 60 cm long conductive spun yarns made with: (type 1) a mixture of a non-natural fiber (like polyester) and stainless steel fibers, and (type 2) yarns made with twisted filaments, each one a polymeric filament covered by a very thin layer of conductive material, generally silver [5].

TABLE I. CONDUCTIVE YARN PER-UNIT-LENGTH IMPEDANCE.

Yarn

Relaxed (natural length) Stretched (1.5 natural length)Ω/cm nH/cm Ω/cm nH/cm

1 0.65 16.4 0.47 6.682 6.76 35 4.43 33

A two dimensional yarn display on the garment is also a limitation that can demand an increase of yarns length to avoid overlap, and thus a worsening of line impedances. Other critical aspect concerns the interconnections’ reliability, since these garments are likely to be subject to frequent wear and washing cycles, i.e., subjecting the yarn to a very hostile environment, which can result on faults electrically translatable into line short or open circuits.

Different solutions to address these challenges have been published, and some are still under development, for this is actually a very active research subject at the moment. To exchange data wireless communications are often used, but still they come at the cost of higher power consumption, which is a critical aspect on a system where the number of batteries and bulky components is to be kept to a minimum [6]. Wired networks are preferable from this point of view, but the communication between nodes is harder to perform due to the type of transmission lines in use, which are mainly chosen after a trade-off between user’s comfort and electrical characteristics.

Power-line-communication (PLC) is a very demanding feature on wired nets and its implementation is not always straight forward. In [7] a solution is presented where communication and powering functions are performed through the same transmission line, but in different time intervals, which comes at a cost of reduced efficiency data-exchange rate due to line allocation for different and non-coincident functions. With such operational characteristics, the need arises for node capacitors to be relatively larger in order to maintain local power supply during communication.

As far as testing is concerned the most commonly seen strategy consists in transmitting a stimulus, most of the time a pseudo-random-bit-sequence (PRBS), and simultaneously read and store it through multiple but equal receiver arquitectures at the same port. Posterior to that, all the corresponding values are compared, the associated results are weighted, and based on such function a decision is made to characterize the transmission line as being in good condition or not [8]. This is a commonly adopted strategy, but it can consume considerably higher power due to the multiple components being involved.

To address the power distribution, communication, and testing issues presented above a specific transceiver has been developed, capable of driving these higher and variable impedance transmission lines, to provide communication at 10

Mbps rate over the power DC line voltage, in order to reduce the number of yarns needed to perform both functions without impairing data rate communication. Some details on the BAN system are presented in section II. The main blocks of the transceiver being proposed are described in section III, being post-layout simulation results of the demonstration prototype chip presented in section IV and final remarks and conclusions in section V.

II. SYSTEM DESCRIPTION The power line communication (PLC) in a mesh network

(Fig. 2) scheme being developed allows for more than two sensor nodes to communicate between each other simultaneously as the pulse signals in the interconnections between different node pairs are independent. This allows increasing data rate and provides for a better synchronization among data captured by the different nodes. The main power supplying battery is placed in the CPM and power distribution is ensured by a line-to-line AC filtering scheme along with specific low-dropout regulators (LDO) existing in each sensor node, to provide the internal power source.

Fig. 4 shows a high-level block diagram of the developed integrated circuit (IC) and its peripheral components. To perform data injection into the non-zero DC voltage line, the Transmitter block uses a capacitive coupling solution designed in such a way that provides a binary phase shift keying (BPSK) modulation, consisting on the generation of positive/negative pulses, for every data signal rising/falling edge, respectively [9][10]. Data demodulation is carried-out at the Receiver block within a clock-less, simple and practical scheme using a biased Schmitt Trigger (ST), aiming at performing its function efficiently with the minimum number of components possible, which also contributes to reduce power consumption. This is a very important aspect since a single battery is used to power all sensor nodes throughout the network, in an attempt to improve the non-intrusiveness characteristics of the wearable system, as batteries tend to be bulky.

Fig. 4. Transceiver’s integrated circuit block diagram.

A specific block allows detecting line faults during normal mission operation. Short- (SC) and open- (OC) circuits are detected which actually correspond to, respectively, line impedances lower and higher than acceptable thresholds. This test procedure does not require the observation of transmitted pulses at the receiving node, what allows for a simpler operation as no additional communication is needed to capture the received signal. Instead, it consists of sensing the voltage drop in the parasitic ohmic resistance of an inductor (L_lp, Fig. 4).

III. TRANSCEIVER FUNCTIONAL

This section describes the role and operatthe blocks of the proposed IC, identifieTransmitter, Receiver, Line Fault DetectoVoltage Generator.

The LDO scheme won’t be described in dit is based on the solution presented in [11]. Idesign is to power supply all the blue area blcontroller with regulated 3 V DC at 50 mAmargin-current-value since the processing un10 mA and the rest of the circuit won’t need to operate properly. In order for such pachieved, a minimum of 3.1 V DC must LP_in pin, so that the LDO 100 mV compensated without compromising functiouseful feature of this specific block is itsControl (DFC) stage that enables the placeC_ldo at the output without consequent oscilenhances the quality of the 3 V voltage control kicks in for very small load situatialso drive the LDO into oscillation if the Dpresent. The reference voltage of this block Reference Voltage Generator, which will be d

The transmission line impedance (Zline, a resistor–inductor series of nominal values respectively, obtained according to informTABLE I. for a 60 cm long yarn of type 1, for this application due to its better impedancompared to those of yarn 2. These are uppassumed in order to assure a worst case ssince sensor nodes will hardly be 40 cm awain the legwear prototype being developed, impedance will be smaller. Notice that twoper node connection, of which one is used tand data, while the other provides ground (Gevery node in the net. In Fig. 4, the IC piGND is common to every block and thussimplicity and better conceptual undconnections were omitted. For similar retransmission-line port is represented, but mothe cost of replicating the blue zone blocksaddition. An identical procedure must also each respective transmission-line’s AC filter to be connected to LP_in pin, in parallel witmore I/O ports can be created in each node’allows creating a variety of different intemesh-like fashion, with line-to-line AC isolathe second-order low-pass filter C_lp and L_the AC data signals and prevents them froother line besides the one they are meant to. Owith such scheme, the DC line voltage compto all nodes, resulting in a power sourcing rthe current flowing from the system’s balocation. However, due to the line’s impedanwill occur and result on a progressively devoltage as the distance to the battery increase

A. Transmitter The strategy adopted to generate comm

over the DC voltage line relies on capacitivoutput of two in-series inverters to the transm5). Transistors Q3 and Q4 are made relativelprovide for a good voltage swing, which in tucapacitor to properly generate data pulses dufunction. This way, a positive/negative

BLOCKS tion of each one of ed in Fig. 4 as

or, and Reference

detail here because Its function on this locks and the local

A, which is a safe-nit consumes about more than 1.5 mA erformance to be be assured at the voltage drop is

onality. One very s Damping Factor ement of capacitor llation, which thus source. The same ons, which would

DFC action wasn’t is generated at the described later.

Fig. 4) consists of 39 Ω and 984 nH

mation provided in which was chosen nce characteristics per bounds values

scenario operation, ay from each other

and thus the real yarns are needed

to exchange power GND) reference to n that connects to s, for the sake of derstanding, such easons, only one re can be added at

s for each singular be carried out for inductor, which is

th L_lp. This way, s transceiver. That

erconnections in a ation performed by _lp that attenuates m flowing to any On the other hand, ponent is common route that delivers

attery to each net nce, voltage drops ecreasing DC line s.

munication pulses ve coupling of the mission-line (Fig. 5 ly large in order to urn will enable the ue to its derivative

going pulse is

transmitted each time there’s asignal.

Since Q3 and Q4 dimenspreviously presented reasons, thnot be availed to control pulimportant parameter, since it duration. That function is enoutside the chip because the reqachievable with an integratedamong nodes vary, this externadjusted to each case. That manipulated to match the pulsoperation conditions. By doing improved, since larger pulses (only generated where really nee

Fig. 5. E-textile pulse transmitter circ

Fig. 6. E-textile receiver’s schmitt trig

With C1 being 10 pF and39+jω984 10 Ω, R1 was pulses amplitudes result in 600 order for them to be easily disnoise on the receiver’s side of th

B. Receiver To detect and demodulat

Schmitt-Trigger (ST) inverter iensures that the positive and nonce the line voltage goes threshold values. Another impothat between the two thresholdis tolerated without compromisi

a rising/falling edge on the data

sions are restricted due to the heir conduction resistance could ses’ time constant, which is an determines their amplitude and sured with resistor R1, placed quired low tolerance value is not d resistor. Also, as net lengths nal resistor can be specifically is, each time constant can be

ses amplitude to the demanding this, power management is also

(which imply higher power) are eded.

uit scheme.

gger circuit scheme.

d the line impedance equal to designed to be 2.5 kΩ so that mV with a duration of 3.4 ns, in

stinguishable from eventual line he line.

e the received data, a biased s used whose hysteresis window egative pulses are only detected above or below the designed

ortant advantage of this design is s, a certain amount of line noise ing the communication.

Pulse detection demands fast operation froand for that reason the conventional version not be used. The adopted alternative is presepositive edge threshold voltage is defined by Q10, whereas that of Q9 imposes the negativratios of the ST input inverter transistodetermine the location of the hysteresis windmoving the whole hysteresis window up or do

Transistors Q5 and Q6 provide the circuiThese two transistors are connected in a diothe respective gate-source voltages be responthe desired bias potential. This way a higfrom aspect-ratio variations is assured, alterndrain-source approach. Such independencefabrication-process induced dimensions considerably change the DC bias point and demodulation efficiency. Capacitor C2 provwith the communication line.

C. Reference Voltage Generator The LDO and the Line Fault Detector requivoltages. One of those (Fig. 7) was designpurpose since it performs a bias function forstages that exist on both blocks and acts at tvoltage (Vbias) reference for the LDO. meaning of Vsc and Voc will be presented Detector’s section.

In order to improve the accuracy oreferences all transistors were made with relaratios to minimize the effect of process-induc

Fig. 7. Reference voltage generator scheme.

In Fig. 7 Q13 to Q16 constitute a boosource, which is adopted here due to iindependent characteristics. This is an impothe referred stage is sourced by the local lowwhich is likely to show different potentials fdue to transmission-line voltage drops. The is connected to the IC pin R_bias which provan external 190 kΩ resistor (in a 0805 packa5 µA current. This small value was adopteconsumption purposes, since it is to be subsequent stages. Branches Q17-Q19 and QVsc and Vbias voltage references. These twomore than one transistor’s threshold voltagesmaller than the power supply potential minudrain voltage drop.

om the ST inverter of this gate could

ented in Fig. 6. Its the aspect ratio of

ve one. The aspect ors, Q7 and Q8, dow, that is, allow own in voltage.

it biasing at 1.5 V. ode mode in order nsible for imposing gher independence natively to using a e is desirable as variations would consequently data

vides AC coupling

ire three reference ned to be multiple r some differential the same time as a

The values and in the Line Fault

of the generated atively high aspect ced variations.

otstrapped current its good voltage-

ortant feature since w-pass filter output, from node to node, source pin of Q15

vides connection to age) for a resulting ed for low power replicated by the Q20-Q21 generate

o voltages differ by e, being their sum us the Q17 source-

D. Line Fault Detector The main goal of this block

line is in good condition to be uresult to the local controller. Tscheme was developed that condifferential voltage at the inducnon-zero resistance) and then values, from which the result wcondition.

As shown in Fig. 8, thisthrough LP_in and Rx, avoidibut at the same time demandinthe printed-circuit-board (PCconsists on placing the inducmentioned pins, to prevent theparasitic resistance. The effectswere also taken into considerdesign.

Fig. 8. Line fault detector block diagr

In order for the inductor to high internal resistance, a 2chosen. This value allows genethe same time it is not that degrade the network power flCPM supplies all nodes in thpower/communication (PC) pnodes each; each sensor node mA for the digital controller acircuit.

In the worst case, the indumA for each PC port at the CPdetermined by the maximum cThis limit has been set to corpower supply currents in a groVoc is established by the miniman interconnection betweencomparators are used to compamplifier with each one of thethe result will be the two bits about a line condition – SC chashort-circuit (a current higher thOC behaves likewise for an osmaller than the expected minim

IV. SIMULA

The simulation results probtained on the Cadence Virtulayout version (Fig. 9) of a designed within a 0.35 μm Mcore occupies an area of 2.9 mpins, the full area is 5.9 mm2.

k is to detect if the transmission used, and then communicate the To achieve such functionality a nsists on sensing and amplify the ctor’s terminals (imposed by its compare it with two reference

will allow to diagnose the line’s

s differential voltage is sensed ng the need for any extra pins,

ng an essential extra care during B) layout design phase, that tor as close as possible to the

e eventual effect of a PCB track s of other parasitic voltage drops ration regarding the IC layout

ram.

have a considerable but not too 200 mΩ series resistance was rating a workable voltage, but at

high that would significantly flow. The battery placed in the he network; the CPM has two ports connected to four sensor

consumes around 11.5 mA: 10 and 1,5 mA for the transceiver

uctor’s current will be about 40 M. The Vsc voltage reference is

current that would flow in a PC. rrespond to the sum of the four oup plus a tolerance. Similarly, mum current that would flow in n two sensor nodes. Two pare the output of the sensing ese two references, from which that inform the local controller

anges from 0 to 1when there is a han the expected maximum) and open-circuit situation (a current mum).

ATION RESULTS resented in this section were uoso framework with the post-

prototype demonstration chip MOS technology. The functional mm2. Considering also the 10 I/O

Fig. 9. Prototype chip layout.

Fig. 10 shows the signals obtained when a PRBS signal is transmitted at a 10 MHz clock rate. Some clock induced noise is visible on the line since the data transmission is being made from a node with no battery, and thus the ground’s quality is not perfect. However, it can be seen from the Received Data signal in the bottom of Fig. 10, that the transmitted information is correctly recovered. The line-noise tolerance characteristic of the receiver’s ST prevents received data to be corrupted by the noise seen in the Received pulses.

Fig. 10. Normal condition communication signals.

Fig. 11 depicts the most important waveforms involved in a line-condition test. To acquire such signals, a current source was placed at the end of the transmission-line in order to force a variation from 0 to 80 mA. It can be seen in that an open-circuit fault situation is detected for current values smaller than approximately 2.5 mA, whereas a 75 mA current will lead the test to identify a line short-circuit case.

In order to better estimate the chip’s power consumption, measurements were made at three different operating conditions: continuously transmission at 10 MHz, 5 MHz and idle state operation. The respective results are 4.7 mW, 4.5 mW and 3.4 mW, corresponding to an average consumption of 4.2 mW (Table II). When performing communication, the energy required to transmit one bit is about 10 pJ, considering both transmitter and receiver operations. With the AC-filter inductor’s 200 mΩ resistance, a power dissipation of 461 µW will occur at the corresponding CPM connection to each four-node group, assuming a 12 mA individual consumption.

Fig. 11. Transmission-line condition test signals.

This power loss progressively drops as the distance to the CPM increases, since the number of nodes left to source decreases accordingly, resulting on a minimum dissipation of 28.8 µW at the end of the chain. While performing a 10 MHz continuous transmission, the power dissipation on the 2.5 kΩ R1 is 503 µW, decreasing to 344 µW if frequency decreases to 5 MHz.

TABLE II. TRANSCEIVER CHIP CHARACTERISTICS

Type wired CMOS Technology 0.35 µm

Supply Voltage (LDO) 3 V Data rate 10 Mbps

Power consumption (average) 4.2 mW Bit transmitting energy 5.1 pJ/bit

Bit receiving energy 4.9 pJ/bit

Preliminary experimental results have also been obtained with the fabricated chips. Fig. 12 shows the waveforms of a ~11,5 MHz frequency signal transmitted between two chips interconnected with 20 cm conductive yarns; CH1 is the signal applied in the transmitter input (T_Data in figure 4) and CH4 is the signal captured in the receiver outpu (R_data in figure 4). It can be seen that the signal is eficiently transmitted, even at a frequency higher than the 10 MHz specification.

Fig. 12. Waveforms of transmitted and received signals obtained with

prototype demonstration transceiver chips.

V. CONCLUSIONS The design of a new transceiver specifically developed to

be used on wired body-area networks implemented within

technical fabrics substrates using conductive yarns for both communication and power distribution, is presented. This transceiver provides power-line communication through a capacitively coupled binary phase shift keying mechanism and generates a regulated 3 V DC voltage to source all the node’s sub-systems after the non-regulated line voltage. Line-fault testing capability is included which allows detecting short and open circuits, as well as considerable deviations of the line impedance. A prototype demonstration chip was designed and fabricated in a 0.35 μm MOS technology. Post-layout simulation results are presented which illustrate the transceiver operation and confirm the functionality of the line-fault detection scheme being proposed. Preliminary experimental results show that efficient communication is achieved.

ACKNOWLEDGMENTS This work has been financed by the ERDF – European

Regional Development Fund through the COMPETE Programme (operational programme for competitiveness) and by National Funds through FCT – Fundacão para a Ciência e a Tecnologia (Portuguese Foundation for Science and Technology) within projects PROLIMB PTDC/EEA-ELC/103683/2008 and SIVIC PTDC/EEI-ELC/1838/2012.

REFERENCES [1] Mehmet Engin, Alparslan Demirel, Erkan Zeki Engin and Musa

Fedakar, “Recent developments and trends in biomedical sensors,” Measurement, vol. 37, pp. 173-188, Mar, 2005.

[2] M. Chen, S. Gonzalez, A. Vasilakos, H. Cao, and V. C. Leung, “Body area networks: a survey,” Mobile Networks and Applications, p. 123, 2010.

[3] F. Derogarian, J. Canas Ferreira, and V. Grade Tavares, “A routing protocol for wsn based on the Implementation of source routing for minimum cost forwarding method,” in SENSORCOMM 2011, The Fifth International Conference on Sensor Technologies and Applications, 2011, pp. 85–90.

[4] Cristina C. Oliveira, José Machado Da Silva, “Towards a dependable cardiovascular surveillance system'', IFMBE International Conference on Health Informatics, Vilamoura, Portugal, 7-9 Nov., 2013.

[5] Andreina Zambrano and José Machado da Silva, “Signal integrity and interconnections test on technical fabrics”, 18th IEEE International Mixed Signals, Sensors and Systems Test Workshop, Taiwan, May, 2012.

[6] Alan Chi Wai Wong, Mark Dawkins, Gabriele Devita, Nikolaos Kasparidis, Andreas Katsiamis, Oliver King, Franco Lauria, Johannes Schiff and Alison J. Burdett, “A 1 V 5 mA multimode IEEE 802.15.6/bluetooth low-energy WBAN transceiver for biotelemetry applications”, IEEE Journal of Solid-State Circuits, vol. 48, no. 1,pp. 186-198, January, 2013.

[7] Patrick P. Mercier and Anantha P. Chandrakasan, “A supply-rail-coupled etextiles transceiver for body-area networks”, IEEE Journal of Solid-State Circuits, vol. 46, no. 6, pp. 1284-1295, June, 2011.

[8] Guinee, R.A., "A novel pseudonoise tester for transmission line fault location and identification using pseudorandom binary sequences," Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2012 IEEE International Symposium on , vol., no., pp.225,232, 3-5 Oct. 2012.

[9] Ron Ho, Tarik Ono, Robert David Hopkins, Alex Chow, Justin Schauer, Frankie Y. Liu and Robert Drost, ”High speed and low energy capacitively driven on-chip wires”, IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 52-60, January, 2008.

[10] Vipul Chawla and Dong Sam Ha, “Dual use of power lines for data communications in microprocessors”, IEEE 14th International Symposium on Design and Diagnosis of Electronic Circuits & Systems (DDECS), pp. 23-28, April, 2011.

[11] Ka Nang Leung, Philip K. T. Mok, “A capacitor-free cmos low-dropout regulator with damping-factor-control frequency compensation”, IEEE Journal of Solid-State Circuits, vol. 38, no. 10, pp. 1691-1702, October, 2003.