Digitally Programmable Second-Order Current mode Continuous-time Filters

Mohd. Zihaib Khan Dept of Electronics Engineering Aligarh Muslim University, India

zohaib017@gmail.com

Mohd. Samar Ansari Dept of Electronics Engineering Aligarh Muslim University, India

mdsamar@gmail.com

Mohammad Jawaid Siddiqui Dept of Electronics Engineering

Aligarh Muslim University, India mjs_siddiqui@rediffmail.com

Abstract—The advent of differential voltage current conveyor (DVCC) has opened up new avenues in analog circuit design. However, a feature that is lacking in DVCC-based circuits is the non-availability of external control over circuit performance. To overcome this disadvantage, a new Digitally Controlled DVCC (DC-DVCC) has recently been proposed. In the present work, the DC-DVCC has been employed to design digitally programmable current-mode second-order continuous-time analog filters. Parameter tunability is achieved by the use of a 3–bit digital control word. The circuit can realize multiple circuit transfer functions by choosing the appropriate input and output terminals. Additionally, the circuit parameters Q and ω0 can be set orthogonally by adjusting the passive components. The biquadratic circuit enjoys low sensitivities to circuit components. The proposed circuits are amenable for monolithic integration by virtue of the fact that only grounded components are employed. Circuit simulations using PSPICE yielded promising results.

Keywords—Digital Control, Digitally Controlled Differential Voltage Current Conveyor, DC-DVCC, Digitally Tunable Circuits.

I. INTRODUCTION The continuous time analog filter is a ubiquitous circuit component in a variety of applications including noise rejection & signal separation in industrial and measurement circuits, feedback of phase & amplitude control in servo loops, smoothing of digitally generated analog signals, audio signal shaping & sound enhancement, channel separation & signal enhancement in communication electronics [1]–[9]. Active filter design generally employs one (or more) active building block and passive components like capacitors and resistors; inductors being avoided due to their incompatibility with the standard CMOS fabrication process. The active element may be one of the following: operational amplifier, second generation current conveyor (CCII) [5], operational transconductance resistance amplifier (OTRA) [4], fully differential current conveyor (FDCCII) [1], third generation current conveyor (CCIII) [7], differential voltage current conveyor (DVCC) [2], [3], [9], etc. Circuit design using each of these building blocks has its own associated advantages and limita-tions with the DVCC offering the highest amount of flexibility and simplicity in analog electronic circuit design. Current-mode (CM) signal processing has received considerable research attention in the recent past due to associated advantages like extended bandwidth, higher dynamic range, suitability of operation in reduced power supply environments, possibility of simpler circuit realizations

and low power consumption [2], [6]–[9]. However, not much work is reported on incorporating digital programmability in CM circuits. In this paper, DC-DVCC-based implementations for current-mode first-order high pass filter (HPF) and low pass filter (LPF) are presented.

This paper is organized as follows. Section–II presents a review of a recently introduced Digitally-Controlled DVCC and then deals with details of the proposed second-order filter configurations. Section–III presents the results of computer simulations of the proposed circuits using the PSPICE program. Non-ideal analysis and discussion on VLSI implementability of the proposed circuit appears in section–IV. Some conclusive remarks appear in section–V.

II. EXISTING METHODS Analog filter design using a variety of active building blocks has been an active area of research for the past two decades. Operational amplifier was the active element of choice during the earlier stages of development. Later, the advent of current conveyors signaled the era of mixed-mode and current-mode signal processing. Since there has been a significant amount of technical literature available on the subject, it is not possible to attempt a thorough review of all the related works. Therefore, a survey of some of the recently published works is presented in this section. The DVCC was introduced by Elwan & Soliman and its application in continuous-time filters was also discussed [5]. Adawy, Soliman & Elwan later proposed another analog building block viz. the Fully Differential Current Conveyor (FDCCII) and several applications in electronic filters were also presented [3].One significant feature of the filters designed using FDCCII was the possibility of obtaining fully-differential processing. Cakir, Cam & Cicekoglu put forward an all-pass configuration employing a single OTRA [4]. Minaei & Ibrahim employed the DVCC for implementing a general topology for obtaining current-mode first-order APF [6]. A third-generation current conveyor (CCIII) was utilized to yield a transadmittance type first-order filter [7]. Maheshwari reported CM all-pass, high-pass and low-pass filter sections based on DVCC, which form the background for the present work. [9]. Minaei & Ibrahim presented a mixed-mode universal filter based on the KHN-biquad topology employing DVCCs [8]. Another voltage-mode all-pass filter using DVCC as the building block is attributed to Minaei & Yuce [2]. More recently, Maheshwari et al. used the FDCCII to realize all-pass/notch filters employing only grounded capacitors as passive elements [1].

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III. PROPOSED CIRCUIT The differential voltage current conveyor (DVCC) was pro-

posed in 1997 as a five terminal device characterized by the following port relations [5]:

(1)

Fig. 1 shows the schematic symbol of a DVCC. While the voltage at the X-terminal follows the difference in voltages of terminals Y1 and Y2, a current injected at the X-terminal is replicated by a factor k to the Z-terminals. For the Z+ terminal, the direction of the conveyed current is the same as that of the current flowing in the X-terminal whereas for the Z- terminal, the current flows in the opposite direction. Ideally, k is unity. One possible CMOS realization of the DVCC is shown in Figure 2. As can be seen, the current at Z+ port will be the same as the current in the X terminal and the current at the Z-terminal will have the same magnitude but opposite direction as the X port current. To obtain a Digitally Controlled DVCC (DC-DVCC) from a DVCC, the technique is to control the current transfer gain parameter k of the DVCC by replacing the Z terminal transistors of the DVCC with transistor arrays associated with switches [10]. The gain parameter k can take

values from 1 to (2n– 1), where n represents the number of transistor arrays. Actually, the transistor arrays implement a current summing network (CSN) at the Z terminal. The circuit of DC-DVCC obtained after suitable modifications in the circuit of Figure 2 is presented in Figure 3 [10].The CSN consists of n transistor pairs, whose NMOS and PMOS aspect ratios are given by:

PMOS

(2)

NMOS

(3)

Therefore, the current at the Z terminal, assumed flowing out of the DC-DVCC, can be expressed by:

(4)

Therefore, the proposed DC-DVCC provides a current transfer gain equal to:

(5)

Parameter di represents the digital code-bit applied to the i-th branch in the CSN. Depending upon its value, it enables or disables the current to flow in that particular branch. It is instructive to note the numbering of the transistors in the CSN. Transistors M8 (i) and M12 (i) refer to the PMOS and NMOS transistors in the CSN that have been put there in the place of their counterparts of Figure 2. Transistors MD8 (i) and MD12 (i) are the actual digital control transistors as the digital control bits d0, d1 and d2 are applied at their respective gate terminals. This section further presents the proposed DC-DVCC based current-mode second-order continuous-time filters with digital control of filter parameters like gain and cut-off frequency.

Fig. 4 shows a current-mode biquadratic filter employing one DC-DVCC, two grounded capacitors and two grounded resistors. In this circuit, we consider two input and output terminals in order to realize the biquadratic characteristic.

Fig. 1. Electrical symbol of DC-DVCC [10]

Fig. 2 CMOS implementation of DVCC [10]

Fig. 3. CMOS realization of Digitally Controlled DVCC with gain k [10]

Routine analysis yields the current outputs Io1(s) and Io2(s) as:

(1)

(2)

The equations above imply that, with different input and output terminals, the circuit in Fig. 4 can implement a variety of circuit transfer functions as shown below. The input is fed at the node marked IIN1 and IIN2 and the output is available at IO1 and IO2. The filter parameters can be controlled by varying the 3–bit digital control word.

IV. SIMULATION RESULTS The proposed circuits were simulated in PSPICE to ensure that the expected functionality is indeed obtained. Fig. 5 and Fig. 6 depict the variation in the low-pass, high-pass, band-reject and all-pass responses when the 3–bit digital control word is changed from [0 0 1] to [1 1 1].

Fig. 5. PSPICE simulation result for the proposed electronically

tunable current-mode LPF and HPF

Fig. 6. PSPICE simulation result for the proposed electronically

tunable current-mode BRF and APF Furthermore, Fig. 7 and Fig. 8 illustrate the variation in control frequency with different control words. All the plots are in excellent mathematical conformity with the transfer functions given in (3–10). The cut-off frequency is found to vary from 1.018MHz to 7.008 MHz for low pass, from 1.047 MHz and 7.222 MHz for band-pass, from from 1.009 MHz to 0.138 MHz for high-pass, from 1.042 MHz to 6.781 MHz for band-reject and from 99.783 KHz to 695.651 MHz for all-pass filter by changing the control word from [0 0 1] to [1 1 1]. Indicative tables of variation of the cut-off frequency of the proposed LPF and HPF with the 3–bit digital control word are presented in Table I and Table II respectively.

Fig. 7. Variation of cut-off frequency of the proposed LPF and BPF

with digital control word

Fig. 8. Variation of cut-off frequency of the proposed HPF and BRF

with digital control word

Fig. 4. Proposed DC-DVCC based digitally programmable current-mode

second order filter

V. DISCUSSION Actual monolithic integrated circuit implementation issues of the proposed circuit are discussed in this section. The analysis presented in the previous section assumed that the DC-DVCC is ideal, and therefore, analysis is required to determine how deviations from this assumption affect the performance of the circuit. The realistic, non-ideal defining equations for the DC-DVCC are given as

(13)

The non-ideal current-mode transfer functions corresponding to (6), (7), (8), (9) and (10) can be given as:

TABLE I VARIATION OF CUT-OFF FREQUENCY WITH THE 3–BIT DIGITAL

CONTROL WORD FOR THE PROPOSED LPF

TABLE II

VARIATION OF CUT-OFF FREQUENCY WITH THE 3–BIT DIGITAL CONTROL WORD FOR THE PROPOSED HPF

Furthermore, all the proposed circuits are compatible with contemporary CMOS processes as only MOSFETs and grounded resistors and capacitors are employed. The absence of floating resistors and capacitors serves to lower the chip area and reduce fabrication costs.

VI. CONCLUSION In this paper, current-mode digitally controllable filters based on DC-DVCC were presented. Tunability by means of a digital control word was achieved and demonstrated. Standard low-pass, high-pass, band-pass, band-reject and all pass filter functions were obtained. PSPICE simulations were carried out to ascertain the working of the proposed filters and the results are found to match with the theoretical results.

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