[IEEE 2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT) -...

2013 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2013]

Low Power, High Speed Hybrid Clock Divider Circuit

John Reuben, Mohammed Zackriya. V Sehool ofEleetronies Engineering, VIT University,

Vellore, lndia johnreuben@vit. ae.in, [email protected]

Abstract- The Clock Divider circuit has found immense

application in Multiple Clock Domain (MCD) systems like

ASICs, SoC and GALS. In MCD systems, we generate many

cIock signals of various frequencies from a high frequency cIock

by frequency division. Power is an important parameter to be

minimized since the nodes in a cIock divider circuit will toggle at

cIock frequency. In this paper, we present a low power hybrid

cIock divider circuit wh ich can take an input frequency up to 6 GHz and perform frequency division. The divider is hybrid

because it uses two different tlip flops - a Modified Extended

True Single-Phase Clock tlip flop (METSPC-FF) and a self

blocking FF (SBFF).The METSPC-FF is fast enough to divide a

GHz frequency, but consumes more power when compared to

SBFF, while the SBFF is relatively slow but consumes less power

compared to METSPC. We analyze the performance of these 2 FFs across PVT variations and implement them in a cIock divider

circuit. Our cIock divider circuit consumes 149.56 /lW power for

'divide by' 8 operation on a 6 GHz cIock. Simulation of these tlip

flops in TSMC 90 nm technology using CADENCE SPECTRE

simulator shows that they are very energy efficient and hence can

be used for other high speed applications without compromising

on the power.

Keywords: Clock Divider (CD); TSPC flip flop; Self blocking Flip

flop; propagation delay; power dissipation; Hybrid Clock

Divider(HCD); METSPC; ETSPC,PVT

I .INTRODUCTION

The Clock Divider circuit has found immense application in multiple clock domain(MCD) systems like ASICs, SoC(System on Chip) and GALS(Globally Asynchronous, Locally Synchronous).SoC, which is an IC designed by stitching together multiple stand-alone VLSI designs( called IPs) to provide full functionality for an application[l] has different IP blocks operating at different clock frequency. Clock generation and clock distribution for these MCD systems are the costliest in terms of power consumption [2].The clock generation system generates different frequencies for the clock domains from the basic crystal oscillator (tens of MHz) using PLLs(as frequency multipliers) followed by Clock Dividers. Hence minimizing the power consumption of the clock divider circuit is a crucial step in the design of Clock generator circuit for MCD systems.

978-1-4673-4922-2/13/$31.00 ©20 13 IEEE 935

Dr.Harish M Kittur Sehool ofEleetronies Engineering, VIT University,

Vellore, lndia kittur@vit. ae. in

In this paper, we present a low power hybrid clock divider circuit which can take an input frequency up to 6 GHz and perform frequency division. The divider is hybrid because it uses two different tlip flops - a modified ETSPC tlip flop (METSPC-FF) and self blocking FF (SBFF) [4]. The METSPC-FF is fast enough to divide a GHz frequency, but consumes more power when compared to SBFF below 1.5 GHz, while the SBFF is relatively slow but consumes less power compared to METSPC. The paper is organized as folIows: Section 11 describes the design of METSPC-FF and its simulation results in TSMC 90 nm . Section III describes the SBFF as presented in [4] and its simulation results in TSMC 90 nm (In [4], the SBFF is simulated in SMIC 65 nm technology).The hybrid clock divider circuit is presented in section IV with the simulation results. We conclude with possible future work in section V.

11 .MODIFIED ETSPC FLIP FLOP (METSPC-FF)

A. Basie ETSPC Flip flop A dynamic ETSPC flip flop is presented in [3], which

doesn't have stacked MOS structure that slows the switching speed.

S1 S2 Q

W/L=1.2

Fig. 1. ETSPC [3]

The ETSPC shown in Fig. 1 is a negative edge triggered flip flop. When the clock is high, NI and N2 will be on, P3 will be off. The node SI and S2 is precharged to low through NI and N2 irrespective of D state.

2013 International Conference on Circuits, Power and Computing Technologies [ICCPCT-20I3]

The evaluation phase starts at the negative edge of the clock.

Case 1: If D is low, PI will turn on to make node SI high

which in turn will turn off P2 to make node S2 stay low. Thus node S2 will turn off N3 to make node S3 (q) high and hence Q will become low.

Case 2: If D is high, PI will turn off to make node SI stay

low which in turn will turn on P2 to make node S2 high. Thus node S2 will turn on N3 to make node S3 (Q ) low and hence Q will become high.

B. Proposed Modified ETSPC Flip flop

The basis ETSPC [3] has delay of 36.34 pS and consumes 141.01 /lW power resuIting in a PDP of 5.12 fJ at 6 GHz (Nominal process corner). We propose a Modified ETSPC FF (Fig. 2) which has a better PDP as will be discussed below.

A B

W/L=1.2

Fig. 2. METSPC -FF

The proposed METSPC-FF is a posItIve edge triggered FF. It consists of precharge and evaluation phase as described. The clock signal (CLK) is generated on chip from the PLL and fed to the flip flops.

Precharge Phase:

When clk is low, transistor PI, P2 will be turned on and N3 will be turned off.

Case 1p: When D is low, NI will be turned off, thus node A

will be high through PI and it will turn on N2. Since the width of P2 is larger than N2 (resistance of P2 will be lesser than N2), node B will stay high through P2 irrespective of N2 being on or off.

936

Table 1. State of nodes at Precharge Phase

Q'-l Case Clk Dt A B Q, Q, 0 Ip 0 0 1 1 1 0

1 2p 0 1 0 1 0 1

1 Ip 0 0 1 1 0 1

0 2p 0 1 0 1 1 0

Case 2p: When D is high, NI will be turned on, thus node A

will discharge through NI and it will turn off N2, therefore node B will stay high through P2.

Since both P3 and N3 will stay turned off in precharge phase, Q, and Q, will hold the previous state ['-I and Qt-l respectively even though the present state of D (Dt) changes as shown in Table 1.

Evaluation Phase:

When clk goes high, transistor PI, P2 will be turned off, N3 will be turned on and the node A and B will hold the precharge state as in Table.2

Table 2. State of nodes at Evaluation Phase

Case Clk Dt A B Q, Qt

Ie J 0 I 0 1 0

2e J 1 0 1 0 1

Case 1e: If D, is low at rising edge of the clock, A will stay

high but B will discharge to GND through N2 since P2 is off in evaluation phase. Thus node B will turn on P3. The node ij, will stay high as the width of P3 is larger than N3 (resistance of P3 will be lesser than N3). Therefore Q, will become low.

Case 2e: If D, is high at rising edge of the clock, A will stay

low and B will also stay high since N2 is off. Thus node B will turn off P3. The node Q, wi 11 be discharged to GND through N3. Therefore Q, will become high.

The simulation results showed that METSPC flip flop has delay of 20.03 pS and consumes 88.74 uW power resulting in a PDP of 1.77 fJ at 6 GHz (Nominal process corner) which is better than ETSPC tlip flop. Hence it is more suitable for high frequency (GHz) operation. The cut-off frequency of MOSFET in TSMC 90 nm is around 120 GHz[9].


25

24

(j) e23 >co Q; 22

Cl c: 021 � Cl �20 e 0.. 19

18

-........ .---*' "...,-- --....

npl," ....... Power Dissipation

1.5 2.5 3 3.5 4 4.5

Frequency (GHz)

�-"\. \ \

5.5 6

100

90

80 � 70 2-

c: 60 2

co 50 .9-

<J> 40 i5 30 Q;

:;: 20 � 10

o

Fig. 3. CIk to Q propagation delay of METSPC-FF Vs. frequency

Fig.3 shows the variation of propagation delay and power dissipation W.r.t frequency which are as expected. To make sure that our FF design is insensitive to process variations, we did extensive simulation of our design across all process corners for various frequency. We have plotted the average propagation delay of our FF across all corners in Fig.4. The propagation delay of our FF averaged over all corners turns out to be 23.48 pS, (NN-Nominal, FF-Fast NMOS,Fast PMOS, FS-Fast NMOS, Siow PMOS,SF-Slow nMOS, Fast PMOS and SS-Slow NMOS and Siow PMOS).

35 'ß:30 >-� 2S

Cl c: �20 Cl �lS e 0.. �10 [!! � 5

o

!

• ss

• • ; FS

Process Corners

Fig.4. Average propagation delay of METSPC-FF across all corners

120 �---------------------------------------

!100 +-----�.�--------------------------------§ FF . � 80 +------------7FS�----�.�------------------.� NN • o 60 +-------------------------�F�----��-----Q; ",F • � � 0.. 40 +-------------------------------��-----Q) Cl [!! Q) 20 +----------------------------------------�

o L-______________________________________ _

Process Corners

Fig.5. Average power dissipation of METSPC-FF across all corners

937

Sirnilarly, we have plotted the average power dissipation of our FF across all corners in Fig.5.The average power dissipation of our FF averaged over all corners turns out to be 76.44 f.1W. The average PDP averaged over all corners is 1. 794 fJ.

III. SELF BLOCKING FLIP FLOP (SBFF)

A. Basic Self blocking Flip flop

A single phase clocked flip-flop, SBFF is proposed in [4], where the authors claim that their FF has better powerdelay product than even the most recent Sense Amplifier FF. To verify the claims of SBFF, we simulated it in TSMC 90 nm and optimized the W /L ratios for proper functionality.

Fig. 6 SBFF [4]

The SBFF consist of a dynamic XOR gate in the first stage and a differential storage latch in second stage. The slave latch is controlled by the X and clk signal from the XOR gate.

When clk is low, the node X is precharged and N7 is turn off, thus the slave latch is opaque to changes in D. At the positive edge of the clk, signal X is evaluated to D EE> Q.

Casel: When the present state D and previous state Q are

same (Dt EE> Qt-I = 0), node X discharges through NI. Which in turn will hold N6 off; this will prevent data from entering into storage latch as the previous data is unnecessary to be changed.

Case2: When the present state D and previous state Q are

different (Dt EE> Qt-l = 1), node X will hold the VDD state. Thus both N6 and N7 will be turned on.

When the present state is high (Dt=I), N8 will be turned on, which will pull Q to high (Qt= l) through P5. Since


Qt is high, N10 is turned on making Qt zero. If present state is low (Dt= O), N9 will be turned on (since Dt= l), which will pull Qt to high (Qt= O) through P4. Since Qt is high, NIl is turned on making Qt zero. Thus SBFF will hold the value Qt and Q t through the differential latch setup in the evaluation stage. Once the Q and D become same, signal X will discharge through NI to GND. Hence changes in D after the positive edge of the clock will not affect Q.

After extensive simulation of SBFF with optimized W /L values shown in Fig.6, we realized that this SBFF has lower PDP than METSPC at frequencies below 1.5 GHz. But SBFF fails to function as a flip flop above l.5 GHz due to setup time constraints. Hence, we concluded that SBFF is a better option for sub 1.5 GHz operation.

120

100 ifi S 80 >ro � 60 c o � 40 Cl ro Cl. e 20 a..

o

"' / -- J -

--- ./ ---

___ Propagation Delay ....... Power Dissipation

100 200 400 500 600 800 1000 1200 1400 1500 Frequency (MHz)

14

12 �

102-c o

8 � Cl. "00

6 6 4 �

o

o a..

Fig.7. Clk to Q propagation delay of SBFF Vs. frequency

Fig.7 shows the variation of propagation delay and power dissipation W.f.t frequency of SBFF which are as expected. Since the authors in [4] didn't check their FF for process insensitivity, we verified the functionality of the SBFF across all process corners for frequencies below l.5 GHz. We have plotted the average propagation delay of SB FF across all corners in Fig.8.The average propagation delay of SBFF averaged over all corners turns out to be 89.80 pS.

180 $160 S iU'140 a; 0120 c: 2100 '" 0> � 80 2 a.. 60 Q) 0> � 40 � 20

o

.!

• SF

• SS

• "bi

• FS

Process Corners

Fig. 8. Average propagation delay of SBFF across all corners Similarly, we have plotted the average power

dissipation of our SBFF across all corners in Fig.9.The

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average power dissipation of SBFF averaged over all corners turns out to be 76.44 /.I. W. The average PDP averaged over all corners is 0.577 fJ.

9

• FF

• • ... ·u NN SF

:�

o Process Corners

Fig.9 Average power dissipation of SBFF across all corners

B. Comparison ofthe two Flip Flops

Compared to the average PDP of METSPC which is l.794 fJ, the average PDP of SBFF is 68% lesser, except that it can function only at frequencies less than l.5 GHz. The PDP of METSPC-FF is higher because the power consumption is high due to short circuit current flowing in the direct path between V DD and GND during the precharge phase.

IV. HYBRID CLOCK DIVIDER (HCD)

To divide high frequency signal we are proposing a hybrid CD structure as shown in Fig. 10. We have used METSPC-FF in fust stage since it has got lesser propagation delay than SBFF at higher frequencies. The second stage of the CD uses SBFF because it has got lower PDP than METSPC for frequencies lesser than 1.5 GHz. The fust stage of the CD is used to convert the high input clock frequency to a sub-l.5 GHz frequency. Then the second stage can implement the required 'divide-by-n' operation using SBFF.

F CD CD F2 = F1 � F1 = Fix using using I---

METSPC-FF SBFF

Fig. 10. Hybrid Clock Divider Structure

For illustration consider the HCD shown in Fig. 12 which does "divide by 8" operation on a 6 GHz clock. We use two METSPC-FFs to obtain 1.5 GHz clock ("/4") in fust stage and one SBFF in the second stage to obtain 750 MHz clock ("/8").

Ix


�':[]DDDQDDDn �'l!D� �\ �f�\ �LH�' \��f�\ �o �ilU: \ [GHz \ 0 �'�j:D��, ��,��\�7�50_M�H:_Z: __ �: __ �,: __ �: __ �: __ �: __ �:�, �-----.-----ln 1.0 2.0 10 4.0 �o 4.5137n5 I 603.956mV time (n5)

Fig. 11 Simulation result of Hybrid CD for 6GHz TSMC 90 nm technology using CADENCE SPECTRE simulator

First State Second Stage r"-" -" -" -" -" -" -" -" -" -" -' r" -" -" -" -" -'"

D Q METPC-FF

Q

CLK f/2

D Q METPC-FF

Q

D Q SBFF

Q

Fig. 12. Hybrid Clock Divider Circuit for 'divide by 8'

Performance ofCD under PVT variation

Since we verified the functionality of METSPC (upto 6 GHz) and SBFF (upto 1.5 GHz) for process variations (at all 4 corners), we conclude that the CD implemented using these two flip flops will be insensitive to process variations. To evaluate our CD circuit under PVT variation, we continue to evaluate our CD across the other 2 parameters viz., voltage, V DD and temperature.

The nominal supply voltage for our flip flop and CD was 1.1 V. To make sure that our CD is insensitive to variation in V DD, we varied V DD for ± 0.2 V deviation. Our CD was insensitive to V DD variation of ± 0.2 V and behavior of propagation delay and power dissipation for VDD variation at 6 GHz is plotted in Fig.13

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250 T'""----------------� 300

Vi 200 .\--...::!!::::!::::� .... __ -------......".....!_ 250 � 3 � � 200 c 1 1� � � ��

� 100 +----��=-==�--------� � � 100 � � � � 50 + ...... ----------------� 50 � Propagation Delay (pS)

...... Power(uW) O +--r--r---r---;r_.____.__-r--r�__.r_.____.__""T"_y__+O 0.9 0.957 1.014 1.071 1.129 1.186 1.243 1.3

VDD(V) Fig.13. Plot of propagation delay and power dissipation over

range Of VDD

The nominal temperature at which we simulated our flip flops was 27 oe . To make sure that our CD is insensitive to variation in temperature, we varied temperature from 0 to 70 oe . Our CD was insensitive to temperature variation. The behavior of propagation delay and power dissipation for temperature variation at 6 GHz is plotted in Fig.14.

250 T'""----------------"""T 160

t��::s;�;:;;:::e::=-= ..... ,...... ..... II::::I!::�9 155

Vi� � � 150 2-� c � 150 +------....::-===-..... .::::----------i... 145 � c � o .� � 100 +---------------:: ....... -----f 140 5 � 1� I e ,. � 50 f1. ...... Propagation Delay (pS)

o ...... Power(uW)

o 5 10 15 20 25 30 35 40 45 50 55 60 65 70 Temperature (degree C)

130

125

Fig.14. Plot of propagation delay and power dissipation over range Of VDD


Fig.15. Layout of divide by 2 using METSPC -FF

1.25 c

1.0

.75 2: >

.5

.25 6GHz 0.0 1.25 'v

3GHz - . 25+-��-_� ____ -_�-____ �_�� _______ -__ -__ -_�-��-----j

o .25 .5 .75 1.0 1.25 1.5 93.1223ps I 906.89SrrN I time (ns)

Fig.16. Post-Layout simulation of divide by 2 using METSPC -FF for 6 GHz

Simulation of this hybrid CD in TSMC 90 nm technology using CADENCE SPECTRE simulator is shown in Fig.ll. For a divide by 8 operation on 6 GHz clock, our hybrid CD consumes average power of 149.56 f.lW considering all PVT variation. The average propagation delay through the entire divider is 19l.34 pS across all PVT variation. Table 3 shows the comparison of our clock divider with the recent clock dividers in literature. The layout of a divide-by-2 circuit using METSPC-FF and the post layout simulation waveforms for a divide-by-2 operation on a 6 GHz clock are shown in Fig.15 and Fig.16 respectively.

T bl 3 P D f I k d" d a e er ormance companson 0 vanous c oe lVI ers Ref. Tech VDD Operating Power

(f.lm) (V) Frequency (GHz) (mW/GHz)

[7] 0.09 l.l 2.4 0.190

[8] 0.18 l.8 5 2.4 This work 0.09 l.l 6 0.024

940

V.CONCLUSION

The proposed METSPC-FF is designed to reduce power consumption and propagation delay at high frequency operation. The self blocking FF presented in [4] is indeed verified to be energy efficient since it has lowest power delay product till 1.5 GHz. Both the flip flops and the resulting CD circuit are simulated across PVT variations to ensure the reliability of the design. These two flip flops can be judiciously used to design a high speed, low power clock divider circuit. We have verified this by being able to "divide by 8" a 6 GHz clock, the entire operation consuming only 149.56 f.lW. Except for the propagation delay, the CD circuit does not alter the clock waveform and maintains the 50% duty cycle of the input clock. Hence they can be used directly by the IP blocks in a Soc. We have also done the post-layout simulation of CD using METSPC-FF and verified that they match closely with the transistor level simulation results.


REFERENCES

[1] R. Rajsuman, "System-on-a-chip: Design and Test", Artech House Inc. Publishers, 2000,pp.3-7.

[2] R. Y. Chen, N. Vijaykrishnan, and M. 1. Irwin, "Clock power issues in system-on-a-chip designs," in Proc. IEEE Workshop on VLSI, 1999, pp.48-53.

[3] Xiao Peng Yu, Manh Anh Do, Wei Meng Lim, Kiat Seng Yeo, and Jian-Guo Ma, "Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler" IEEE Transactions On Microwave Theory And Techniques, Vol. 54, No. 11, Pp. 3828-3835, November 2006.

[4] X. Li, S. Jia, X. Liang and Y. Wang, "Self-blocking flipflop design", Electronics Letters, Vol. 48, No. 2, 19th January 2012.

[5] 1. N. Soares, Jr. and W. A. M. Van Noije, "A 1.6-GHz dual modulus prescaler using the extended true-single-phaseclock CMOS circuit technique (E-TSPC)," IEEE J. SolidState Circuits, vol. 34, no. 1, pp. 97-102, Jan. 1999.

[6] Wu-Hsin Chen and Byunghoo Jung, "High-Speed LowPower True Single-Phase Clock Dual-Modulus Prescalers ",IEEE Transactions On Circuits And Systems-li: Express Briefs, Vol. 58, No. 3, pp. 144-148, March 2011.

[7] Stephan Henzler and Siegmar Koeppe, "Design and Application of Power Optimized High-Speed CMOS Frequency Dividers," IEEE Transactions On Very Large Seale Integration (VLSI) Systems, vol. 16, no. 11, pp. 1513-1520, November 2008.

[8] Chih-Wei Chang and Yi-Jan Emery Chen," A CMOS True Single-Phase-Clock Divider With Differential Outputs," IEEE Microwave And Wireless Components Letters, vol. 19, no. 12, pp. 813-815, December 2009.

[9] Kuang-Yu Cheng et al, "Development of 90nm InGaAs HEMTs and Benchmarking Logic Performance with Si CMOS," Compound Semiconductor Integrated Circuit Symposium (CSICS), 2010 IEEE , vol., no., pp.I-4, 3-6 Oct. 2010

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John Reuben holds a B.E.,(Honors') degree in Electrical and Electronics Engineering from BITS,Pilani and M.Tech in Communication Engineering from VIT University, Vellore. He is currently Assistant Professor with VIT University, Vellore where he is pursuing his PhD.

Mohammed Zackriya. V was born in Vellore, India. He received B.E., degree in Electronics and Communication Engineering from Anna University, Chennai. He is pursuing M.S (By Research) in the School of Electronics Engineering ,VIT University, Vellore .

Dr. Harish M Kittur (M'10) was born in Gadag, India. He received - B. Sc. Degree in Physics, Mathematics and Electronics from the Karnataka University, India, in 1994. M.Sc. in Physics from the Indian Institute of Technology, Mumbai, in 1996. M. Tech. in Solid State Technology in the year 1999 from the Indian Institute of Technology, Madras, and Ph. D. in Physics from the RWTH Aachen, Germany in the year 2004.

He is currently Professor with VIT University, Vellore, India and heads the VLSI Division. He has published 8 papers in International Journals and 8 papers in International Conferences. His research interests are Low Power VLSI Design, Memory Design and Nanoelectronics. He is a life member of IETE and member of IEEE.

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