A 1.52 uJ/classification Patient-Specific Seizure Classification Processor using Linear SVM Muhammad Awais Bin Altaf and Jerald Yoo

Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates {mbinaltaf, jyoo}@masdar.ac.ae

Abstract— This paper presents an 8-channel electroencephalograph (EEG) classification processor for seizure detection and recording. To integrate 8 channels, an area- and energy-efficient filter architecture using Distributed Quad-LUT (DQ-LUT) is proposed, which reduces area by 64.2% with minimal overhead in power delay product. The on-chip patient specific classification with a Linear Support-Vector Machine (SVM) results in 82.7% seizure detection accuracy with a 2 second latency using the CHB-MIT EEG database [1] . The overall energy efficiency is measured as 1.52μJ/classification while operating at 8 channel mode.

I. INTRODUCTION Epileptic seizures occur from disorders in the central nervous system. For proper treatment of seizure, an energy-and area-efficient on-chip classification is essential since the power and area utilization are the most stringent constraints in the small form factor sensor implementation. Moreover, patient-to-patient variations in seizure onset EEG pattern makes the design particularly challenging and adopting the patient-specific classification is essential [1]. [2] consumes large area and power due to the extensive processing operations that are required to detect abnormality using EEG/EKG signals. On-chip feature vector extraction for the seizure detection was done in [2], and it transferred the extracted vector wirelessly for further analysis and classification at the software level; however, it did not include on-chip classification or recording, and it only included a single channel. Several generic bio-signal processors were proposed for EEG and EKG [3], [4], but neither of them had on-chip classification, which is a must to fulfill the requirements of wearable, continuous health monitoring sensor. [5] presented a single channel intracerebral EEG(icEEG) based on-chip seizure detector, but it lacks patient specific detection, and maximum latency of 20 sec from the 7 tested results puts a bottleneck on implementing a real-time system. This work presents an 8-channel EEG processor for seizure detection with feature extraction and classification integrated on a chip [6] , [7] with on-chip storage for capturing raw EEG during seizure onset with maximum latency of less than 4 sec. Fig.1 shows the EEG signal processing flow. This work focuses explicitly on processing of digitized EEG data for the seizure detection. Therefore, the task is to classify seizure affected EEG data based on the extracted feature vector using machine learning algorithm with recording function to store the seizure-affected EEG data for further analysis.

II. SEIZURE DETECTION ALGORITHM Development of seizure detection algorithm started in early 80’s with the initial focus on rhythmic activity of dominant

frequency component in 3 to 20 Hz range [8] with 50% Detection Rate (DR). Patient non-specific and specific seizure onset detector were developed in software using wavelet decomposition, EEG’s average amplitude and rhythmic dominant frequency based on both probabilistic [9] and deterministic models [10] with reported classification accuracy as 78% and 95% respectively. Later on, machine learning based algorithms were developed with seizure specific approach [11] in order to adapt to patient-to-patient variation, but all of them were only implemented at software level. Also, most of the above reported either moderate or high latency (> 10 seconds), which is not acceptable in real-time applications- that is, when combined with neural stimulator to suppress seizure, the latency should be less than 2 second. Moreover, these algorithms does not take into account seizures whose onsets lack the development of rhythmic activity, i.e. physical sequence such as eye-fluttering, which will lead to detection error and reduce the DR. Taking into account such cases, apart from spectral and spatial variation, the temporal variation, which is the relation of current feature vector (FV) with recent past FVs must be analyzed as well [1], [6] , [7] . Hence, the multichannel spectral energy calculation using filter bank evaluated over certain time duration is adopted [6] , [7] with linear SVM as a classifier to optimize the energy efficient hardware implementation without hampering the accuracy significantly and with minimum latency.

III. FEATURE EXTRACTION ENGINE Feature Extraction Engine extracts the discriminating feature vectors from the EEG data for seizure detection. The spectral distribution of rhythmic activity of seizure onset comprises of multiple frequencies, characterized by dominant and non-dominant frequency components varying among patients. Seizure onset variation among patients based on dominant and non-dominant frequency components is shown in Fig. 2. In addition, the spectral distribution of seizure onset also varies among electrode positioning, and features from only single electrode position can lead to significant errors in the classification accuracy. That’s why in order to account for the

Fig. 1: EEG data processing flow.

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Fig. 2: Seizure onset variation in the spectrum of patients [1]

spectral and spatial components, the inter spectral energy for the duration of 2 second is calculated using multi-channel filter bank approach to form a temporary feature vector, XT. Moreover to accommodate the temporal variations, overall feature vector is formed by concatenating the current XT with two previous FVs i.e. XT-2 and XT-4 to form a non-overlapping 6 sec sliding window (Fig. 3), where XT captures the low amplitude activity and XT-2 and XT-4 captures the high amplitude and spike respectively to also detect seizures onsets without rhythmic activity.

Fig. 3: Feature Vector formation considering the temporal variation. A. Single Channel In each channel, a decimation block, a filter bank composed of 7 Band Pass Filters (BPFs) and a spectral energy calculator is used for the feature extraction. Decimation filter comprises of an antialiasing filter and a 32 factor down sampler to reduce the processing cost. The filter bank parameters are specified in TABLE I. The filters are Type-II FIR with an order of 43, which is an optimized order based on the Least square design technique to ensure minimum stop band attenuation without affecting the classification accuracy results. The resulting impulse responses are symmetric, thus sharing the coefficient multiplications becomes possible, and MAC blocks can be reduced to half.

TABLE I: Filter Specification of Filter Bank

B. Multi-channel Integration of 8 channel feature extraction is limited by area, and if we adopt conventional implementation [2], the resources consumed by filter bank will reach up to 87% of total chip area (Fig. 4); as conventional digital filter relies heavily on MAC operation with multipliers which takes significant portion. To overcome this, we propose a

Distributed Quad Look-Up Table (DQ-LUT) which is more area and energy efficient as compared to the conventional MAC-based filter architecture. By the usage of DQ-LUT the overall logic gates of feature extraction engine reduces from 95160 to 18728 as compared to the parallel implementation.

Fig. 4: Feature Extraction Engine

Fig. 5: (a) Conventional and implemented filter architecture, and (b)-(e) the comparison between the architectures.

The proposed DQ-LUT is shown in Fig. 5(a), along with a conventional approach. The comparison graph of power, area, power delay and area power delay is shown in Fig. 5(b), (c), (d) and (e), respectively, synthesized in TSMC 0.18um process and simulated using Modelsim. The DQ-LUT exploits the LUT input instead of area-consuming multipliers to minimize the resources and power consumption [12] ; by splitting LUT into 4b slices which shows the optimal result. This results into the maximum power reduction of 86.5% as compared to the conventional MAC-based architecture with 30% power delay overhead.

IV. CLASSIFICATION ENGINE Machine-learning based patient specific classifier is used for the classification purpose, because of the person to person variations in the seizure onset EEG pattern. In the implemented processor, on chip machine learning classifier is employed with an off-chip training. To optimize the patient-specific decision boundary between seizure and non-seizure,

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the Linear SVM classifier is employed. In the Linear SVM, the classification is done as (1):

W . 0 0 1

where in (1), W (the normal vector to the hyper-plane) and β (determines the offset of hyper-plane, i.e.β/||W||) are the patient-specific parameters and K(x) is the incoming feature vector extracted from the incoming EEG data. The feature vector ‘K(x)’ and normal vector ‘W’ are 7 dimensional vectors in the implementation, separated by a 6 dimension hyperplane for classification. The block diagram of the Classification Engine (CE) using linear SVM based on spectral energy calculation is elaborated in Fig 6. In this implementation, the patient specific learning is done off chip using SVM training, and the actual classification is done on-chip at real time. The resource sharing in SVM realization block for filter banks and multiple channels is adopted to reduce the area (Fig. 7). Floating point multiplication and addition operations are performed to compute the seizure info. Also, a 14 bit custom IEEE 754 floating point standard format is used with 5 exponent bits and 8 fractional bits to cover the computation range with optimized precision.

Fig. 6: Classification Engine.

In addition, for the variability and error accommodation programmable dwell time of 2 and 4 second is introduced, which can be programmed depending on the specific patient.

Fig. 7: Resource sharing in CE implementation.

The CE generates the output Seizure Info at 128classifiers/s. Seizure DR based on the linear SVM classifier is defined as in (2): DR # of seizure classifiersTotal # of classifiers during seizure 2

where the DR is the ratio between the number of “seizure” classifiers and the total number of classifiers processed during the seizure onset period. This definition for DR is pessimistic as compared to [5] which calculate the sensitivity based on number of seizure “events”, not based on number of “seizure classifiers”.

V. RECORDING ENGINE In case of seizure, for further analysis by concerned physician, the processor records the raw EEG data for pre-defined programmable period (8~32 sec) depending on the specific patient to optimize the storage space utilization. During the storage period, the classification processor is by-passed to save power consumption and abnormal EEG data is stored in a 64KB SRAM, embedded in the chip (Fig. 8).

Fig. 8: Recording Engine.

Apart from the storage function, there is an option for both wired and wireless data transfer: the wired (transferred using the SRAM control signal) or the wireless (TI CC2500 external memory I/F). Transmission of only seizure affected EEG data will reduce the communication power overhead.

VI. IMPLEMENTATION RESULTS The implemented system specifications and the 3x5mm chip micrograph is shown in Fig. 9. The overall power consumption for 8 channel seizure classification process is 195uW with 128 classification/sec. The chip is verified with the CHB-MIT Scalp EEG database [1],[13] , which contains 906 hours of EEG data for 23 epileptic patients with 198 seizure events in total. For testing the Xilinx Virtex 5 LX-110T FPGA board and Logic analyzers are utilized to upload specific patient EEG data and to display the seizure info along with debugging signals respectively. As a result, the seizure DR is 82.7% for 206 hours of on chip testing with false alarm of 4.5% (TABLE II) and latency of less than 2 second. This DR is based on (2) as opposed to the [5] DR definition where the sensitivity of 100% is reported for the detection of just one result during 13.5 sec window. The distribution of seizure DR and false alarm among the patients is shown in Fig. 10, with variation of 71 to 87% in DR and best false alarm of 2.5% among patients.

TABLE II: Classification results.

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Fig. 9: Implemented Features and chip micrograph.

Fig. 10: Detection rate and false alarm distribution among patients.

Fig.11: On chip seizure detection results.

The processor performance based on the CHB-MIT EEG database is shown in Fig. 11, where the seizure affected EEG data for the duration of 20 seconds is classified by the implemented seizure detection processor. The comparison with state of the art works along with implemented work is depicted in TABLE III.

TABLE III. Comparison.

This work is the first multi-channel, the most energy efficient on-chip patient-specific seizure detection, classification and recording processor.

VII. CONCLUSION We have implemented the first multi-channel seizure classification processor with on-chip feature extraction, classification and recording using linear SVM-based machine learning. The implemented seizure detection processor exploits the machine learning for patient-specific classification, and it adopts the DQ-LUT which is 47% more power delay area efficient as compared to conventional filter architectures. The linear SVM classification results in 82.7% DR and a 2 second latency with the overall energy consumption of 1.52μJ/classification.

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