[IEEE 2013 IEEE Energy Conversion Congress and Exposition (ECCE) - Denver, CO, USA...

8
Virtual Impedance Current Limiting for Inverters in Microgrids with Synchronous Generators Andrew D. Paquette, Deepak M. Divan School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA, USA [email protected] AbstractThis paper focuses on current limiting for voltage controlled inverters during overloads caused by poor transient load sharing between inverters and synchronous generators in islanded microgrids. The use of simple current reference saturation limiters can cause instability when the voltage regulator loses control after the current reference saturates. The use of virtual impedance for current limiting is shown to provide stable current limiting when operating in parallel with synchronous generators. Small signal analysis is used to set the virtual impedance magnitude and X/R ratio, and validation is provided by simulation and experimental results. I. INTRODUCTION Grid-supporting-grid-forming (GSGFm) control [1], where an inverter acts as a droop controlled voltage source, allows multiple grid-forming sources to operate in parallel in grid connected or islanded mode [1]-[5]. When synchronous generators and GSGFm inverters operate together in islanded mode, they exhibit poor transient load sharing, where the inverter picks up the majority of any load step [5]-[7]. This constrains the inverter rating to be able to handle the largest expected load step, and could negatively impact the life of battery energy storage inverters. It is possible to modify the inverter controls to improve the transient load sharing, but this comes at the expense of increased voltage and frequency transients [5]. Instead of trying to improve the transient load sharing by effectively slowing down the inverter, it is desirable to fully utilize the inverter by allowing it to provide as much support as possible and simply current limit when necessary. This takes advantage of the fast response characteristics of the inverter to improve power quality without overloading the inverter during transients, as well as protecting the inverter during faults. Current limiting is accomplished differently in single- loop and multi-loop voltage control, the two main types of inverter voltage control. Current limiting in single-loop voltage control methods is generally accomplished by reducing the voltage magnitude when the current exceeds a threshold, through a pre-defined droop relationship [8], or by a current limiting PI controller [9]. In multi-loop voltage control methods, the two main current limiting methods are to either limit the current reference [10]-[12], or to reduce the voltage reference with a virtual impedance [13]-[15]. This paper describes that when GSGFm inverters go into current limiting mode during overloads in parallel with synchronous generators, the use of simple current reference saturation limiters may cause instability. When the current reference saturates, the voltage controller is effectively disabled and loses control. The voltage and current controllers then ‘wind up’ as the inverter and generator frequencies deviate, and the system goes unstable. When operating a voltage controlled inverter in parallel with other voltage sources such as a synchronous generator, current limiting is not just as simple as limiting the current magnitude. It is important to address the interactions between the inverter and generator, and how the inverter enters and exits current limiting mode. Out of [8]-[15], only [8], [10], [11] address how to exit current limiting, and [8], [10] only consider a single inverter with a bolted fault, for which entering and exiting current limiting is very straight forward. Reference [11] addresses current limiting with inverters and synchronous generators, but uses a complicated control scheme. Additional discussion on [11] is provided in Section III.A. This paper examines the current limiting characteristics of multi-loop GSGFm inverter controls [1]-[4], specifically looking at current limiting during overloads caused by poor transient load sharing with synchronous generators. Section II describes the multi-loop dq GSGFm control, along with a proposed transient virtual impedance to eliminate steady state virtual impedance voltage drop. In Section III it is shown that the use of simple current reference saturation can cause instability when the voltage regulator loses control after the current reference saturates. Section IV proposes virtual impedance current limiting to eliminate the instability, and simulation and experimental results are provided. Finally, conclusions are given in Section V. 1039 978-1-4799-0336-8/13/$31.00 ©2013 IEEE

Transcript of [IEEE 2013 IEEE Energy Conversion Congress and Exposition (ECCE) - Denver, CO, USA...

Page 1: [IEEE 2013 IEEE Energy Conversion Congress and Exposition (ECCE) - Denver, CO, USA (2013.09.15-2013.09.19)] 2013 IEEE Energy Conversion Congress and Exposition - Virtual impedance

Virtual Impedance Current Limiting for Inverters in

Microgrids with Synchronous Generators

Andrew D. Paquette, Deepak M. Divan

School of Electrical and Computer Engineering

Georgia Institute of Technology

Atlanta, GA, USA

[email protected]

Abstract—This paper focuses on current limiting for voltage controlled inverters during overloads caused by poor transient load sharing between inverters and synchronous generators in islanded microgrids. The use of simple current reference saturation limiters can cause instability when the voltage regulator loses control after the current reference saturates. The use of virtual impedance for current limiting is shown to provide stable current limiting when operating in parallel with synchronous generators. Small signal analysis is used to set the virtual impedance magnitude and X/R ratio, and validation is provided by simulation and experimental results.

I. INTRODUCTION

Grid-supporting-grid-forming (GSGFm) control [1], where an inverter acts as a droop controlled voltage source, allows multiple grid-forming sources to operate in parallel in grid connected or islanded mode [1]-[5]. When synchronous generators and GSGFm inverters operate together in islanded mode, they exhibit poor transient load sharing, where the inverter picks up the majority of any load step [5]-[7]. This constrains the inverter rating to be able to handle the largest expected load step, and could negatively impact the life of battery energy storage inverters. It is possible to modify the inverter controls to improve the transient load sharing, but this comes at the expense of increased voltage and frequency transients [5]. Instead of trying to improve the transient load sharing by effectively slowing down the inverter, it is desirable to fully utilize the inverter by allowing it to provide as much support as possible and simply current limit when necessary. This takes advantage of the fast response characteristics of the inverter to improve power quality without overloading the inverter during transients, as well as protecting the inverter during faults.

Current limiting is accomplished differently in single-loop and multi-loop voltage control, the two main types of inverter voltage control. Current limiting in single-loop voltage control methods is generally accomplished by reducing the voltage magnitude when the current exceeds a threshold, through a pre-defined droop relationship [8], or by a current limiting PI controller [9]. In multi-loop voltage

control methods, the two main current limiting methods are to either limit the current reference [10]-[12], or to reduce the voltage reference with a virtual impedance [13]-[15].

This paper describes that when GSGFm inverters go into current limiting mode during overloads in parallel with synchronous generators, the use of simple current reference saturation limiters may cause instability. When the current reference saturates, the voltage controller is effectively disabled and loses control. The voltage and current controllers then ‘wind up’ as the inverter and generator frequencies deviate, and the system goes unstable.

When operating a voltage controlled inverter in parallel with other voltage sources such as a synchronous generator, current limiting is not just as simple as limiting the current magnitude. It is important to address the interactions between the inverter and generator, and how the inverter enters and exits current limiting mode. Out of [8]-[15], only [8], [10], [11] address how to exit current limiting, and [8], [10] only consider a single inverter with a bolted fault, for which entering and exiting current limiting is very straight forward. Reference [11] addresses current limiting with inverters and synchronous generators, but uses a complicated control scheme. Additional discussion on [11] is provided in Section III.A.

This paper examines the current limiting characteristics of multi-loop GSGFm inverter controls [1]-[4], specifically looking at current limiting during overloads caused by poor transient load sharing with synchronous generators. Section II describes the multi-loop dq GSGFm control, along with a proposed transient virtual impedance to eliminate steady state virtual impedance voltage drop. In Section III it is shown that the use of simple current reference saturation can cause instability when the voltage regulator loses control after the current reference saturates. Section IV proposes virtual impedance current limiting to eliminate the instability, and simulation and experimental results are provided. Finally, conclusions are given in Section V.

1039978-1-4799-0336-8/13/$31.00 ©2013 IEEE

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II. MULTI-LOOP DQ VOLTAGE CONTROL

A. Basics

Multi-loop voltage control uses an outer voltage loop that provides the current reference to an inner current loop. In grid-supporting-grid-forming controls, the voltage reference and frequency are given by voltage and frequency droop [1]. The multi-loop dq voltage control used in this work is shown in Fig. 1. The voltage reference and frequency are given by conventional voltage and frequency droop. Virtual output impedance is added by subtracting the voltage drop across a virtual resistance, RVI, and virtual inductance, LVI, from the voltage reference. The virtual impedance voltage drop is given by (1)-(2). The outer voltage loop includes output current feed-forward (with gain H) [2], [3], [11]. Other feed-forward and compensation terms were investigated in this work (specifically voltage feed-forward and decoupling terms in the current controller, and filter capacitor current compensation in the voltage controller [2], [3], [11]), but have been omitted because small signal analysis indicated they had negligible impact on any of the important modes. Also, in the presence of significant measurement noise in the experimental setup, some of the compensation terms significantly degraded performance by feeding forward noise into the current and voltage commands.

oqVIodVIVId iLiRv , (1)

odVIoqVIVIq iLiRv , (2)

B. Transient virtual impedance

Virtual impedance can be used for controlling the output impedance, to improve stability, and for current limiting [1], [4], [13]-[15]. In inverter-based microgrids, impedance has a significant impact on stability, and virtual impedance has been used to provide stable operation [1].

Virtual output impedance degrades voltage regulation due to steady state voltage drop across the virtual impedance. It has been proposed to use a supervisory control (or tertiary control [1], [16]) to change adjust each source’s voltage reference to compensate for virtual impedance voltage drops. However, when operating in parallel with a synchronous generator, a steady state voltage drop causes significant reactive power sharing error, because the generator’s automatic voltage regulator (AVR) does not include a steady state voltage drop. To avoid the need for a central controller to continuously modify all of the voltage references, a variation on the conventional virtual impedance is proposed.

This work proposes using a transient virtual impedance, wherein a high-pass filtered version of the dq output current is used for the virtual impedance, as given by (3)-(4), where ωc,hpf is cutoff frequency of a single-order high-pass filter. The positive sequence fundamental component of the current is constant in the synchronous dq frame, and thus the positive sequence fundamental virtual impedance voltage drop will decay to zero in steady state. This allows the

Fig. 1. Multi-loop dq grid-supporting-grid-forming control with

virtual impedance and output current feed-forward.

virtual impedance to impart the necessary stabilizing effects without the steady state voltage drop.

)/()/( ,,, hpfcoqVIhpfcodVIVId ssiLssiRv (3)

)/()/( ,,, hpfcodVIhpfcoqVIVIq ssiLssiRv

(4)

It should be noted that in this work the inverter uses an output transformer, and the voltage drop across the transformer is not currently being compensated. The extra output impedance from the transformer causes steady state reactive power sharing error. If it is desired to compensate for the voltage drop across the output transformer, a slower, extra outer voltage loop may be used to modify the primary voltage loop’s reference to slowly restore the transformer output voltage to the droop set point. In the case of an extra outer voltage loop, transient virtual impedance is not necessary, since the outer loop will compensate for the voltage drop across both the virtual output impedance and the transformer impedance.

III. CURRENT LIMITING IN MULTI-LOOP INVERTER

CONTROLS

A. Current reference saturation

The multi-loop voltage control in Fig. 1 has inherent current limiting ability due to the use of current regulators. Assuming the current regulators have sufficiently high bandwidth, the current can be limited simply by limiting the current reference, iLd* and iLq*.

With current controlled inverters, i.e. grid-feeding control [1], the phase-lock-loop (PLL) tracks the grid voltage phase angle and aligns of the dq transformation angle with the grid voltage, such that the d and q axis currents correspond to reactive and real current, respectively. The multi-loop GSGFm strategy in Fig. 3 aligns the q-axis with the output voltage by setting the d-axis voltage reference to zero and the q-axis voltage reference to the desired voltage magnitude. In a grid-feeding inverter the PLL maintains phase angle alignment even during current limiting (except for some transient error). However, with GSGFm control the output of the voltage regulator(s) saturate once current limiting starts, and the voltage regulators are not necessarily able to keep the q-axis aligned with the output voltage (or grid voltage). While the current magnitude is effectively controlled, the alignment of the d and q-axis are not maintained. This allows the phase

PQ Calc, Filt

P -mP 1/s θ+

ω0

+

Q

L

CiLq

+

-

dq

αβ

θ

SVMPI

6

+

iL

iovo

-mQ

+V0

+V*

++PI

++PI

voq-

+

Hioq

iLq*

iLd*PI

vod*

voq*

+ -

+0

V*

vq,VI

vod-

iLd

-

P=(voqioq+vodiod)ωc/(s+ωc)

Q=(voqiod-vodioq)ωc/(s+ωc)

iL,abc

vo,abc

io,abc

abc

dq

θ

iLd

iLq

abc

dqvod

voq

abc

dqiod

ioq

+

Hiod

-

vd,VI

1040

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angle to drift, and if another voltage source is present with a different frequency, such as a generator whose frequency is transiently dipping following a load step, the frequencies may diverge causing the dq voltages to ‘wind up.’ This problem is illustrate through a simulation in Section III.B.

Reference [11] uses a hybrid between grid-forming and grid-feeding control, and thus may not suffer from the instability described above. In [11] the dq transformation angle is provided by a PLL as in grid-feeding control, but there are extra regulation loops that attempt to drive the frequency and phase angle to that given by the droop frequency (similar to GSGFm control). Since the PLL tracks the output voltage phase angle, during current limiting the inverter dq transformation angle should not drift from the output voltage angle. However, the control in [11] is very complex, with many extra regulation loops. The control proposed in this paper has the advantage of significantly reduced complexity.

B. Simulation

The system diagram for the experimental microgrid setup is shown in Fig. 2. The inverter has an output delta-wye transformer to supply single phase loads with a three-wire inverter. The inverter uses the control in Fig. 1 and the generator uses the control in Fig. 3. The generator controls are standard PID control for the governor and voltage regulator, with droop implemented by biasing the voltage and frequency references.

The response of the baseline controls (without current limiting) to the application of a 21 kW, 0.9 power factor linear load is shown in Fig. 4. The inverter initially picks up most of the load step, and the current reaches 1.89 pu. In Fig. 5 the same load step is applied, except with the current reference saturation limiters set at +/-1.06 pu (Imag =

22 06.106.1 = 1.5 pu). The q-axis current limit saturates

first, and as the q-axis voltage drifts, the output voltage alignment drifts and the d and q axis currents no longer correspond to real and reactive power. This causes the generator voltage and frequency to change. As the inverter and generator frequency deviate, the inverter d and q-axis voltage begin to ‘wind up’ and oscillate at a frequency equal to the difference between the generator and inverter frequency. As the sign of the d and q axis voltage error changes, the current reference flip-flops between positive and negative limit, and the voltage regulators never regain control.

IV. VIRTUAL IMPEDANCE CURRENT LIMITING

Virtual impedance can be used increase the inverter’s output impedance during transients and thereby limit the current [13]-[15]. While normal current limiting works by limiting the current reference, virtual impedance current limiting works by reducing the voltage reference, thereby preventing the voltage controller from commanding an excessively large current reference. During current limiting the voltage controller output does not saturate, and the instability observed in Fig. 5 is avoided.

Fig. 2. Diagram of experimental microgrid setup

Fig. 3. Control diagram for synchronous generator with droop.

Fig. 4. Simulation of base case response to application of 21 kW, 0.9

power factor load without current limiting.

IMSG

Speed Encoder

12.5 kW

208 VL-L

25 hp, 460V 20 hp, 480V Drive

Default Controller

Diesel Engine Emulator

480 V 3ph

Utility

1 Ω

9.25 mH2.5Ω

480V Drive w/ rectifier

& dc chopper

NI cRIO Controller

20 Ω,15 µF 5 µF

1.4 mH

480 V 3ph

Utility208/380 V

Y Δ

11.1 kVA Inverter with Rectifier Input to Emulate

Energy Storage or Fast-Responding Energy Source

+

-f0

P-mP

+

fbias

PIDthrottle*

(torque)

+

+V0

-

Vbias

VfieldPwrAmp

Q-mQ

SGEnginefshaft

AVRVterminal,RMS

Gov

Generator set

PQ

Calc

Controller

IVPID

0

1

2

Real

Pow

er,

pu

0

1

Reactiv

eP

ow

er,

pu

58

59

60

Fre

quency,

Hz

0.8

1

Volta

ge, pu

0

0.1

Volta

ge, pu

1 1.5 2 2.5

0

1

2

Curr

ent, p

u

Time, s

Gen

Inv

vq*

vq

vd*

vd

iq

id

|idq|

1041

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Fig. 5. Simulation of response to application of 21 kW, 0.9 power factor

load with current limiting, showing instability caused by current reference saturation limiters.

When the current magnitude exceeds a threshold, additional virtual impedance is added. The total virtual impedance is given by (5), and consists of a nominal virtual impedance, RVI

0, and LVI

0, plus a current limiting virtual

impedance, ΔRVI and ΔLVI. This is the same as in [14]. The expressions for ΔRVI and ΔLVI are given in (6)-(7), where kp,Rvi, ΔX/R, and Ithresh are the current limiting virtual resistance proportional gain, current limiting virtual impedance X/R ratio, and current limiting threshold, respectively. ΔX/R is used to set the ratio ωΔLVI/ΔRVI.

VIVIVI RRR 0 , VIVIVI LLL 0

(5)

)0,max( 2

,

2

,, threshrefLqrefLdRvipVI IiikR

(6)

)0,max( 2

,

2

,, threshrefLqrefLdRvipVI IiiRXkL (7)

For current limiting, transient virtual impedance is undesirable because the virtual impedance voltage drop decays with the high-pass filter time constant. Therefore, in this work, transient virtual impedance is used for ZVI

0, but

normal (not high-pass filtered) virtual impedance is used for ΔZVI. The final expression used in this work for the virtual impedance voltage drop is given by (8) and (9). Note that (6)-(7) use iLdq,ref for the current magnitude calculation instead of iodq because using iodq was found to cause significantly more oscillatory behavior.

oqVIodVIhpfcoqVIhpfcodVIVId iLiRssiLssiRv )/()/( ,

0

,

0

, (8)

odVIoqVIhpfcodVIhpfcoqVIVIq iLiRssiLssiRv )/()/( ,

0

,

0

, (9)

A. Setting Current Limiting Gains

The choice of the current limiting gains kp,Rvi and kp,Rvi*ΔX/R are chosen to limit the current magnitude to a suitable level during a bolted fault. For a three-phase bolted fault, the virtual impedance voltage drop should equal the voltage magnitude command, V0, as given by (10), where Imax is the desired maximum current magnitude.

(10)

For given values of Imax, Ithresh, and ΔX/R, (5)-(7), and (10) can be combined and solved for kp, with the result given in (11). Note that when using transient virtual impedance for ZVI

0, RVI

0 and LVI

0 should be omitted from

(11) because the voltage drop associated with ZVI0 would

decay to zero with the high-pass filter’s time constant, causing the current to increase beyond Imax.

a

acbbk Rvip

2

42

,

(11)

where,

22

max )(1 RXIIa thresh

0

0

0

max )(2 VIVIthresh LRXRIIb

2

max

2

0

20

0

20 )()( IVLRc VIVI

B. Small Signal Analysis

Small signal analysis of the inverter-generator microgrid is used to choose ZVI

0 and to investigate the limits on the

magnitude and X/R ratio of ΔZVI. In this work, the small signal analysis uses a procedure similar to [3] to write the full differential equations of the inverter, generator, and RL loads and lines. However, instead of linearizing the differential equations by hand, they are simulated in MATLAB Simulink to obtain the steady state operating point, and MATLAB’s ‘linmod’ function is used to linearize the equations around the operating point. In the following small signal analysis, the operating point is rated load, with a 0.8 power factor linear load.

First, small signal analysis is used to choose the nominal virtual impedance, ZVI

0. Both the magnitude and X/R ratio

of ZVI0 impact stability. It has been well documented that a

low X/R ratio causes coupling between the real and reactive power control loops, sometimes causing instability [1], [13], [17]. The root locus plot in Fig. 6 shows the system eigenvalue trajectories when sweeping XVI

0/RVI

0 with a fixed

|ZVI0|. Two primary eigenvalue pairs of interest are

identified: λ15,16, which based on participation factor analysis [3], [18] is primarily associated with the voltage controller states, and λ19,20, which is primarily associated with the generator electromechanical states. Fig. 6 shows that as XVI

0/RVI

0 decreases, damping of the voltage controller

mode increases, but damping of electromechanical mode decreases. As XVI

0/RVI

0 drops below 0.5, the

electromechanical mode becomes unstable.

-2

0

2

4R

eal

Pow

er,

pu

0

2

Reactiv

eP

ow

er,

pu

50

60

Fre

quency,

Hz

-1

0

1

Volta

ge, pu

-1

0

1

Volta

ge, pu

1 1.5 2 2.5

-1

0

1

Curr

ent, p

u

Time, s

Gen

Inv

vq*

vq

vd*

vd

iq

id

|idq|

2

0

2

maxmax0 )( VIVIVI LRIZIV

1042

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Fig. 6. Root locus for sweeping XVI

0/RVI0 from 10 to 0.2, with |ZVI

0| = 0.1

pu.

The root locus plot in Fig. 7 shows the eigenvalue trajectories when sweeping |ZVI

0| with XVI

0/RVI

0 fixed. As

|ZVI0| is decreased, λ19,20 in Fig. 7 become unstable. A

compromise between damping of the voltage controller and generator electromechanical mode is chosen at |ZVI

0| = 0.1

pu and XVI0/RVI

0 = 1 (pointed out in Fig. 6), i.e. RVI

0 = 0.0707

pu, and ω0LVI0 = 0.0707 pu.

Next, small signal analysis is used to determine the upper stability limits on virtual impedance for current limiting when operating in parallel with the generator. The root locus plot for sweeping |ΔZVI| with a fixed ΔX/R and ZVI

0 is shown in Fig. 8. With increasing magnitude of ZVI,

damping of the generator electromechanical mode, λ19,20, decreases and eventually becomes unstable. As |ΔZVI| increases, the frequency of the voltage controller mode, λ15,16, increases to ~100 Hz and then turns toward the horizontal axis, reaching damping factor ζ<0.1 at ΔZVI = 0.7 pu. The behavior of the generator electromechanical mode has a strong dependency on ΔX/R. The root locus plot for sweeping ΔX/R with a fixed |ΔZVI| is shown in Fig. 9. When ΔX/R is reduced the electromechanical mode becomes unstable. To give sufficient damping of the electromechanical mode while allowing a large |ZVI| for current limiting, ΔX/R = 5 is chosen and |ΔZVI| should not exceed 0.65 pu. Using Imax = 2 pu and Ithresh = 1 pu in (10) and (11), the limit on |ZVI| is not violated. The inverter, generator, and system parameters are summarized in Table I.

It is very interesting to note that small signal analysis shows that too high of a virtual impedance X/R ratio causes insufficient damping of a voltage controller mode, and it is only very low X/R ratios (<0.5) that cause instability. This is the case in this experimental low-voltage microgrid with relatively low X/R ratio of connecting impedances (see Table I). This indicates that with proper selection of virtual impedance, normal voltage and frequency droop may work acceptably in low voltage microgrids even with fairly low

Fig. 7. Root locus for sweeping |ZVI

0| from 0.15 pu to 0.01 pu with XVI

0/RVI0 = 1.

-100 -80 -60 -40 -20 0-25

-20

-15

-10

-5

0

5

10

15

20

25

Imagin

ary

, H

z

Real, 1/s

3 4

5

6

7

8

9

10

11

12

13

14

15

λ19

λ20

λ15

λ16

ζ=0.2

Fig. 8. Root locus for sweeping |ΔZVI| from 0 pu to 0.7 pu with ΔX/R =

5, |ZVI0| = 0.1 pu, and XVI

0/RVI0 = 1.

X/R ratios. However, X/R ratio is important, and microgrid designers need to pay attention to coupling impedances.

Small signal analysis was also performed to compare stability with transient virtual impedance vs. normal virtual impedance for ZVI

0. However, there were no significant

differences for any of the eigenvalues of interest, so no plots are included.

C. Simulation

A simulation of the virtual impedance current limiting scheme is shown in Fig. 10 for the same load step as in Fig. 4. The virtual impedance increases when the current magnitude exceeds 1 pu, and the current is reduced from a peak of 1.89 pu without current limiting (Fig. 4) to 1.25 pu with virtual impedance current limiting. The current limiting comes at the expense of increased voltage dip. The

-100 -80 -60 -40 -20 0-25

-20

-15

-10

-5

0

5

10

15

20

25Im

agin

ary

, H

z

Real, 1/s

3 4

5

6

7

8

9

10

11

12

13

14

17

X/R = 1

λ19

λ20

λ15

λ16

ζ=0.2

-100 -80 -60 -40 -20 0-25

-20

-15

-10

-5

0

5

10

15

20

25

Imagin

ary

, H

z

Real, 1/s

3 4

5

6

7

8

9

10

11

12

13

14

15

λ19

λ20

λ15

λ16

ζ=0.2

1043

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-30 -25 -20 -15 -10 -5 0 5-5

-4

-3

-2

-1

0

1

2

3

4

5Im

agin

ary

, H

z

Real, 1/s

3

5

6

7

8

9

10

11

12

13

14

15

16

17 18

28

29

30

31

32 33

λ19

λ20

ζ=0.2

Fig. 9. Root locus for sweeping ΔX/R from 10 to 0.5, with |ΔZVI| = 0.5

pu.

TABLE I –INVERTER, GENERATOR, AND SYSTEM PARAMETERS

Parameter Value

Base frequency, ω0 60 Hz

Sb_gen 15.625 kVA

Vb_gen, line-neutral 120 V

Ib_gen 43.4 A

Sb_inv 11.16 kVA

Vb_inv 380/sqrt(3) V

Ib_inv 17 A

Inv voltage PI proportional gain, kpv 0.05 Ipu/Vpu

Inv voltage PI integral gain, kiv 500 (Ipu/Vpu)/s

Inv current PI proportional gain, kpc 0.5 Vpu/Ipu

Inv current PI integral gain, kic 500 (Vpu/Ipu)/s

Nominal virtual resistance, RVI0 0.0707 pu

Nominal virtual inductance, LVI0 0.0707/(2π60) pu

Current limiting max current setting, Imax 2 pu

Current limiting threshold, Ithresh 1 pu

Virtual resistance current limiting proportional gain, kp,Rvi

0.1275 pu

Current limiting virtual impedance X/R

ratio, ΔX/R 5

Gen AVR proportional gain, kp 0.92 Vpu/Vpu

Gen AVR integral gain, ki 23.1 (Vpu/Vpu)/s

Gen AVR derivative gain, kd 0.05 (Vpu/Vpu)-s

Gen Governor kp 12 ωpu/ωpu

Gen Governor ki 100 (ωpu/ωpu)/s

Gen Governor kd 0 (ωpu/ωpu)-s

P, Q calculation filter cutoff frequency, ωc 10*2π rad/s

Transient VI cutoff frequency, ωc,hpf 2*2π rad/s

Inverter filter inductor impedance 0.035 + j0.528 Ω

Inverter transformer leakage + cable

impedance (measured) 0.25 + j0.15 Ω

Generator cable impedance (measured) 0.04 + j0.01 Ω

instability caused by current reference saturation limiters is prevented by the virtual impedance current limiting method by preventing the current references from saturating.

Fig. 10. Simulation of load application with virtual impedance current

limiting.

D. Experimental Results

The proposed controllers have been tested on the experimental microgrid shown in Fig. 2. The generator is a 12.5 kW Marathon Electric Magnaplus 282PSL1704 with a DVR2000E digital voltage regulator. The generator is coupled to an induction motor powered by a variable frequency drive running closed loop speed control to emulate a diesel engine. Inverter control and data acquisition have been implemented in a National Instruments CompactRIO FPGA and real-time processor.

Experimental results for the microgrid in Fig. 2 are shown in Fig. 11, Fig. 12, and Fig. 13. All plots show instantaneous, unfiltered quantities. The data acquisition system has problems with picking up switching noise, and is primarily responsible for the significant harmonics present on the power and voltage traces.

Experimental results for the base case with constant ZVI0

and no current limiting are shown in Fig. 11. The oscillations of the ~7 Hz electromechanical mode are apparent in the power and frequency traces. With simple saturation current limiting, shown in Fig. 12, the q axis voltage regulator current limits first, and when the inverter and generator frequency begin to deviate the voltage and current regulators ‘wind up’ and become unstable. Virtual impedance current limiting is shown in Fig. 13. The virtual impedance is inserted when the current magnitude exceeds

0

1

2

Real

Pow

er,

pu

Gen

Inv

0

0.5

1

Reactiv

eP

ow

er,

pu

58

59

60

Fre

quency,

Hz

0.8

1

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ge, pu

vq*

vq

0

0.1

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vd*

vd

0

1

Curr

ent, p

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|idq|

1 1.5 2 2.50

0.1V

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pedance, pu

Time, s

Rvi

Lvi

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Page 7: [IEEE 2013 IEEE Energy Conversion Congress and Exposition (ECCE) - Denver, CO, USA (2013.09.15-2013.09.19)] 2013 IEEE Energy Conversion Congress and Exposition - Virtual impedance

Fig. 11. Experimental results for base case without current limiting.

Fig. 12. Experimental results showing instability caused with simple

current reference saturation limiting.

1 pu, and reduces the q-axis voltage reference in order to limit the current. Virtual impedance is seen to be effective

Fig. 13. Experimental results with virtual impedance current limiting

showing that the current magnitude is limited and instability avoided.

for current limiting during overloads caused by poor transient load sharing between GSGFm inverters and synchronous generators.

V. CONCLUSION

This paper analyzes current limiting controls for voltage control inverters as a solution to poor transient load sharing between inverters and synchronous generators in islanded microgrids. Simple saturation of the d and q axis current references can cause instability when in parallel with synchronous generators. Virtual impedance current limiting is shown to prevent the instability caused by saturation limiters.

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0

1

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u

58

59

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Re

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|idq|

Rvi

Lvi

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