A Novel Approach for On-chip Step Down DC-to-DC Converter with DC Voltage Control

Brajesh Pandey ECE Discipline

PDPM IITDM Jabalpur Jabalpur, India

e-mail: brajeshp@iiitdmj.ac.in

Abstract—This paper propose a novel design for an on chip implementation of DC to DC converters. Instead of existing designs approaches which control output voltage using pulse width modulation (PWM) scheme, this design style proposes output voltage control with a DC voltage source. The proposed converter circuit is designed and tested for frequency operations between 50KHz to 50MHz for pulse generation. This frequency range can be further fine tuned as per the specific need of any particular circuit. For MOSFETs we have used industry certified models of 180nm mixed mode planar CMOS technology. Cadence tool kit environment is used for simulating the circuit. Results obtained show that this circuit can be used a potential on-chip dc to dc converter.

Keywords- DC-to-DC converter, open circuit, on-chip

implementation, DC supply, pulse width modulation (PWM)

I. INTRODUCTION A step down DC-to-DC converter is an electronic circuit that converts a DC voltage to its corresponding lower level DC voltage. Such circuits generally find its uses in electronic devices such as cellular phones and laptop computers. In portable systems [1], the input voltage is often a battery, however different components in an electronic circuit requires different voltage levels, thus the need of a DC-to-DC converter. The relation between the output voltage and the input voltage of a step down DC-DC Converter is

Vo = D × Vi (1) where D is the Duty cycle of the pulse train. However, critical issue in a DC-to-DC converter is the control of the duty cycle using pulse width modulation [2]. Another problem in such circuits is implementation of high Q inductors [3] using VLSI technology. The proposed design takes care of both these problems by making the output voltage independent of duty cycle and eliminating the need of an inductor. By implementing the design of DC-to-DC converter only with MOSFETs, such circuits can be used for high speed and low power applications. In this paper, the proposed design and its operation is discussed in section II. Simulation based analysis of the proposed design for

operation at 50MHz is discussed in section III. In the last section, conclusion of this work is reported.

Fig. 1. Generic step down DC-DC converter

Fig. 2. Proposed design of DC-DC Converter

II. DESIGN AND OPERATION The proposed design, as shown in Fig. 2, consists of MOSFETs working as switch, resistances and capacitances [4]-[5]. The functionality of this circuit is very different from conventional step down converters. It gives control on the output voltage by only changing a constant DC supply (Vcontrol). This DC supply is connected to the gates of the MOSFETs (M2 and M3) which are operated in linear and saturation regions depending on the required output voltage. The MOSFET M1 is gated with a pulse train. The output voltage is independent of duty cycle of the pulse train, therefore any duty cycle can be used for design purposes. C1 acts as a capacitor for the device and control ripples in the output voltage of the proposed converter. This capacitive

2013 7th Asia Modelling Symposium

978-0-7695-5101-2/13 $26.00 © 2013 IEEEDOI 10.1109/AMS.2013.53

311

2013 7th Asia Modelling Symposium

978-0-7695-5101-2/13 $26.00 © 2013 IEEE

DOI 10.1109/AMS.2013.53

311

block is combination of capacitances made up of MOSFETs. When voltage Vin is applied to the circuit and a pulse train of duty cycle D is applied on the gate of M1, the device acts as a RC circuit with R and C as design parameters. R is controlled by DC supply voltage (Vcontrol) and capacitance is controlled by number of nMOS devices used in capacitive block C1. The design of C1 can be implemented using MIM technology [6] or by making High capacitance MOS based capacitors [7].

Fig. 3. Variation of output voltage with time Design parameters are adjusted depending upon desired output voltage level and ripples (Vripple) on this output voltage. This design does not use inductor as a circuit element. Therefore the proposed design gives flexibility and ease of on-chip implementation.

III. ANALYSIS AND RESULT The testing and simulation of the proposed circuit is performed using industry standard tool-kits. In the following subsections effect of Vcontrol, RLoad, duty cycle and capacitive block on output voltage (Vout) is discussed, respectively.

A. Varitation and Output Volatge with Vcontrol

In the proposed design M2 and M3 are working as a resistor [8]. Equivalent resistance of M2 and M3 is controlled by Vcontrol. This effective resistance of M2 and M3 modulates output voltage. Variation of output voltage with Vcontrol is shown in Fig. 3. As shown in Fig. 3, variation of Vout is prominent in the mid-section of figure. In this section M2 and M3 are in linear region. This shows that there is a linear relationship between Vcontrol and Vout. The two extremities of Fig. 3 correspond to cut-off and saturation regions of M2 and M3. These are not desired regions of operation. The typical values of Vout are 0.54-1.0V for 1-1.7V of Vcontrol values.

B. Variation of Output Voltage with Load

As shown in Fig. 4, variation of output voltage is almost negligible for load variation from 10K� to 100K�. As we increase value of load, variation in output voltage is nominal. This dependency on load value tends to zero as load value approaches � (open circuit condition). But for values less than 1K� variation in output is significant as shown in Fig. 5.

Fig. 4. Output voltage vs time with RLoad

Fig. 5. Variation of output voltage vs time with Rload To circumvent the dependency on lower values of load, a buffer can be inserted between C1 and resistive load. Similar effect can be achieved using a voltage regulator circuit.

C. Varitation of output voltage with duty cycle

This section discusses variation in output voltage with Duty cycle as shown in Fig. 6. The key difference between the proposed circuit and inductor based DC-DC converters lies in the fact that Vout of the proposed circuit is insensitive to duty cycle variations. This has been achieved by using the pulse train only to charge and discharge the capacitor circuit (C1). The change in duty cycle only affects the time for charging and discharging of C1 without affecting the output voltage level. As shown in Fig. 5, variation of Vout is 25mV for 25%-75% duty cycle variations.

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As shown in Fig. 7, increase in C1 results in reduction of Vripple and vice versa. Typical value of C1 can be chosen from particular design specifications. But larger value of C1 requires larger on-chip area and also increases settling time. This limits use of MOSFETs as building block of C1 for on-chip implementation

Fig. 6. Output voltage vs time with Duty Cycle

D. Variation of Output Voltage with C1

Fig. 7. Output voltage vs time with Capacitance

IV. CONCLUSION A new design approach is proposed for step down DC-DC converter. For on-chip applications this design can be implemented by using MOSFETs. The output voltage using this design is as per the standards of conventional DC-DC converters. The main advantage of this design is control over the output voltage with only a DC supply and independence from pulse width modulation controlling

scheme. This design is not using inductor therefore for on-chip implementation of DC-DC converters is made easy and cost effective both. Simulation results using Cadence tool-kit for 180nm CMOS technology justify effectiveness of this design.

REFERENCES

[1] Anthony J. Stratakos, Seth R. Sanders, and Robert W. Brodersen, “A Low-Voltage CMOS DC-DC Converter for a Portable Battery-Operated System,” IEEE, pp. 619-624, 1994.

[2] Sang-Hwa Jung, Nam-Sung, Jong-Tae Hwang and Gyu-Hyeong Cho, “An Integrated CMOS DC-DC Converter for Battery-Operated System,” PESC, vol. 47, pp. 43-47, July 99.

[3] S. Musunuri, P.L. Chapman, J.Zou, and C. Liu, “Inductor Design for Monolithic DC-DC Converters,” IEEE, pp. 227-232 , 2003.

[4] A. Tajalli, Y. Leblebici and E. J. Brauer, “Implementing Ultra-high-value Floating Tunable CMOS Resistors,” Electronics Letters, Vol. 44, No. 5, February 2008.

[5] Hang Hu, Chunxiang Zhu, Y.F. Lu, M. F. Li, Byung Jin Cho and W.K. Choi, “A High Performance MIM Capacitor Using HfO2 Dielectrics,” IEEE Electron Device Letters, Vol. 23, No. 9, September 2002.

[6] Ko-Tao Lee, Chih-Fang Huang, Jeng Gong, “High Quality MgO/TiO2/MgO Nanolaminates on p-GaN MOS Capacitor,” IEEE Electron Device Letters, Vol. 31, No. 6, June 2010.

[7] Chi On Chui, Hyoungsub Kim, Paul C. McIntyre, and Krishna C. Saraswat, “Atomic Layer Deposition of High-� Dielectric for Germanium MOS Applications-Substrate Surface Preparation,” IEEE Electron Device Letters, Vol. 25, No. 5, May 2004.

[8] Phuoc T. Tran, Bogdam M. Wilamowski, “VLSI Implementation of Cross-Coupled MOS Resistor Circuits,” IECON, pp. 1886-1891, December2001.

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