The Variability Issues in Small Scale Trigate CMOS Devices: Random Dopant and Trap Induced Fluctuations

Steve S. Chung

schung@cc.nctu.edu.tw Fax: +886-3-573 4608

Keywords:

I. INTRODUCTION Moore’s Law has driven CMOS devices scaling for several

decades. The random phenomenon becomes increasingly important as we continue to scale the devices. One of the most significant issues in the scaling is the variability induced by the process and device design [1-2], especially the random dopant fluctuation (RDF) [1] (Fig. 1), the major source of Vth variation. To solve RDF, several approaches by using different transistor architecture or process [3-5] have been proposed to remedy the problem. Among them, FinFET or FDSOI [4] has been evolved as a better choice for 20nm and beyond. However, the understanding of the dopant fluctuation effect on the RDF induced Vth variation has been almost studied by the simulations [3-5]. Not until 2011, the understanding of the RDF became possible by using an experimental discrete dopant profiling technique [6-7]. As a consequence, experimental verifications become a first step on the understanding of the RDF behavior.

In this paper, a discrete dopant profiling ( ) method will be first introduced for this experimental purpose. On the other hand, rare has been reported for another similar type of

effect, the stress-induced random trap fluctuation (RTF) [8]. It shows an evidence that the device under electrical stress will induce the Vth variation as well. As a consequence, we will discuss how to find the correlation between the device reliability and variability and the impact on the trigate CMOS devices.

II. THE METRICS ON RANDOM DOPANT FLUCTUATION

The random fluctuation can be gauged by the Pelgrom plot [9] or Takeuhi plot [10]. Historically, the Pelgrom plot is to measure the variation as a function the device area, in which

Vth can be plotted as an inverse of , i.e.,

where L is channel length and W is channel width. Here, the coefficient (Pelgrom coefficient) can be taken from the Pelgrom plot, Vth with respect to the inverse of the square root of device area, which is easy to be achieved by the simple measurement data, and hence it is often used as a popular metric to evaluate the random dopant induced fluctuations.

Advanced poly-Si gate bulk planar and trigate CMOS devices, with SiON insulator, were fabricated. The fin width 30nm or 75nm and with various fin heights, 10nm, 15nm, and 30nm, and gate length= 36nm. Both control and split are made on the same wafer. To exclude and avoid the parasitic effects,

devices were prepared. (Fig. 2) Devices with different areas were used to calculate the Vth variations.

The comparison shown in Fig. 3 is the Pelgrom plot, in which the Vth variation is compared for the planar (control) n- and p-MOSFETs. The AVT of nMOSFET is larger than that of pMOSFET. To explain the larger value of nMOS, a boron clustering model was reported in [11]. In general, the boron atoms with high concentration are clustered in silicon. Some boron atoms of channel dopants are grouped together with weak bonding and act as one boron cluster which then leads to the larger fluctuation of dopants in the channel.

III. RDF IN TRIGATE CMOS DEVICES For a long time, the study of dopant effect on the RDF induced Vth variation has been mostly studied by the simulations [12-14]; until more recently, an experimental approach becomes feasible [15]. The profiling of the dopant

(1)

173978-1-4799-0480-8/13/$31.00 c©2013 IEEE

can be made through the calculation of the local threshold voltage based on a quasi-2D Vth model, the so called discrete dopant profiling (DDP) method.

Fig. 1 illustrates a device with existing random dopant and oxide traps especially near the drain region. Fig. 2 shows the cross-sectional view of the experimental trigate device. The profiling of random dopant distribution along the channel of the device can be obtained experimentally by combining a theoretical model [7-8]. By varying the source-to-drain bias in Fig. 4, the peak position of the channel barrier can be calculated. To achieve this purpose, the channel barrier can be considered as a second order curve, in which the peak position can be determined from the experimental measured DIBL and lateral length, Leff”, based on the formulae in Eqs. (1) and (2), Fig. 5. The discrete dopant can be modeled as a delta function, as in Table 1. The local Vth(x) was first calculated and then the dopants distribution can be determined. Eq. (5).

To study the effect of the dopant fluctuation in Trigate and the comparison with conventional MOSFET are demonstrated. Fig. 6 shows the comparison of the dopant distribution in conventional and trigate nMOSFETs. It was found that the experimental results of trigate device shows much less fluctuation, which should be from the suppression of the dopant fluctuation by the larger electrical field as a result of the specific 3D electrical field effect with better channel controllability in the trigate structure. This is consistent with the Pelgrom plot in Fig. 7 where the trigate devices have a smaller slope, AVT, in this plot. To prove the existence of the boron clustering, experimental result was demonstrated in Fig. 8, where the large fluctuation in nMOSFETs was observed. Also, very high dopant distributions are found near the drain side that are attributed to the diffused atoms of drain impurities into the channel. To study the sidewall roughness effect in trigate devices, the trigate devices with 3 different fin heights are evaluated. Fig. 9 shows the structure and the profiling results for both n- and p-trigate. It reveals that larger fin height device shows a much larger dopant fluctuation, as a result of the sidewall roughness effect.

IV. RANDOM TRAP FLUCTUATIONS Not only the process induced random dopant causes the RDF but also the device after the electrical stress, such as channel hot carrier or FN stress, NBTI stress, will induce the Vth variations. This kind of fluctuation is the so-called random trap fluctuation (RTF) [8,16]. This section will discuss how the generated traps affect the Vth variation. Furthermore, their correlation with the device reliability will be discussed.

The dopant variation before the stress can be interpreted

and quantified by the standard deviation of Vth,fresh, Vth,fresh. The slope, AVT, is an indicator of the Vth,fresh fluctuation, as given in Eq.(1), Table 2. For the device after the stress, the stressed Vth will also be shifted, which is attributed to the trap generation. If a trap generates in the gate dielectric or the interface randomly after stress, it is reasonable to treat this single trap as a delta function, as shown in Eq.(2), Table 2, where Vth,shift is the standard deviation of shifted Vth after the stress. Then, the total variation of Vth after the stress, Vth,stress, becomes a simple form as a square root of the squares in both

Vth,shift and Vth,fresh, as in Eq.(3), where Vth,shift is the standard deviation of stress-induced Vth shift. From Eq. (3), actually Vth,stress also holds the Pelgrom’s inversion square rule as Vth,fresh does in Eq. (2). Random Trap Fluctuation (RTF) Induced Vth Variation and the Reliability in Trigate CMOS Devices From Pelgrom plot [9], bulk trigate devices exhibit better Vth variation because a good control of the short channel effect which led to the suppressed RDF (Fig. 7). But, after the stress, Vth variation of trigate devices was much worse than that of control due to RTF, resulting in an increase of Vth variation. (Fig. 10) The amount of increased traps can be extracted by

Vth after the stress in Table 2. To characterize the oxide trap spatial distribution, random

trap profiling was performed after hot carrier(HC) stressed the planar and trigate nMOS devices. In planar devices, it was found that the local Vth variation fluctuated more heavily near drain edge after the stress, showing where the traps were generated due to a high electric field.(Fig.11) But, for trigate devices after HC stress, not only the local Vth variation was observed near the drain edge but also , meaning that the sidewall creates another effect. We suspect that the sidewall corner effect induced a high electric field and generated the traps. As a result, in trigate nMOS devices, the trap density was much higher than that of the planar after the HC stress. (Fig. 12) To examine the sidewall effects, pMOS devices with three different sidewall heights, under NBTI stress, have been compared, Fig. 13, in which the higher the sidewall is, the more device degradation becomes as a result of the sidewall roughness and a high electric field on the sidewall corner. The results shown in Fig. 14 confirm these reasons.

Through the above experiments, it provides us a more

specific evidence to confirm the interface traps which results from the electrical stress would enhance Vth variation, i.e.

(Vth)2 = (dopant)2 + (Nit)2 + (others)2. Also, more importantly, in the case of trigate devices, because of its specific structure of the 3D gate with possible line edge roughness, corner rounding effect, which might cause detrimental effect to the device failure if under the HC stress or NBTI stress for n-channel and p-channel devices respectively. In summary, a random trap profiling technique has been generalized and demonstrated successfully to identify the

174 2013 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

ST

H

oxide

ST

oxide trap distribution, in addition to the random dopant distribution, in a small dimension bulk trigate device. Trigate devices show better RDF variability but poorer reliability than the planar devices. From the reliability aspects, we conclude that

. (Fig. 13) Through the above experiments, it provides us a more specific evidence to confirm the traps which results from the electrical stress could enhance Vth variation, i.e., (Vth)2 = (dopant)2 + (Nit)2 +

(others)2. These results provide us a direction on a good understanding on the control of the reliability in future 3D trigate CMOS devices.

The author would like to thank the Central R&D team of UMC, Taiwan for the continuous support in the devices fabrication. This work was sponsored by the Taiwan, under

and under the ATU Top-University Program, MoE, Taiwan.

[1] F. Yang et al., , 208 (2007). [2] A. Asenov et al., ., 86 (2007). [3] T. Tsunomura et al., in , 110 (2009). [4] A. V-Y Thean et al., in , 881 (2006). [5] S. Kamiyama et al., in , 431 (2009). [6] E. R. Hsieh, S. S. Chung, C. H. Tsai et al., Symposium on VLSI

Technology, 184 (2011). [7] H. M. Tsai, E. R. Hsieh, S. S. Chung et al., VLSI Technology

Symposium, 194 (2012). [8] E. R. Hsieh, S. S. Chung et al., , 941 (2011). [9] M. J. M. Pelgrom, A. C J. Duinmaijer, A.P. G. Welbers et al.,

, 1433 (1989). [10] K. Takeuchi, T. Tatsumi, and A. Furukawa, ,

467 (1997). [11] T. Putra, A. Nishida, S. Kamohara, T. Tsunomura, and T.

Hiramoto, , vol. 48, 044502 (2009). [12] A. Asenov, S. Kaya, A. R. Brown et al.,

, 1254 (2003). [13] N. Sano, K. Matsuzawa, M. Mukai et al., ,

275 (2000). [14] A. Asenov, S. Roy, R. A. Brown et al. , 949

(2008). [15] E. R. Hsieh, S. S. Chung, C. H. Tsai et al.,

, 152 (2010). [16] E. R. Hsieh and S. S. Chung, “The understanding of the random

dopant fluctuation effect in a silicon-carbon source-drain stressed n-channel metal-oxide-semiconductor field-effect transistors,” , 101, 223505 (2012)

Vth variation is dominated by the discrete dopants in the channel, known as RDF; however, after the stress, another effect, RTF caused by the traps, will also lead to Vth variation.

( ) The 3D structure of bulk trigate FET. ( ) the cross sectional view with fin height H. Drain current is perpendicular to this plane.

The comparison of the Pelgrom plot for n-MOS and p-MOS device respectively, where the slope gives the value of AVT.

The derivation of concentration of discrete doapnts. Note the discrete dopant can be modeled as the delta function.

Gate ox

ide

DS

Oxide traps

0

0

3

( )

( ) ( ) ( 2 )

( ) ( 3 )

( # / )

23(#/ ) (5)

2013 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) 175

oxidePoly Gate

D

Gate

S Dy

”Leff

Vbi

0Y 0 Ypeak

+

oxidePoly G ate

mV

nm

channel barrier

DS

oxidePoly Gate

D

oxidePoly G ate

D

By varying the VSD, the barrier peak can be found from the DIBL since as VSDincreases, the barrier peak will be shifted toward the drain such that the trap density can be profiled along the channel.

The method to calculate the channel barrier peak along the channel, in which the peak position can be determined from the measured DIBL.

The experimental delta dopantdensity of conventional nMOS and pMOS devices.

The experimental dopant density of conventional and trigate nMOSdevices. Note that trigate device exhibits a smaller dopant density.

The trigate devices show lower slopes of Avt than the planar ones (control) because a stronger gate field in trigate tends to suppress the dopant fluctuation.

VC,max

Poly Gate

oxidePoly G ate

D

oxidePoly G ate

D

(d)

(e)

(a) The trigate with various heights. Local Vth variations in (b) nMOSFET, (c) pMOSFETs, and the dopant density of trigate devices in (d) nMOSFETs, (e) pMOSFETs. Larger fin height induces larger dopant variation.

oxide

,

,

0

2 2, , ,

/ (1) /

( ) ( ) /

1/ (2)

1/ (3)

The local Vth profiling results by RTP for planar devices. RTF was accumulated over the RDF.

10-year lifetime prediction of trigate pMOS devices after NBTI stress,showing the higher the fin device shows poorer lifetime as a result of sidewall roughness effect.

The comparison of trapdensities for planar and trigatedevices after HC stress, showing that the traps of trigate device are much larger than those of planar device.

Ntrap profiling for different Fin-height trigate devices after NBTI stress. More traps are observed for larger Fin-height device due to sidewall roughness effect.

oxidePoly Gate

D

roughness effect

The derivation of Random Trap Fluctuation (RTF), in which Vth is also proportional to the inverse of the square root of device area.

Although trigate devices show good variability, they show much worse Vthdegradation after the stress than the control, resulting in an increase of Vthvariation.(RTF)

176 2013 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)