2013 10th International Multi-Conference on Systems, Signals & Devices (SSD) Hammamet, Tunisia, March 18-21, 2013

SSOl131569700371

Direct Space Vector PWM Algorithm for Multilevel Inverters independent of that of two

levels with Neutral Point Balancing Karima Halfaoui

University of Sf ax , Engineering School of Sf ax , B.O.P.W, 3038 , Sfax , Tunisia

halfaouikarima@yahoo.fr

Abstract-This work proposes a direct space vector

PWM algorithm for multilevel inverters without

passing by the decomposition of space vector diagram

of three-level inverter into two-level, the nearest three

vectors (NTV) are determined via identification of the

sector that the reference voltage vector belongs and

the triangle where the tip point of the reference vector

lies. The duty-cycles are determined using a single

calculation equation set; the switching sequences that

will be used are chosen to generate the output

voltages.

The redundancies of some output voltage vectors are

thoughtfully used to cancel imbalance of dc link

capacitor voltages. This algorithm can be generalized

into the case of any num ber of levels.

Simulation results show the algorithm feasibility.

Index Terms-modulation index, neutral point

balancing, space vector pulse width modulation

(SVPWM), three-level neutral point clamped

(NPC) inverter.

I. INTRODUCTION

Multilevel inverters are mainly applied in high­voltage and high-power applications. They offer the advantage of effectively stacking the switching devices in series, thereby providing a higher dc-bus voltage than can be obtained by conventional techniques. At the same time, the harmonic content of the output voltage waveform is significantly reduced compared to conventional two-level inverters. This kind of converters requires a more complicated controller to generate the large number of gating signals. Another inherent problem with these inverters is possible unbalance of the capacitor voltages which may result in overvoltage of one or more of the switches.

The performance of multilevel inverter depends mainly on the pulse width modulation method that used. Various multilevel pulse width modulation strategies have been developed and studied [1-3]. Among these strategies, space vector

978-1-4673-6457-7/13/$31.00 ©2013 IEEE

Abdessattar Guermazi University of Sfax , Engineering School of Sf ax , B.O.P.W, 3038 , Sfax , Tunisia

Abs.Guermazi@enis.rnu.tn

pulse width modulation (SVPWM) is more suitable for digital implementation and switching waveform optimization.

Several works apply the space vector modulation to multilevel inverters. These works use the decomposition method [4-6]. Tn this method, the Space vector diagram of three-level inverter is composed of six small hexagons that are the space vector diagrams of the two level inverters. Each hexagon, constituting the diagram of a two level inverter, centres on the six apexes of the medium hexagon. To simplify the diagram of a two level inverter, two steps have to be taken. Firstly, from the location of a given reference voltage, one hexagon has to be selected among the six hexagons. Secondly, we substrate the amount of the centre voltage of the selected hexagon from the original reference voltage. After this correction of reference voltage vector, all the remaining necessary procedures for the three-level SVPWM are done like conventional two-level inverter.

In this paper, firstly we present the proposed space vector pulse width modulation algorithm for three level diode clamping inverter that didn't need to pass by the decomposition method; we focus on finding the location of the reference vector via a direct positioning approach of available triangles within the SVM diagram. Secondly, we present an algorithm for balancing of dc link capacitor voltages, which explain how to choose desirable redundant vector on the base of measurement of dc link capacitors voltages.

II. STRUCTURE OF THREE-LEVEL INVERTER

Figure 1 shows the simplified circuit diagram of a popular three-level neutral point clamped (NPC) inverter. The inverter leg 'A' is composed of four IGBT switches Tl to T4 with four antiparallel diodes Dl to D4. On the dc side of the inverter, the dc bus capacitor is split into two, providing a

neutral point '0'. When switches T2 and T3 are turned on, the inverter output terminal 'A' is connected to the neutral point through one of the clamping diodes Dl and D2. The operating status of the switches in the NPC inverter can be represented by the switching states shown in table I. Switching state '1' denotes that the upper two switches in leg 'A' are on and the inverter pole voltage VA is ideally +Vdc/2, whereas '-1' indicates that the lower two switches conduct, leading to V A = -V del2. Switching state '0' signifies that the inner two switches T 2 and T 3 are on and VA is clamped to zero through the clamping diodes. Depending on the direction of the load current lA, one of the two clamping diodes is turned on. For instance, a positive load current (IA > 0) forces Xl to turn on, and the tenninal 'A' is connected to the neutral point '0' through the conduction of Xl and T2• The switches Tl and T3 operate in a complementary manner similar to switches T2 and T4. Figure 2 resumes the six possible switch combinations in the inverter.

A B c

Fig. l. Three-level neutral-point clamped inverter topology

Current sign Switches turned on Pole voltage ''A 11 , 12 Vdcl2

IA>O Xl,12 0

D4,D3 . Vdcl2

13,14 . Vdc/2 I <0 A I3, X2 0

D2, Dl Vdel2

TABLE 1. SWITCHING STATE (PHASE A)

Since three kinds of switching states exist in each leg, the three-level inverter has 3

3 = 27

switching states. Figure 3 shows the space vector diagram of three-level inverter. The voltage vectors are identified as 10-1, 100, etc. For example, in the case of 10-1, the output terminals A, B, and C have the potentials V del2, 0, and -V dc/2 respectively.

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Based on magnitude, the voltage vectors can be divided into four groups: Zero vectors (000, Ill, -1-1-1), Small vectors (located on the interior hexagon of the diagram, can be obtained by two distinct vectors, called redundant vectors, Medium vectors (10-1,01-1,-110,-101,0 -11,1-10), and Large vectors (1-1-1 , 11-1 , -11-1 , -111 , -1-11 ,1-11 ) . All zero vectors have zero magnitude, small vectors have a magnitude of Vdc/3, medium vectors have a magnitude of V dcl -J3 and large vectors have

magnitude of 2Vdc/3. Each small vector has two switching states, one containing 1 and other containing -1, and therefore can be further classified into positives redundant vectors or negatives redundant vectors.

(a) :Vxo=Vdcl2 .. �,>() (b) :Vx� etI,>() (e) :Vx.,...Vdc12 ,,1,>0

""lE4' ::: " I . I"

T4

(d) :V,o=Vdel2 et Ix<\! (Q :V,o=-Vdcl2.t 1,<0

Fig. 2. Six possible switch combinations of three level NPC inverter (X = A, B, C)

1(3

Fig. 3. Space vector diagram of three-level inverter

Ill. DIRECT SVPWM FOR THREE LEVEL INVERTER

As shown in figure 3, the space vector diagram of a three level inverter can be composed of six sectors; each sector is divided into four triangles, thus to know the vectors that will be applied, we ought to identifY the number of the sector that the reference voltage vector belongs and the triangle where the tip point of the reference vector lies.

A. Sector's identification Tn order to locate the sector where the reference vector exists let us use the following flow chart:

if V pref � 0 then if Varef � 0

if Vpref >.J3Varefthen Sector 2 else Sector

else if V pref > -.J3 V mef then Sector 2 else

Sector 3 end

else if V mef > 0 then

if V pref < -.J3 Varef then Sector 5 else

Sector 6 else

if V pref < -.J3 Varef then Sector 5 else

Sector 4 end

B. Triangle's identification Once we identify the sector, we focus on

finding the location of the tip point of the reference vector among the four triangles in this sector. Let us take for example the first sector and number all lines within this sector as shown in Figure 4. We define the modulation index by:

3 Vref m=- --

2 Vdc So that the reference vector does not leave outside

the diagram, we choose m ::;; .J3 .

1

o Ll 0.5

2

J3 "l�Varef 2

3

Fig, 4, Lines' distribution in the sector 1

Figure 4 shows six lines Ll - L6 whose mathematical equations in the a-� plan are:

L1: Vllref = 0

J3 L2 : V13ref - 4 = 0

L3: V13ref + J3varef - J3 = 0

L4: V13ref + J3varef - � = 0

L5: V13ref - J3varef = 0

L6 : V13ref - J3varef + � = 0 Where Vref =(Varef, V�ref) is associated with the three-phase voltage reference.

According to the basic algebra, Li(V mef, V pref) = 0 is valid for all points located on Li. When an arbitrary vector (Varef, Vpref) locates above a line Li, Li (Varer, Vpref) gives a positive value, and if the arbitrary vector (Varef' Vpref) locates below a line Li, Li (Varer, V pref) gives a negative value. Thus, it is possible, by some conditional expressions, to identify the triangle where the reference vector lies, according to the following flow chart:

if L4 ::;; 0 then Triangle I else if L2 2: 0 then Triangle 4 else if L6 ::;; 0 then Triangle 2 else end

Triangle 3

Generalization of the algorithm (or an n-Ievel �

For an n-Ievel inverter, every sector is divided into (n_I )

2 triangles, making a total of 6(n_I )

2

triangles, and comprises 3n-3 lines numbered L 1, L2 ... L3n-3 starting trom the lowest horizontal side straight up to the last one, then turn clockwise and similarly continue numbering as illustrated in Figure 5. This figure shows the numbering of lines and triangles of a four-level inverter in the first sector 1.

Sta.rt here

Fig. 5. Lines' and triangles' numbering in the sector 1

The generalized equations of the lines are given by the following relationships [7]:

13 (1' -1), Li= �ref 2(n-I) i = l,2, .... p-1;

Lj=�ref+13Varef- 13 (2n-j-I), (n-I) j =n,n + 1, ... 2n - 2;

Lk= VJjref-13Varef+ 13 (k-2n + 1), (n-I) k = 2n -1,2n, .... �n -3;

C. Duty-cycle calculation Tn the space vector approach, over one PWM

cycle T m a specific number of voltage vectors are selected and used in a specific time length and sequence. Typically, three voltage vectors are selected. Tn this case, associated with the three voltage vectors Vk, Vk+1, Vk+2, three time lengths Tk, Tk+1, Tk+2 should be determined. To calculate the time lengths, the complex variable volt-second balance rule is applied. V T =V T +V T +V T ref m k k k + 1 k + 1 k + 2 k + 2

The total time lengths of voltage vectors in a PWM period should be equal to the PWM period.

Tm =Tk +Tk+l +Tk+2 The time length of the output voltage vectors in a PWM period Tk, Tk+l, Tk+2 are calculated as shown in table II, where to is the time length of the zero vectors, t1 and t2 are the time lengths of small vectors, t3 is the time length of the medium vectors, t4 and ts are the time lengths of large vectors, Tm is PWM period, m is the modulation index and e is the angle from the axe a to the reference vector.

Tri;;lngle 1:

( 4 . " to =Tm 1- .,J3mSm(6+-) 3 3

4 . " t, = J3mTmsmC--El) 3 3

4 . t, = ,j3 mTrnsmCEl) •

3

T"inngle 3:

4 . t, =T",(1- .J3 lll sm( 6»

4 . TI t, = T (1- 'J3m srn(- - 6» - on

3 3

4 . 11 tl =T (JjmSm(8+-J-I) m 3 3

Tri�ngle 2:

2 . " t, =2T",(I- J3msm(6+-) 3 3

4 . t, = .J3 mT .. sm( El)

4 . It t, = Tm ( ,j3msmC - - El) - I ) 3 3

Trinngle �:

t, = 2T .. (1- '* III sinc e + �» - 3 3 4 . It t, = T3 mTon sm(- - 6» . 3 3

t, =TmCimSin(6)-') TABLE 2. NEAREST TRIANGLE VECTOR TIME

LENGTH CALCULATION

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D. Choice a/the switching sequences After calculating the time lengths of the

voltage vectors, these voltage vectors can be applied in any sequence. Also these vector time­lengths can be split into subintervals and applied the standard pulse pattern of the NTV-PWM technique, in such manner that in each triangle, the reference voltage vector is composed by using the tip points of the triangle in turn and in reverse turn as shown in figure 6. The pulse pattern is determined with a manner that the transition from one state to another involves switching of one device only, in order to decrease losses in the inverter, thus getting a high waveform quality and a minimum number of switching criteria.

oI=c A ,

phase B 0

I

Time length

phase A 0

phase B -1

phase C

!;-!t

� 2

Trl,s'ogle 1

., " � !f � ., .,

2in... Triangle 2

�4 t3 �

1: ..:m.... 2

2

Triangle 3 Time length � � Ts � �

I I

I L

I I

phase A 0 1--+-4-+-1--!---!--1--+--+-

phase B 0 I--f--f--+----f

phase C

.:!in... 2

Triangle 4

Time length

phase A

phase B 0 I--!-.....,.-+--+--f---'P--+_--I

phase C -1 t--t--+--f

Fig. 6. The pulse pattern of NTV-PWM in the sector I

IV. DC VOLTAGE CONTROL

Ideally, the voltage across each of the dc capacitors is Vdc/2, which is half of the total dc link voltage Vdc. With a finite value for CI and C2, the capacitors can be charged or discharged by neutral current Ida, causing neutral-point voltage deviation.

The neutral-point voltage Va varies with the operating condition of the NPC inverter. If the neutral-point voltage deviates too far, an uneven voltage distribution takes place, which may lead to premature failure of the switching devices and cause an increase in the hannonic of the inverter output voltage.

Several works have been proposed for the three-level NPC inverter using either open loop scheme or closed loop scheme to ensure neutral point stabilization, as changing the switching sequence, rearranging the time distribution of the voltages vectors in the switching sequence [ 4-5-8-9].

Dc input voltages will be influenced only by small and medium vectors. However, as medium vectors are not redundant vectors, this influence will be not controlled, being therefore considered a perturbation for the dc voltage stabilization.

Thus, we change between positive and negative small vectors; we make a continuous comparison between Vcland VC2. If VCl - VC2 >0 we apply positive small vectors and if V Cl - V C2 0<0 we apply negative small vectors to generate the output voltage.

To do so, we consider the model of the input dc voltage of the inverter given by following equations:

I C I

= C dV C I = I - Id

dt I

Ie 2

= C dV C 2 = I + Id

dt 2

Id (] = - Id I - Id 2

Where VCl and VC2 are capacitors voltages, Ida, Idl and Id2 are input currents of the inverter and Fij (i=1..3 ; j=1..4) are commutation functions of switching devices (Figure 1).

V. RESULTS AND DISCUSSIONS

In order to prove the validity of the direct proposed space vector pulse width modulation (SVPWM) without use of the decomposition method, a three phase three-level inverter fed induction motor is simulated with the simulation

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parameters shown in Table Ill. The dc link voltage of the inverter is Vdc=800V, the output phase voltage of three-level inverter is shown in Figure 7. The Line to line voltage is shown in Figure 8.

Figure 9 shows the stator current lAS of three­level inverter fed induction motor. The torque of induction motor is shown in Figure 10.

Rs =4.85Q Rr = 3.805Q M=258mH p=2 Ls = 27411lH Ll=274mH J = 0.03l Kg.1Il2 Kf =0.008 N .lIl.slrad

,

TABLE 3. SIMULATION PARAMETERS

'11111"li'� I I I I I I I I 1IWIII :::WIITI'IIII'I���II-:- -- :---:--- :------:- - -' : ��I\rllrl'm o + n�II��' --:--- :----_ I,��]t -:--I I l�I�� I r�'�l I I

-200 I I II I \ I I 400- -- :--- :--- :- )II�II "� 1-:--

I I I I I I Imllt I I I I

-600 O��0.0�02�0.�00�4 �0-c'.006�0�.0=08�0.�01�0.=01�2 �0-e-.0'�4�0�.0�'6�0�.0�'8� time(s)

Fig. 7. Output phase voltage

1ime(s)

Fig. 8. Line to line voltage

"'0 1.1 1.2 OJ 0.4 05 86 01 8S 0.9 1 ·21 + 1 + II II i H i 1 1 : + 1 1 + H

� II ; 5 , , 051 U 0.52 0.64 Ui 1.11 0.1 ! ., . I--+---+----+---I-_+__! Iim�s)

\ u u u u � 00 � M M 1 I,"�s)

Fig. 9. Stator current of three-Ievel inverter fed induction motor

100 '1.8r--_--�---,

: : : : 80 ••..•. ! . . ...... ,.� . . ...... . ! .... " ." . j ... ,." .. ,

� : : ! 60 ........ L ... ... ..l ...... . .. . L ......... : . ..... . .. . : : : :

._----_ .. -- - --- - _ .. . _------ .. _.

.2IJ:--+.--t-:----:':,..--:':-----J o 0. 2 0..4 o.s 0.3

1G.6

'O�.!:o9ol-----:-0.96:::---:c0'=9B-----J Fig. 10. Torque of three-level inverter fed induction motor

To show the phenomen of dc voltage variation, we simulate the association of dc voltage input­three level inverter and induction motor, using only one type of small redundant vectors: positives vectors (Figure 11) or negative vectors (Figure 12), (Sampling frequency fs =6 KHz, modulation index m=0.8, Cl =C2=4mF). In both two studies, we show that from the beginning, the two dc voltages VCl and VC2 change from their equal initial values (400V). This variation become very important if we apply a load torque (at time 0.6s), because of the neutral point current induced by this load torque.

When the balancing algorithm is introduced, it is clear, from Figure 13 that the capacitor voltages are kept in balancing conditions, even and especially with application of a torque load.

€ :: N ··. · . · . ·· 1 ·····.·,,:::cL:�,J � ::: boo o o" i" -- -" i" o o oo i oo" o o t --- "!---TT:t-l G G.1 G.2 G.l G.4 G.5 G.6 G.7 G.8 G.9 1

6GG : : : : : : : : :

� ::h··!·r·r··r·j"':CCt:r:j G G.1 G.2 G.l G.4 G.5 G.6 G.7 G.8 G.9 1

� : � I"""""�""""";. :::1 ! ! • 1 ] �"" oo " r"""""'" oo " " i """ oo i""""":-" oo" "

;:::::I:::: I::::[:::: -5

G G.1 G.2 G.l G.4 G.5 G.6 G.7 G.8 G.9 1 Time t(s)

Fig. I I . Input dc voltages with positives redundant vectors only

6GG

� ::HTiT , [ Cr- -:ycj 30°0 0.1 00.2 00.3 00.4 0.5 G.G 00.7 00.8 0.9 1

� ::: Hm + m !, m i u mi,m , m humi,.�: j' :: i!_".�:_. �" � lGG """"";""""";""""" ;""""" ;""""" ;""""" ;""""" ;""""" ;"" : 1 2GG

• . . . . . . . .

G G.1 G.2 G. l G.4 G.5 G.6 G.7 G.8 G.9 1

! : � I:::f + ::': f i::::: ! + ::!::: i :j G G.1 G.2 G. l G.4 G.5 G.6 G.7 G.8 G.9 1

Time t(s)

Fig. 12. Input dc voltages with negatives redundant vectors only

j!:"" ' ! L iil o 01 U OJ U OS � U M 09 1

Tim��I)

�l; : '.',1 �.",;, ;, ;1 :1 I 1 1 1 � _ •

m!mu .... u .mu!mu .mum I t t \ 01 U 03 � 05 06 U " 09 1

Timt�l)

Fig. 13. Input dc voltages with the balancing algorithm

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VI. CONCLUSION

In this work, we show that we can simplify the S VPWM algorithm applied to the three level diode clamping inverter without passing by the decomposition of space vector diagram of three­level inverter into two-level, we find the location of the reference vector via a direct positioning approach of available triangles within the SVM diagram. The flexibility of the SVPWM method, which is the free choice of switching sequences and redundant vectors, allows us to control the neutral point potential by choosing the adequate redundant vectors, and using a continuous measurement of input voltages.

VII. REFERENCES

[1] F.Wang, "Multilevel PWM VSIs: Coordinated control of regenerative three-level neutral point clamped pulse width modulated voltage source inverters", IEEE Industrial Applications Magazine, July-August 2004, pp. 51-58.

[2] S.Ogasawara, H.Akagi, "Analysis of variation of neutral point potential in neutral-point­clamped voltage source PWM Inverters", Proceedings IEEE Industrial Applications Society Conference, 1993, pp. 965-970.

[3] K.R.M.N.Ratnayake,Y.Murai and T.Watanabe, "Novel PWM scheme to control neutral point voltage variation in three-level voltage source inverter", Proceedings of IEEE Industrial Applications, 34th lAS Annual Meeting Conference., vol. 3, pp.1950 - 1955, 1999.

[4] D.Lalili, E.M.Berkouk, F.Boudjema, N.Lourci, N.lkhlef, "Neutral Point Potential Control For Three Level Inverter Using Simplified Space Vector PWM" Fourth International Multi­Conference on Systems, Signals & Devices Hammamet, Tunisia, Volume 11, March 19-22, 2007.

[5] D.Lalili, E.M.Berkouk, F.Boudjema , N.Lourci , F.Boudjema and J.Petzold, " Simplified Space Pulse Modulation Algorithm for Level Inverter with Neutral Point Potential Control", Research Journal of Applied Sciences 1 (1-4) : 19-25,2006.

[6] P.Satish Kumar, T.Abhiram, lAmamath, S.V.L.Narasimham, "Space Vector Pulse Width Modulation for Multi-level Inverter using Decomposition Method", Journal of Electrical Engineering: Theory and Application (Vol.l-20 1 O/Iss.l) Kumar et aLI Space Vector Pulse Width Modulation for Multi-level Inverter ... 1 pp. 60-68

[7] M. Tavakoli Bina, "Generalised direct positioning approach for multilevel space vector modulation: theory and DSP­implementation", Authorized licensed use limited to: CNUDST. Downloaded on

November 8, 2008 at 03:27 from IEEE Xplore. Restrictions apply.

[8] Kanchan,R.S., Tekwani, P.N. and Gopakumar K, "Three-Level Inverter Scheme With Common Mode Voltage Elimination and DC­link Capacitor Voltage Balancing for an Open­End Winding Induction Motor Drive", IEEE Transactions on Power Electronics, vol. 21, No. 6, pp.1676-1683, November 2006.

[9] Kalpesh H.Bhalodi and Pramod Agarwal "Space Vector Modulation with DC-Link Voltage Balancing Control for Three-Level Inverters", International Journal of Recent Trends in Engineering, Vol 1, No. 3, May 2009.

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