[IEEE 2012 International Conference on Computer Communication and Informatics (ICCCI) - Coimbatore,...

2012 International Conference on Computer Communication and Informatics (ICCCI -2012), Jan. 10 – 12, 2012, Coimbatore, INDIA

An Efficient Design Technique of Circular

Convolution Circuit using Vedic Mathematics and

McCMOS Technique

Jubin Hazra, Student Member IEEE Electronics and Communication Engineering

Institute of Engineering and Management

Kolkata, India

Email- [email protected]

Abstract— This paper proposes a high speed low power circular

convolution implementation of two finite length sequences by

taking the advantage of fast Vedic Urdhva-Tiryakbhyam

multiplication algorithm with a very efficient leakage control

technique called Mutilple Channel CMOS (McCMOS)

technique. The use of this Vedic formula allows for high speed

convolution processing which happens frequently during the

treatment of the time domain of signals. In this paper, the

circular convolution is approached as a combination of Vedic

multiplication unit and transmission gates based adders. The

idea for designing the multiplication unit from Vedic Sutra is

adopted because the partial sums and products are generated in

only a single step. Furthermore McCMOS technique is used

having non-minimum length transistors to offer the possibility of

achieving excellent leakage control in nano-scale CMOS design

with a very modest increase in area and switched capacitance.

The simulations have been carried out in Cadence spice spectre

using 130nm, 90nm, 65nm and 45nm node technology and

presents comparative simulation results indicating the

performance of the circuit. Thorough simulations show that the

proposed architecture of designing the circular convolution

achieves approximately 74-97% better performance in terms of

PDP compared to the conventional architecture. The proposed

technique will be very useful in different applications of time

and space domains in digital image and signal processing.

Index Terms— Circular convolution, Vedic Mathematics,

Urdhva-Tiryakbhyam Sutra, Multiple Channel CMOS

(McCMOS) technique.

I. INTRODUCTION

The convolution operation is the heart of digital signal

processing and digital image processing. The effectiveness of

circular convolution is much greater than the linear

convolution due to the successive inputs of data. Circular

convolutions are the basic building blocks in the computation

of FIR filters, real time Discrete Fourier Transforms (DFT)

and Fast Fourier Transforms (FFT) [1]. Linear convolution of

two N point sequences can be conveniently computed by

employing circular convolution i.e. using the properties of

DFT [2,3,4] or Number Theoretic Transform (NTT) [5,6,7].

All of these methods require the use of 2N-1 point circular

convolution to compute N point linear convolution of discrete

time sequences. To improve the speed of this operation,

alternative methods such as the right-angle circular

convolution (RCC) have been proposed [8,9], and a

relationship between this method and linear convolution is

established. To compute RCC, the modified Fermat number

transform (FNT) was used, whereby some adjustments had to

be made to split the N numbers from the computation of RCC

into 2N-1 numbers required by linear convolution calculation

methods.

However for the implementation of circular convolution of

two finite length sequences we propose to use McCMOS

technique along with Urdhva-Tiryakbhyam Sutra of Vedic

mathematics [10] which achieves a much better performance

in terms of leakage power and speed compared to the

conventional design. The application of Vedic mathematics

enhances the speed of the circular convolution operation

enormously and on the other hand the McCMOS technique

takes control of the leakage power. It has been shown through

the simulation results that the proposed architecture of

designing circular convolution is ~2-5 times faster and the leakage power is reduced up to 55-85%.The organization of the paper is as follows:

Section II describes about the McCMOS technique, section

III deals with the Urdhva-Tiryakbhyam formula of ancient

Vedic mathematics, a brief discussion about circular

convolution and the proposed architecture of implementing

the circular convolution have been described in section IV.

Section V and VI encompass simulation results and

conclusion respectively.

II. MCCMOS TECHNIQUE

One of the earnest needs for modern VLSI designs is low

power dissipation which is making the design communities to

accept ultra low voltage CMOS technologies. Lowering the

supply voltage would force us to scale down the threshold

voltage (Vth) of the transistor to maintain the necessary

978-1-4577-1583-9/ 12/ $26.00 © 2012 IEEE


performance requirements [11]. But due to such scaling,

leakage current may increase resulting in an increase in

leakage power which seems to be one of the major problems

in sub-micron CMOS designs. In this paper we use an

efficient leakage control technique, McCMOS (Multi

Channel CMOS), for the power and performance

optimization of our proposed circuit. Leakage power is

controlled due to the use of non-minimum length of atleast

one transistor (having higher probability of being turned off)

in the non-critical path of the circuit which will result in an

increase in channel resistance as a result of which the leakage

current would get reduced and applying same technique for

the critical path but increasing the channel width to meet the

performance requirements [12].

In Fig. 1 we have shown the structure of an inverter where

McCMOS technique has been used for power and

performance optimization of the circuit. 45nm MOS model

file is used in this structure. But for controlling the leakage

power and performance we are not using the minimum length

of the transistors all the time. As seen from the figure that in

the non-critical path of the circuit we are using non-minimum

length of the nmos to reduce the leakage current. In the

critical path we have kept the channel length to minimum one

(45nm) but increasing channel width of the pmos in a manner

to satisfy necessary performance.

.

Fig 1. Inverter using the 45nm McCMOS technique.

III. VEDIC MATHEMATICS

The contribution of ancient Indian mathematics in the world

history has been immense. Vedic mathematics is one such

system of ancient Indian mathematics, which enables to

perform different tedious and cumbersome mathematical

operations at a very brisk rate [13]. The term Vedic

mathematics has been derived from the word “Ved” which

means the storehouse of all knowledge. It has a unique

technique of calculations based on only 16 Sutras (Formulae)

and their Upa-Sutras or corollaries derived from these Sutras

by means of which it offers a very efficient approach for

practical mathematical applications covering a wide range of

areas like algebra, arithmetic, geometry or trigonometry. In

this paper we are concentrating only on Urdhva-Tiryagbhyam

Sutra as discussions on the rest of the formulae are beyond

the scope of this paper.

A. Urdhva-Tiryakbhyam Sutra

Urdhva-Tiryakbhyam Sutra is one such formula of Vedic

mathematics which is applicable for all cases of

multiplication. The meaning of this sutra is “vertically and

crosswise” i.e. the bits of the multiplicand and the multiplier

are multiplied in vertical and crosswise fashion.

Multiplication procedure using this formula is simply known

as array multiplication technique [14]. Fig2. represents the

general multiplication procedure of 4×4 multiplier using the

above sutra. This figure depicts the generation of different partial products and addition of them to get the final

multiplier output.X0*Y0 is a partial product which is the 1st

bit of the multiplier output, P0. In the next step X1*Y0 &

X0*Y1 are two partial products and by adding them we get

P1. In this way we get P2,P3,..,P6 and consequently the final

7bit output of the 4×4 multiplier.

Fig 2. Urdhva-Tiryakbhyam 4×4 multiplication procedure


IV. CIRCULAR CONVOLUTION

Let us consider two n-point sequences X= {x(0),

x(1),……………..x(n-1)} and H= {h(0),h(1)………..h(n-1)}.

Their cyclic convolution [15] is an n-point sequence Y=

{y(0),y(1)………….,y(n-1)} with

n=0,1,2,………….N-1 (1)

where < >N denote the mod N

operator. Based on the operator;

<k>N = k 0≤ k ≤N-1 (2) <n-k>N = n-k ; 0≤ n-k ≤ N-1 (3) <n-k>N = N+n-k; n-k ≤ 0 (4) To separate the circular convolution from equation (1) into two partial sums we can write

Where n=0,1,……………N-1 (5)

The first term in (5) represents a linear convolution of

sequences x and h, for n= 0,1, ..., N -1 , whereas the second

term in (5) comprises the values of linear convolution

between x and h , for n= N, N + 1 ,..., 2N - 2 . Technically,

this gives an opportunity to calculate an N point circular

convolution of two N point sequences from their linear

convolution whereby an extra addition is necessary.

Yc(n)= Yl(n) + Yl (N+n) n=0,1,2……………N-2

(6)

A. Proposed design of circular convolution The proposed design of circular convolution has been shown

in fig3 taking two 4 point sequences

X(n)={x(0),x(1),x(2),x(3)} and {h(0),h(1),h(2),h(3)} i.e. we

have assumed N=4. However, the design can be extended to

any larger value of N, without any loss of generality. The fig3

shows the technique of circular convolution using the

Fig 3. Proposed Circular Convolution technique

Urdhva-Tiryakbhyam formula of Vedic mathematics. The

generations of multiplier outputs are given by the eqs shown

below.

P(0)=x(0)h(0) (7)

P(1)=x(0)h(1)+x(1)h(0) (8)

P(2)=x(0)h(2)+x(2)h(0)+x(1)h(1) (9)

P(3)=x(0)h(3)+x(3)h(0)+x(1)h(2)+x(2)h(1) (10)

P(4)=x(1)h(3)+x(3)h(1)+x(2)h(2) (11)

P(5)=x(2)h(3)+x(3)h(2) (12)

P(6)=x(3)h(3) (13)

As seen from the eqs (7)-(13) the generated output is same to

that of the linear convolution. Now to get the circular

convolution the following steps are done:

• The Urdhva-Tiryakbhyam multiplier output is

always of odd number. The middle number is first

marked. According to the fig3 P(3) is circled.

• Thus we get two arrays of outputs in both sides of

the circled middle number. In fig3 the right side

array of P(3) consists of P(4), P(5), P(6) and the left

side array consists of P(0), P(1), P(2).

• Keeping the circled middle bit fixed, the MSB of

right side array of the middle bit will be added with

the MSB of left side array. Similarly all the bit

positions in the right side array will be added with

the corresponding bit positions in the left side array.

• This step will go on until all the bit positions in the

right and left side array of the middle bit are added

according to the previous step and after addition we

will get the final output of the circular convolution.

In fig 3 the final output sequence are shown

generated by the following equations:

Y(0)=P(0)+P(4) (14)

Y(1)=P(1)+P(5) (15)

Y(2)=P(2)+P(6) (16)

Y(3)=P(3) (17)

B. Block Diagram

The block diagram of our proposed architecture of circular

convolution has been shown in fig 4. The proposed design of

circular convolution consists of the following blocks:

• The Urdhva-Tiryakbhyam initial processing unit

composed of CMOS AND gates which

generates the partial products after the

multiplication between the bits of two input

sequences according to the Urdhva-

Tiryakbhyam rule of Vedic mathematics.

• The 1st

processing unit consists of TG

adder blocks i.e.2bit to 4 bit adder blocks in

case of two 4 point input sequence as shown in

fig3 to perform the addition operation of the

partial products generated by the above step.

• The 2nd

processing unit consists of only TG half

adder blocks which gives the final output

sequence which is the circular convolution

result of the two input sequences.


Fig 4. Block Diagram of Proposed Circular Convolution architecture

V. SIMULATION RESULTS

The simulations have been performed by using 45nm, 65nm,

90nm and 130nm McCMOS technology with 1V power

supply using Cadence Spice spectre. For the evaluation of the

performance of the circuit we have shown the comparative

simulation results of conventional circular convolution

technique and circular convolution using Vedic mathematics

in table I and a comparative study of performance between

the conventional circular convolution and McCMOS

implemented circular convolution technique using Vedic

mathematics is presented in table II. Though using the

Urdhva-Tiryakbhyam Sutra, the leakage power increases a bit

(~28%) but the propagation delay of the circuit reduces in a

large proportion (~66%) to cause a considerable amount of

reduction in PDP (~53%) shown in results of table I. From

table II it can be seen that with the application of McCMOS

technique the proposed circuit achieves excellent leakage

savings (~3-7 times) than the conventional design. Also the

McCMOS implemented proposed architecture with Vedic

mathematics achieves ~45-86% and ~53-81% better

performance in terms of average power and delay compared

to the conventional circular convolution architecture which

results in an impressive overall PDP reduction(~74-97%)

shown in fig 5. So the overall simulation results are indicating

that the proposed architecture of designing circular

convolution has enormously improved the performance of

conventional architecture in terms of power consumption,

propagation delay and PDP.

TABLE I. COMPARATIVE PERFORMANCE ANALYSIS OF CONVENTIONAL AND CIRCULAR CONVOLUTION DESIGN USING VEDIC MATHEMATICS

Conventional Circular Convolution Technique

Circular Convolution Technique using Vedic Mathematics

Leakage

Power (10-6

watt)

Average

Power

(10-6

watt)

Delay

(10-9

sec) PDP

(10-15

J) Leakage

Power (10-6

watt)

Average

Power

(10-6

watt)

Delay

(10-9

sec) PDP

(10-15

J)

7.87 6.65 1.124 7.4746 10.9356 9.127 .38432 3.50768

TABLE II. COMPARATIVE PERFORMANCE ANALYSIS OF CONVENTIONAL AND MCCMOS IMPLEMENTED CIRCULAR CONVOLUTION DESIGN USING VEDIC

MATHEMATICS

Technology

Conventional Circular Convolution Technique

McCMOS implemented Circular Convolution Technique

using Vedic Mathematics

Leakage

Power (10-6

watt)

Average

Power

(10-6

watt)

Delay

(10-9

sec) PDP

(10-15

J) Leakage

Power (10-6

watt)

Average

Power

(10-6

watt)

Delay

(10-9

sec) PDP

(10-15

J)

45nm 9.33087 8.719 .4106 3.580 1.35034 1.1092 0.0766 .08496

65nm 8.7286 7.65548 .6714 5.1398 1.8893 1.639 .17304 .2836

90nm 7.87 6.65 1.124 7.4746 2.5387 2.46138 .37095 .91304

130nm 6.64752 5.076 1.7984 9.1286 2.89022 2.8063 .8523 2.3918


PDP (10-15J)

10

8

6

4

2

0

45nm 65nm 90nm 130nm

Conventional Circular

Convolution Technique

McCMOS

implemented Circular

Convolution

Technique using

Vedic Mathematics

[11] T. Fjeldly "Threshold Voltage Modeling and the Subthreshold ltegime

of Operation of Short Channel MOSFET's", IEEE Transactions on Electron

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Telecommunication Technologies.

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of Two Finite Length Sequences. IEEE Transactions on Education, Vol. 39,

No. 1, FEBRUARY 1996, pp.77-80.

Fig 5. Comparative analysis of PDP of linear convolution

VI. CONCLUSION

A fast algorithm for computation of circular convolution of

two finite length sequences with modest power consumption

is presented in this paper. The major aspects of the proposed

architecture have been the reductions of power consumption,

delay and hardware complexity of the circuit for modern

ASIC design. The proposed architecture achieves

approximately 74-97% better performance in terms of PDP

compared to the conventional architecture of circular

convolution. And therefore, this proposed technique will be

very useful in different applications of time and space

domains in digital image and signal processing where power

and delay are the main area of concerns. However the

Urdhva-Tiryakbhyam Sutra is not that efficient for larger

length multiplications due to large number of propagation

delays. Our future scope of research lies in overcoming this

problem by designing the circular convolution using the

Nikhilam Sutra of Vedic mathematics which is mostly suited

for larger length multiplications.

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