Experimental Observation on the Random Dopant Fluctuation of Small Scale Trigate CMOS Devices

Steve S. Chung

Department of Microelectronics, National Chiao Tung University University, Hsinchu, Taiwan Email: schung@cc.nctu.edu.tw

Abstract- The random dopant fluctuation is one of the most important issues for sub-50nm CMOS technologies in terms of the device architecture and manufacturing. This paper will demonstrate the methodology to understand the dopant fluctuation via a purely experimental approach. It will be demonstrated in advanced bulk-trigate devices. The discrete dopant distribution along the channel direction can be determined. Boron clustering effect in nMOSFETs can be reasonably explained which results in a larger Vth variation, in comparison to that of pMOSFETs. Moreover, experiments have been extended to the advanced bulk-trigate CMOS devices. The sidewall roughness effect in trigate has also been studied. This approach provides a direct-observation of the random dopant fluctuation (RDF) and is useful for the gate oxide quality monitoring of future generation trigate devices. 1. Introduction Moore’s Law has driven CMOS devices scaling for several decades. The random phenomenon becomes increasingly important. One of the most significant issues in the scaling is the variability induced by the process and device design [1-2], especially the random dopant fluctuation (RDF) [1], (Fig. 1), the major source of Vth variation. To solve RDF, carbon co-implant [3], FDSOI or FinFET [4], and gate dielectric with high-k [5] have been proposed to reduce the variability effectively. So far, the understanding of discrete dopant effect on the RDF induced Vth variation has been almost studied by the simulations [3-5]. Not until 2011, the understanding of the RDF became possible by using an experimental discrete dopant profiling technique [6-7]. In this paper, a discrete dopant profiling (DDP) method has been proposed along with simple experimental measurements to locate the discrete dopant position along the channel. Extensions of the approach to study the sidewall roughness effect in trigate CMOS devices have been further demonstrated. 2. Device Preparation Advanced poly-Si gate bulk planar and trigate CMOS devices, with SiON insulator, were fabricated [7]. The fin width 30nm or 75nm and with various fin

heights, 10nm, 15nm, and 30nm, and gate length= 36nm. Both control and split are made on the same wafer. To exclude and avoid the parasitic effects, single-fin devices were prepared. (Fig. 2) Devices with different areas were used to calculate the Vth variations. 3. Principle of the Discrete Dopant Profiling For a long time, the study of dopant effect on the RDF induced Vth variation has been mostly studied by the simulations [3-5]; until more recently, an experimental approach becomes feasible [6-7]. profiling of the dopant can be made through the calculation of the local threshold voltage based on an accurate calculation of the channel barrier potential under a varying source-to-drain bias.

3.1 Pelogrom Plot

The random fluctuation can be gauged by the Pelgrom plot [8]. Historically, the Pelgrom plot is to measure the variation as a function the device area, in which Vth can be plotted as an inverse of (LW)1/2, i.e.,

where L is channel length and W is channel width. Here, the coefficient AVT (Pelgrom coefficient) can be taken from the Pelgrom plot, σVth with respect to the inverse of the square root of device area, and is often used as a popular metric to evaluate the random dopant induced fluctuations. By using AVT, fair comparison between devices with different geometry can be made. During measurements, narrow-width devices are selected, where the discrete dopant is obvious. The first comparison is Pelgrom plot, in Fig. 3, in which the Vth variation is compared for the control n- and p-MOSFETs. The AVT of nMOSFET is larger than that of pMOSFET. To explain the larger BVT of NMOS, a Boron clustering model was proposed. In general, it is well known that Boron atoms with high concentration are clustered in Si [9]. Some Boron atoms of channel dopants are grouped together with weak binding force and act as one Boron cluster which then leads to the larger fluctuation of dopants in the channel.

. (1)VTth

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3.2 Theory of the Discrete Dopant Profiling(DDP)

The principle of DDP method is to locate the channel barrier-peak position by varying the source-to-drain bias as shown in Fig. 4. Reverse-Vth-reading is performed to profile from the channel center to the drain side. The measured Vth

corresponds to the discrete dopant at the channel-barrier peak. To determine the dopant concentration, the discrete dopant can be modeled as a delta function as derived in Table 2. Vth can be calculated by the sum of delta functions at the channel-barrier peak, from which the concentrations of discrete dopants can be determined. Eq. (5). In practice, as shown in Fig. 5, the channel barrier is moved from the middle of the channel toward the drain as we increase the source-to-drain bias, Vsd. Each channel potential can be regarded as a parabola, from which the peak position can be determined from the measured DIBL value for each VSD. The value of L” represents the lateral diffusion length which can be calculated from the difference of the depletion capacitance at two different VSD. Also, L [10] , Vc,max, and Vbi can be extracted experimentally (Figs. 6-8). One typical result is demonstrated in Fig. 9, where the large fluctuation in nMOSFETs is observed as a result of the boron clustering effect [9]. Furthermore, very high dopant distributions are found near the drain side that are assumed coming from the diffusion of drain impurities.

3.3 More on the Profiling of Trigate Devices

To study the effect of discrete dopant, extensions of the approach to study the dopant fluctuation in Trigate and the comparison with conventional MOSFET are demonstrated. Fig. 10 shows the comparison of the dopant distribution in conventional and trigate nMOSFETs. It was found that the experimental results of trigate device shows much less fluctuation, which should be from the suppression of the dopant fluctuation by the larger electrical field as a result of the specific 3D electrical field effect.

3.4 The Sidewall Roughness Effect in Trigate Devices

In order to study the sidewall roughness effect in trigate (or FinFET) devices, the trigate devices with 3 different FinFET heights are evaluated. Fig. 11 is the device structure and the profiling results are given in Fig. 12. It reveals that larger FinFET height device shows a much larger dopant fluctuation, as expected. In summary, an experimental discrete dopant profiling technique has been demonstrated on the

advanced trigate device. This approach provides a direct-measurable and high-resolution scheme from very small size device. By applying this approach, we may understand: (1) the dopant fluctuation in the channel completely, (2) the boron clustering effect in n-channel devices which explains why the AVT is much larger in n-channel devices, and (3) the sidewall roughness effect in a trigate device. The channel discrete dopant profiling indeed provides us a simple-to-use and powerful technique to understand the RDF behavior. Acknowledgments This work was supported by the National Science Council, Taiwan, under contract NSC99-2221-E009-192 and NSC100-2221-E009-016. References [1] F. Yang et al., in Symposium on VLSI Tech., 208 (2007). [2] A. Asenov et al., in Symposium on VLSI Tech., 86 (2007). [3] T. Tsunomura et al., in Symposium on VLSI Tech., 110

(2009). [4] A. V-Y Thean et al., in Tech. Dig. IEDM, 881 (2006). [5] S. Kamiyama et al., in Tech. Dig. IEDM, 431 (2009). [6] E. R. Hsieh, S. S. Chung, C. H. Tsai et al., Symposium on

VLSI Technology, 184 (2011). [7] H. M. Tsai, E. R. Hsieh, S. S. Chung et al., VLSI

Technology Symposium, 194 (2012). [8] M. J. M. Pelgrom, A. C J. Duinmaijer, A.P. G. Welbers et al.,

IEEE J Solid-State Circuit, 1433 (1989). [9] S. B. Herner et al., J. Appl. Phys., vol. 83, 6182(1998). [10] S. S. Chung et al., Symposium on VLSI Technology, 74

(2002).

Fig. 1 Vth variation is dominated by the discrete dopants in the channel, known as random dopant fluctuation.

Fig. 2 (top) The 3D structure of bulk trigate formed by STI etching into the silicon surface, to form the Fin-channel; (bottom) the cross sectional view with fin height H. S/D is perpendicular to this plane.

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Fig. 3 The trigate devices shows obvious lower slopes of Avt than the planar ones(control) because a stronger gate field in trigate tends to inhibit the discrete dopant induced RDF.

Table 1 The derivation of generated traps as a function of the Vthvariation for devices after the stress. Note the trap density can be determined from σVth,stress.

Fig. 4 By varying the VSD, the barrier peak can be found from the DIBL since as VSDincreases, the barrier peak will be shifted toward the drain such that the delta trap density can be profiled along the channel.

Fig. 5& Table 2 A new model is to approximate the channel barrier peak as a second degree curve, in which the peak position can bedetermined by the DIBL.

Fig. 5

Table 2Fig. 6 The Leff in Table 2 can be extracted by the charge pumping measurement [8].

Fig. 8 Vbi in Table 2, Eq. (8) can be determined from Vth by varying Vbs, and the extrapolated value at zero gate length yields to 2(Vbi-S)+ Vds such that Vbi can be found.

1.Ypeak: channel peak position@Vds

2.Y0: channel peak position@|Vds=0.05V|

3.Leff: effective channel length

4.S.S.: subthreshold swing@|Vds|

5.ΔL: depletion length of drain@Vds

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Fig. 9 The experimental delta dopant density of conventional nMOS and pMOS devices. Note that nMOS exhibits a much larger dopant density as a result of the clustering effect.

Fig. 11 To study the sidewall affects on the degradation of stressed trigate devices, three different sidewall devices were measured.

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Fig. 10 The experimental delta dopant density of conventional and trigate nMOS devices. Note that trigate device exhibits a smallerdealta dopantdensity as a result of a larger electrical field effect.

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Fig. 12 The experimental delta dopant density of trigate devices in Fig. 11 with various fin height. It was noted that larger Fin height induces larger dopant variation as expected. (a) nMOSFETs, (b) pMOSFETs.

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Fig. 7 (a) Illustration of the flat band and local threshold voltages (b) Using charge pumping measurement, the local threshold voltage can be profiled, where at the center (0.5Leff) the local threshold voltage reaches the maximum.

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