978-1-4673-1184-7/12/$31.00 ©2012 IEEE 786

2012 5th International Conference on BioMedical Engineering and Informatics (BMEI 2012)

Biomechanics: Surface Electromyography Prosthesis Control

Patrick Caldwell, Richard Al-Bayaty, Chris Kellar, and Il-Seop Shin, Ph.D. School of Engineering

University of North Florida Jacksonville, U.S.A.

Abstract — This paper provides a method to control a robotic arm by analyzing Electromyogram (EMG) collected from surface of the forearm. The electrodes are strategically placed on top of a particular muscle to harvest its myoelectric signals generated by physiological variations associated with muscular activities such as contraction and retraction. Since the movements of other muscles detectable under the electrodes are electrically superimposed, the main strategy in controlling motor units is to isolate the desired signals by filtering, sampling, and signal processing. The prototype design, incorporated into Field Programmable Gate Array (FPGA), is a low-cost and adaptable system that could potentially be available to any subject with a very minimal learning curve. The system yields quick responses and is scalable and capable of being a valuable tool for biomedical research and development.

Keywords–biomechanics; surface Electromyogram; prosthesis; robotic control; Field Programmable Gated Array

I. INTRODUCTION Surface Electromyography (SEMG) is an experimental

technique of identifying, developing, and examining myoelectric signals developed from the body’s muscle fibers [1]. Many current devices in the market are prohibitively expensive (e.g., i-LIMB being approximately $70,000) and require a large training set [2]. The proposed design uses the properties of myoelectric signals as control methods for a robotic arm at a significantly lower cost with a minimum training interval. The signals are pre-processed through an analog input stage and digitally converted for signal processing using the Spartan 3-E Field Programmable Gated Array (FPGA). The robotic arm is controlled through the motor controller circuit. All processes occur in real time offering a quick response of the desired motions. Fig. 1 represents a flow layout of the proposed system, with the internal processes of the FPGA enclosed with dashed lines. Hardware considerations were made to negate aliasing higher frequencies, supplying adequate motor current, as well as ensuring a scalable design.

II. SYSTEM DESIGN The system designed in this work provides the real-time

responsive movements of the robotic arm. As the subject contracts the flexor digitorum superficialis (i.e., lower forearm muscle), the robotic arm appropriately moves until the muscle is retracted or the arm hits its end stop. Upon retraction, the robotic arm returns to its initial state.

Figure1. Block diagram of process

A. Anti-aliasing Input Filter Stage The myoelectric signals supplied through the electrodes,

attached on the subjects forearm, range from -80mV to +30mV [1]. Typically, the meaningful information in the signals is contained within the frequency range of 10Hz to 500Hz [1]. In order to acquire and extract only the desired information, the system requires the use of an analog input stage. The input stage consists of four cascaded operational amplifiers. (The 741 op amps are used for the system.) The first two produce a 4th order low pass filter (LPF) with a cutoff frequency approximately at 251Hz with unity gain, as shown in Fig. 2. The LPF acts as an anti-aliasing filter eliminating all higher frequencies disguised as lower frequencies. The third stage provides seven times higher gain to extract the most information from the signal. The last stage asserts a DC offset of 1.6V to the myoelectric signal, which is required since the ADC was limited to unsigned values.

B. Analog-to-Digital Converter After the input stage, the signal is routed to the analog-to-

digital converter (ADC), PmodAD1, in which the analog signal is quantized into 212 discrete levels for internal FPGA processing. The PmodAD1 requires two clocking signals to be generated by the FPGA for sampling and data conversion, respectively. In order for the ADC to stay active, the sampling signal clock must be high for a single cycle prior to the next data conversion.

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Figure 2. Frequency response representing 251Hz cutoff

Figure 3. Analog-to-digital serial data timing in [3]

The sampling rate of 1.524 kHz is selected while the

specifications for the ADC required a data conversion rate of at least 16 times that of the sampling rate due to the 16-bit output per sample for each discrete analog value. The most significant four of the 16 bits are initialization bits while the remaining 12 are the data bits. The Verilog is used for the ADC module in the Spartan 3-E Field Programmable Gated Array (FPGA) that creates both clocks, stores the 16-bit data conversion, truncates the data to 12 bits, and then outputs the discrete data value to the signal processing modules. Fig. 3 demonstrates the clocking signal timing constraints. The data bit is consecutively sent on the low data conversion-clocking signal.

C. Finite Impulse Response Band-Pass Filter The signal is sent from the ADC module into a finite

impulse response (FIR) band-pass filter (BPF) with the corner frequencies at 80 Hz and 250 Hz. Most of the features in the raw SEMG signal are contained in 10Hz to 200Hz band. However, significant noise is found at 60Hz, which necessitates the filter to be designed with a very steep transition from the stop-band to the pass-band [4]. The FIR filter coefficients are calculated using the equiripple method with the attenuation in the stop-bands set to 40dB. The minimum order filter is found to be a 109th order filter to meet the required performance. The filter module is created using the FIR Compiler v5.0 contained in the Xilinx core generator. Due to the limitations of the dedicated multipliers in the Spartan3E, the generated double precision floating-point coefficients are converted to fixed-point coefficients, and the output is truncated to unsigned 12-bit integers. The filter module generated by the FIR Compiler provides sufficient performance to remove the noise at 60 Hz. Fig.4 shows the frequency response of the generated filter.

Figure 4. Frequency response of FIR Band-Pass filter

Figure 5. Raw EMG signal (bottom) vs. conditioned signal (top)

D. Rectification and Smoothing Rectification and smoothing occurs directly after the

filtering stage. The samples generated by the FIR filter are unsigned and contain a DC offset. The module detects the offset contained in the signal by taking the average of the signal over a time window of 0.3 seconds while the offset zero button is held down. Rectification occurs by comparing the current sample with the offset. If the sample is above the offset value, the sample is subtracted by the offset. On the other hand, if the sample is below the offset value, the sample is subtracted from the offset. After rectification, the sample is smoothed by taking the moving average over a 0.3 second window. The averaging is realized using a 512 sample circular buffer. Every time a new sample is received, the value at the current index is removed from the sum and the new sample value is added to the sum. The sample is written to the buffer at the index overwriting the old value. The index is then increased by one. Once the index reaches 512, it rolls over to zero on the next increment. Since the samples are in binary, shifting the sum right by nine divides it by 512, yielding the average over the last 512 samples. The average value is then sent out of the module for threshold detection. Fig. 5 shows a comparison of the raw signal with the conditioned signal.

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Figure 6. Input signal superimposed on motor-control step signal

E. Feature Extraction via Threshold Detection The feature extraction algorithm models the time-domain

signal as Gaussian noise with a muscle contraction event occurring when the signal energy exceeds a predetermined threshold. This feature extraction method is well suited for real-time practical application because it allows for a negligible delay. It also requires no training sets from subject such as those found in [5] and [6], and is suitable for a variety of muscle targets.

A Verilog module designed for the system compares the current signal value sent from the rectification and smoothing module with a predetermined threshold value, outputting either logic one signifying a threshold break, or logic zero to signify the signal had not broken the threshold. A threshold designation is made based upon the signal-to-noise ratio (SNR) between the resting potential of the subject’s SEMG signal and the highest output from an active motion signal. The threshold of approximately 0.4 volts is determined by starting at a mark of 25 percent of the SNR and progressively moving down until the threshold level is consistently above the noise. Further threshold averaging is accomplished by making a simple state machine that outputs logic high when the threshold is broken, but requires 50 consecutive logic low values before returning the high output logic back to low output logic. This additional averaging helps reduce noise error and give a steadier output logic signal. Fig. 6 shows the rectified and smoothed input signal for half the duration with a corresponding motor control signal. The second portion of the signal represents the motor control command, which automatically returns the motor to the default position.

F. Motor Controller Design The control of the DC motors requires the ability to switch

the polarity of the voltage across the motor to reverse the motor. Since the FPGA used in this work is only capable of outputting a 3.3V signal for logic high or a 0V signal for logic low, an analog motor controller circuit is required. The circuit consists of two bipolar junction transistors, TIP31G NPN and TIP42G PNP, an LM741 operational amplifier, resistors, and positive and negative voltage sources. The motor controller converts a 2-bit logic signal to three states for the motor: positive voltage, negative voltage, or no voltage. These three states represent one direction of the motor’s motion, the opposite motion, and no motion, respectively. The three logic states are 10, 01, and 00, as shown in Table 1.

TABLE 1. STATE LOGIC TABLE FOR MOTION

Motion Pin 1 Pin 2

Open 1 0

Close 0 1

Stationary 0 0

Figure 7. Motor controller circuit diagram

Since the motions of the robotic arm are meant to seem

realistic, considerations are made to restrict the range of motion of the motor. This motion restriction is achieved by incrementing an initially zeroed counter while the threshold level is high and decrementing it back to zero while it is low. It only signals the motor while the counter is nonzero. When the counter reaches a value determined by a desired timing restraint for the motor motion, the motor stops moving even while the threshold high signal is being sent. The motor would automatically return to the original position by decrementing the counter back to zero and stopping. This motion is similar to how a human hand has a resting position and must use muscles to make a fist; yet relaxing the muscles returns the hand to the resting position. The design of the motor controller is shown in Fig. 7.

G. Pulse Width Modulation Digital to Analog Converter A digital to analog converter (DAC) is implemented using

pulse width modulation (PWM) in combination with a reconstruction filter. The DAC provides a method for viewing the intermediate signals as well as the full processed signal for performance testing. The DAC module counts a pulse clock with a frequency 212 times the sampling rate. Whenever a new sample is received, the DAC holds the output high until the counter equals the value of the sample, at which time it sends the output low. The counter rolls over to zero every time a new sample is received. The PWM signal out of the FPGA passes through a reconstruction filter, which is identical to the anti-aliasing filter. The reconstruction filter removes the harmonics of the pulse frequency rendering the actual signal.

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III. RESULTS The system was tested on three healthy subjects who had

full muscle functionality. The subjects contained very little medical background and were instructed to place the electrodes in proximity to the main lower forearm muscle (i.e., digitorum superficialis). Each subject, once connected, was asked to control the robotic arm with two motions: grip and release. Within a very short period of time, the subject was able to fully grasp a small object and release it on command. All subjects tested displayed the same results. The designed system requires zero online training sets, and can be expanded easily to tap into multiple muscles without changing the overall system structure.

IV. CONCLUSION The minute voltage signals from the depolarization and

repolarization of muscle fibers were effectively sampled, digitized, processed, and used to control a predetermined motion of a robotic representation of an arm. During the design procedures, the project suffered from several limiting factors, which were overcome by the required module additions, such as the anti-aliasing and FIR filters. Although the motor controller design allowed distortion in the control signal, the robotic arm still represented the correct muscle movements. The control signal distortion was caused by the overshooting of the desired voltage level when an abrupt voltage change was made, specifically the stopping of the motor.

In a relatively small footprint, signal conditioning and robotic motion control can be accomplished in real-time utilizing SEMG, FPGA, and the appropriate controlling mechanisms. This specific design requires a minimum learning curve, and is very adaptable to multiple subjects. In addition, the overall cost of this design is significantly less than what is currently on the market. The technique of acquiring SEMG signals is highly researched and applied in many areas including sports medicine, military and medical industries. The

main focus of this design targets the implementation of prosthetic limb motional functionality and the scalability of this medium of use.

The system presented in this paper is developed to provide the end-user with a cost effective prosthesis adaptable to many different muscle types. The threshold detection feature extraction is presented as an effective method of identifying individual muscle movements. Further research is currently being conducted into designing alternative means of feature extraction using neural networks and support vector machines (SVM) for pattern recognition similar to the methods demonstrated in [7] and [8].

REFERENCES [1] P. Konrad, “The ABC of EMG: A practical introduction to

kinesiological electromyography,” Noraxon, Inc., v1.0, April 2005. [2] C. Ishii, A. Harada, T. Nakakuki,and H. Hashimoto, "Control of

myoelectric prosthetic hand based on surface EMG," 2011 International Conference on Mechatronics and Automation (ICMA), pp. 761-766, August 2011.

[3] Analog Devices, AD7476A Reference Manual, pp. 9, May 2012. [4] M. Zecca, S. Micera, M. C. Carrozza, and P. Dario, "Control of

multifunctional prosthetic hands by processing the electromyographic signal," Critical Reviews in Biomedical Engineering, vol. 30, no. 4–6, pp. 459–485, 2002.

[5] B. Qiaohua, Z. Qiang, and L. Jinkun, "A pattern recognition research for crosswise normalized forearm SEMG signal," 2011 International Conference on Fluid Power and Mechatronics (FPM), pp. 968-972, August 2011.

[6] M. Khezri and M. Jahed, "A neuro–fuzzy inference system for sEMG-based identification of hand motion commands," IEEE Transactions on Industrial Electronics, vol. 58, no. 5, pp. 1952-1960, May 2011.

[7] Xin Zheng; Wanzhong Chen; Bingyi Cui; , "Multi-Gradient Surface Electromyography (SEMG) Movement Feature Recognition Based on Wavelet Packet Analysis and Support Vector Machine (SVM)," Bioinformatics and Biomedical Engineering, (iCBBE) 2011 5th International Conference on , vol., no., pp.1-4, 10-12 May 2011.

[8] Hioki, M.; Kawasaki, H.; , "Estimation of finger joint angles from sEMG using a recurrent neural network with time-delayed input vectors," Rehabilitation Robotics, 2009. ICORR 2009. IEEE International Conference on , vol., no., pp.289-294, 23-26 June 2009.