The AES Encryption And Decryption Realization Based On FPGA

Authors Name Luanlan Department of Information Security College of Computer Science and Information Guizhou University Guizhouguiyang, China e-mail:chongzi_ll@163.com

Abstract—With the development of networking technology,Hardware encryption technology will become an irreplaceable safety technology.In this paper, a method of AES encryption and decryption algorithm implemented on the same FPGA is presented, where a 128-bit key size mode is implemented, Modelsim simulation test results are demonstrated, the correctness of logic function of the system is verified, and system resource occupancy is presented and briefly analyzed to verify the reliability of the method.Practice proving it is an optimized hardware encryption and decryption method. Keywords:EDA QuartusII verilog HDL Simulation Modelsim AES Optimization System Resource

I. INTRODUCTION With the rapid development of computers and

communication technology a lot of sensitive information exchange with the public communication facilities and the internet. Safely and efficiently transmission of information become a important topic.Cryptography be used to data protection and identity authentication etc. Encryption algorithm implemented in hardware have a higher physical security,because the data wich packaged in the chip not easily be read or charged by external attacker.so cryptographic algorithms basted on hardware attentioned by the information security industry.

II. BRIEF INTRODUCTION OF THE RELATED TECHNOLOGIES

FPGA (Field Programmable Gate Array) a product developed on the basis of the programmable devices such as PAL, GAL, CPLD, and so on, comes out as a semi-custom circuit in the field of Application-Specific Integrated Circuit (ASIC). It overcomes the shortages of custom circuits, as well as the shortcoming of limit number of gate circuits of the original programmable devices.

The current technical mainstream for the modern IC design verification is to test by way of quick burning the circuit design completed with hardware description language (Verilog or VHDL) to the FPGA through simple composition and layout. Those programmable elements can be used to realize some basic logic gate circuits (such as AND, OR, XOR, NOT) or some even more complicated composed functions, such as decoder or math formula. In

most FPGA, those programmable elements also consist of memory elements, such as Flip-flop, or other even more completed memory blocks.

FPGA adopts the concept of LCA (Logic Cell Array) and it is composed of three parts, namely CLB (Configurable Logic Block), IOB (Input Output Block) and Interconnect, as shown in Figure 1:

Figure 1. The Structure of FPGA

The fundamental features of FPGA are: • Designing ASIC circuits with FPGA, the user can

obtain applicable chips without putting into production. • FPGA can be used as the pilot test sample for other full-

custom or semi-custom ASIC circuits. • There are lots of Flip-flops and I/O pins within FPGA. • FPGA is one of the elements with the shortest design

cycle, the lowest development expense and the minimum risk in ASIC circuits.

• FPGA, with low consumption, adopts high speed CHMOS technology and is compatible with CMOS and TTL electrical level.

We can say that FPGA chip is one of the optimal choices for small amount of systems to enhance systematic integration level and reliability.

The operation status of FPGA is set by the program in the RAM within the chip; therefore, the RAM in the chip should

2011 Seventh International Conference on Computational Intelligence and Security

978-0-7695-4584-4/11 $26.00 © 2011 IEEE

DOI 10.1109/CIS.2011.138

603

be programmed in operation. The user can adopt different programming methods in accordance with different configuration modes.

When powered on, the FPGA chip will read the data in EPROM into the RAM in the chip. After configuration, the FPGA will enter the operation status. When powered off, the FGPA will return to original state, and the internal logical relationship will disappear, thus, the FPGA can be used repeatedly. The programming of FPGA needs no dedicated FPGA programmer and the general programmers like EPROM and PROM can be used. When it is required to alter the functions of FPGA, it is only required to change one piece of EPROM. So, the same piece of FPGA can generate different circuit functions with different programming data. Therefore, the usage of FPGA is very flexible.

The system designer can, as required, connect the logic blocks within FPGA via programmable connections, which is like to put a circuit breadboard into a chip. The logic blocks and connections of the delivered finished FPGA can be altered by the designer; therefore FPGA can accomplish the required logical functions.

Altera Quartus II, as a programmable design environment, is gradually welcomed by digital system designers due to its strong design ability and easy-to-use interfaces.

Quartus II design provides improved timing closure and Logic-Lock design flow based on blocks and is the only software of programmable logic device (PLD) boasting the features of timing closure and the design flow based on blocks. The Quartus II software improves the performance, enhances the functionality and solves the potential design delay, and it is the first to provide the unified workflow developed by FPGA and mask-programmed devices in the industry fields.

The Quartus II programmable logical software of Altera is the development platform of the fourth generation, which supports the design requirements in one working group environment, including supporting the cooperative design based on Internet. The Quartus platform is compatible with the developing tools of the EDA suppliers of Cadence, Exemplar-Logic, Mentor Graphics, Synopsys, etc. It improves the design function of Logic-Lock module, adds the Fast-Fit compile options, promotes the performance of web editing, and enhances the debugging ability.

The merits of such complicated digital logical system are:

• The logical functions of the circuit are easy to understand.

• It is convenient for the computer to make analysis on the logic.

• The logic design and the realization of specific circuits are operated in two separated stages.

• The logic design is irrelevant with the actual technology.

• The resource accumulation of logic design can be repeatedly used.

• It is possible to design very complicated logic circuit by many persons in a better and quicker way (the logic system with tens of thousands of gates).

The software design flow is illustrated in Figure 2 below:

Figure 2. The design process

III. ABOUT AES ALGORITHM As the new AES symmetric data encryption algorithm

standard, Rijndael algorithm became effective on May 26, 2002. Main advantages of Rijndael algorithm are: simple design, fast key installation, needs less memory space, works well on all platforms, supports parallel processing, and can resist all currently known attacks. AES is a key iterated block cipher that contains the repeat action of round transformation on the state. Encryption process includes an initial key addition that is denoted as AddRoundKey, followed by Nr-1 rounds of transformation, and finally a FinalRound. Initial key addition and each round transformation all use the state and a round key as the input. Round key of the ith round is denoted as ExpandedKey [i], and the input of initial key addition is denoted as ExpandedKey [o]. The process of deriving ExpandedKey from CipherKey is denoted as KeyExpansion. Decryption process is similar to the encryption process, except that the round keys are used in reverse order, its encryption and decryption process for key size of 128 bits is as shown in figure 3:

Figure 3. encryption and decryption process

Where each round function consists of four steps,

604

A. SubBytes: A non-linear transformation of bytes, where the

substitution of each byte in the block is completed using a S-box function. Its algebraic expression is bij = S [aij], S-box is a transformation function, functional performance is 8-bit input & output lookup table.

Figure 4. SubBytes

SubBytes transformation is reversible, the computing of InvSubBytes, inverse transformation of SubBytes used in the AES decryption process, is as follows: firstly, inverse affine transformation of each byte element of the state matrix in the finite field G (28), and then calculate its multiplicative inverse in the finite field G (28).

B. ShiftRows: A byte transposition step where each row of the state is

shifted cyclically according to different offsets. The offset depends on the row number R, and plaintext block length Nb, if the offset of each row is denoted as Shift (R, Nb), there will be: Shift (0,4) = 0, Shift (1,4) = 1, Shift (2,4) = 2, Shift (3,4 ) = 3.

Figure 5. ShiftRows

The inverse transformation of ShiftRows used in the AES decryption process is called InvShiftRows, which is calculated by cyclically right shifting each row of the state matrix according to different offsets.

C. MixColumns: A linear substitution making use of the arithmetic

properties in the finite field GF (28). MixColumns function transforms the state matrix column by column, after transformation, byte elements of each column are equivalent

to a linear combination of byte elements of that column before changing.

Figure 6. MixColumns

The inverse transformation of MixColumns used in the AES decryption process is called InvMixColumns, which is similar to MixColumns, is the multiplication of each column of state matrix and the polynomial d(x)=0Bx3+0Dx2+09x+0E modulo x4+1.

D. AddRoundKey: Bitwise XOR of round key to each byte of the array.

Round key is derived from expanded key in sequence.

Figure 7. AddRoundKey

Where the round keys are generated and selected through the KeyExpansion of initial key. Key selection in encryption: round key of the ith round is given by column Nb×i to column Nb× i+1 -1 in matrix W. Key selection in decryption: round key of the ith round is given by column Nb× Nr-i to column Nb× Nr-i+1 -1 in matrix W.

IV. IMPLEMENTATION AND OPTIMIZATION In this system, AES encryption and decryption algorithm with key size of 128 bits is implemented. System design is mainly divided into four modules: logic module, registerfile module, interface module and testbench module. Main function of registerfile module is to receive or send data to the bus, and read/write the verilog code of logic module register. Interface module is the top-level module of this IP, its purpose is to instantiate the logic module and registerfile

605

module, providing interface logic for the task logic and register file. Testbench module is a test module.

Logic module function realizes logic verilog code of AES function, and realizes data encryption / decryption operations, which is the core of this IP.

Corresponding to Chart 1, pseudo-C language of AES encryption and decryption algorithm is described as follows:

Aes_Cipher(Satte CipherKey) { KeyExPnasion(CIPherKe ExPnadedKey); AddRoundKey(State ExPandekdey[0]); ofr(i=l;i<Nr;i++)Round(Satte ExpnadedKey[i]); Fina1Round(State ExpandedKey[Nr]); } Inv_aes_cipher(Satte CipherKey) { KeyExPnasion(CipherKe ExpnadedKey): AddRoundKey(Staet Expandedkey[Nr]); ofr(1=N-rl;i>0;i--)InvRound(Satte ExpnadedKey[1]): InvFinalRound(State ExpnadedKey[0]): }

Figure 8. System encryption and decryption process

Where the values of Opcode operation control characters are as follows: 2'b01: round key generation; 2'b10: encryption operation; 2'b11: decryption operation. It should be noted that the round keys must first be generated before encryption or decryption operation during system running, if

the subsequent encryption or decryption operation key does not change, the repetition of such operation is not needed.

Among four steps of round transformation during designing and implementation, AddRoundKey and ShiftRows are relatively easier to be implemented, the ones that consume more hardware resources are S-box and MixColumns computing, therefore, the target of optimization algorithm should be concentrated on the structure of S-box and the introduction of pipeline. Generally there are two ways for describing S-box in round function using Verilog HDL language: (1) behavioral description using case statements, taking up LE resources after synthesizing; (2) using the memory resource comes with the FPGA. If entirely implemented using LE, a lot of hardware resources will be taken up, structure will be complex, and delay will be increased. While the implementation of S-box using memory resource does not take up other hardware resources, and reduces delay, making full use of device resources. Cyclone II series FPGAs have abundant memory resource, with 33,000 LE integrated in the EP2C35F672 chip, 484Kbit RAM, and 35 18×18 multipliers, which can fully meet the design requirements. The core of AES algorithm is a repetition structure, its hardware implementation can be based on part of the pipeline structure.

V. SIMULATION TEST Based on the modules designed previously, description

on logic function of entire system is conducted. Finally, behavioral description on the system was carried out using VerilogHDL hardware description language. In order to verify the correctness of logic functions of the system, simulation of the system with MODELSIM SE 6.0 was carried out to verify the correctness of logic functions of this 128-bit mode AES encryption and decryption system. All the data used are testing data provided by FIPS.

Plaintext 128'h3243f6a8885a308d313198a2e0370734 Key 128'h2b7e151628aed2a6abf7158809cf4f3c Ciphertext 128'h3925841d02dc09fbdc118597196a0b32

Figure 9. Simulation test result

606

Table1.test data Through the analysis on simulation results of the above

test data, under the control of the same key, plaintext is encrypted by the system, and the resulting ciphertext is again decrypted by the system, the final resulting data is consistent with the input plaintext data, as well as the test data provided in the reference material. Thus it can be proved that the encryption and decryption work of this system is normal.

VI. CONCLUSION

With wide-range application of AES algorithm, how to reduce hardware costs and choose the right chip and design to meet the same design requirement will be a problem can not be ignored. The device used in this design is Altera's Cyclone II series EP2C35F672, according to comprehensive compilation results of QUARTUS 9.0, we can see that total logic elements: 11,187 / 33216 (34%). The AES encryption and decryption system designed in this system

completed design code description and comprehensive compilation on Altera’s QUARTUS 9.0 development software, and then design simulation verification on MODELSIM SE 6.0, the design has basically achieved the desired purpose, on the basis of meeting the execution speed of encryption and decryption process, balance between speed and resource is achieved, which has a favorable cost-performance.

[1] Joan Daemen Vincent Rijmen.AES Proposal:Rijdael [2] Nicholas Weaver,John Wawizynek.Very High Performance Compact

AES Implementations in Xilinx FPGAs [3] Sounak Samamta.FPGA Implementation Of AES Encryption and

Decryption. [4] Announcing the ADVANCED ENCRYPTION

STANDARD(AES).Federal Information Processing Standards Publication 197.November 26,2001

[5] RODRIGUEZ-HENR IQUEZF,SAQBNA,DIAZ-PEREZA.4.2 Gbit/s single-chip FPGA implementation of AES algorithm.Electronics Letters,2003,39(15)

[6] SKLAVOS N,KOUPOPAVLOU O.Architectures and VLSI Implementations of the AES-Proposal Rijndael[J].Computers,IEEE Transactions on,2002,51(12):1454-1459

[7] MCLOONE M,MCCANNY JV.High performance Single-Chip FPGA Rijndael AlgorithmImplementation.Proceedings Cryptographic Hardware and Embedded Systems Workshop,CHES,Paris,May 2001

607