Low-Power Design Techniques with Process Tagging

and Dynamic Power Management

Daniel Cooley, Yuwono Rahman, Jin Ruan, Xun Yu, Lei Chen, Jianyuan Deng

Silicon Laboratories International Pte., Ltd.

Singapore

Email: Daniel.Cooley@silabs.com

Abstract—This paper proposes a power optimization strategy

that takes into consideration the effects of operating frequency,

process, voltage, and temperature variation (FPVTV) in both

analog and digital circuits. Traditional designs set the biasing

points to guarantee performance over all working conditions,

resulting in wasted power in most instances. By collecting

information about FPVTV, the designer can make intelligent

decisions to reduce power consumption and extend battery life in

mobile products. The proposed optimization strategy was

implemented in silicon and successfully proven on an RF/mixed-

signal chip with DSP, resulting in a power savings of 11.2% in

typical conditions. The usage of such a strategy is discussed, as

well as the production flow for gathering process corner

information in high volume situations.

Index Terms – dynamic power management, process tagging,

process variation, low-power design

I. INTRODUCTION

As consumer electronic and medical devices continue to advance in feature set and battery life, chip suppliers are pressured to extend the power reductions that have fueled a two-decade boom in portable devices. Lowering power consumption without sacrificing performance requires design teams to develop new architectures that take advantage of advances in semiconductor processing and lithography. New designs are also incorporating information such as frequency, process, voltage, and temperature variation (FPVTV) into the biasing of digital, mixed-signal, and RF circuits [1]–[3]. Extensive searches to locate the optimal biasing for a given set of conditions have been made, but analysis has shown that increased optimization of biasing points provide diminishing returns [4]. In other words, the largest power savings come from simple ideas that prove challenging to implement.

In this work, we present a simple and flexible process tagging and biasing algorithm that reduced the typical power consumption in a fully-integrated RF/mixed-signal chip with DSP by 11.2%. More sophisticated use of the existing platform can further reduce power by another 5-10%. Like existing designs, voltage scaling according to FPVTV was used in the core digital circuits. However, unlike most designs, half of the power savings came from reductions in analog, RF, and mixed-signal circuit biasing points. To date, previous designs have considered power scaling in analog circuits according to

voltage, temperature, and frequency [3]. Other designs strive to reduce sensitivities to process variation [5]. This work goes one step further and incorporates process variation into the biasing algorithm of the analog, RF, and mixed-signal circuits to actually reduce the power consumption averaged over large quantities of chips.

After this introduction, Section II explains the basic concepts for dynamically biasing circuits according to FPVTV. Section III provides a simple yet flexible circuit for determining process variation. Section IV addresses system integration issues that arise while using FPVTV information to dynamically adjust power consumption during normal operation. Section V discusses the production flow considerations in a high-volume environment. Section VI describes experimental data captured in production and summarizes overall power savings. Section VII discusses additional concerns in implementing the ideas in this paper. Section VIII is dedicated to conclusions, and further experiments and data are presented in the appendix.

II. FPVT BIASING BACKGROUND

Traditionally, the power consumption of a finished design is limited by the worst-case conditions that a design will experience over FPVTV. Designers must provide adequate margin over the lifetime of the chip to withstand the full FPVTV, resulting in wasted power when operating in typical conditions. Design teams have developed many methods to cope with FPVTV to minimize power consumption, and the techniques vary based on whether the circuits are digital, mixed-signal, or analog/RF in nature.

As standard CMOS process geometries have scaled from 1.0 μm in the early 1990’s down to the 45 nm node available today, digital power consumption should grow 2.7X each two years without process modifications to threshold voltages and new design strategies to limit power growth. Starting in 1990, Macken et al. first suggested scaling the supply voltage of digital circuits in order to minimize current drawn from the battery over FPVTV [1]. Researchers over the next two decades extended this idea to include sophisticated modeling of critical path sensitivity to FPVTV, voltage adjustment during normal operation, advanced processor speed scheduling, immunity to supply ripple caused by voltage scaling, and systems with dynamic frequency and voltage scaling [2], [4].

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These trends are expected to continue as new challenges appear in advanced digital processes at 40 nm and below.

Despite their common use in digital FPVTV compensation schemes, pure analog and RF circuits have not received the same attention. However, the idea has gained traction in recent years. Designers are now considering dynamic threshold voltage (DTMOS) control of critical transistors to reduce FPVTV effects in ultra-low power analog circuits. Additionally, one proposal optimizes power consumption by monitoring temperature and signal conditions to dynamically adjust biasing currents in RF circuits such as low-noise amplifiers [3]. As high-performance analog circuits continue to be integrated within standard digital CMOS processes, the trend in FPVTV compensation is expected to continue.

Mixed-signal circuits that bridge the analog-digital domains have experienced large power reductions with regard to FPVTV. A key objective in designing these circuits is to transition traditional analog functions into the digital domain to take advantage of existing FPVTV power saving techniques. New ADCs are continually executing more functions in the digital domain, going so far as using open-loop amplifiers with digital correction [6]. The analog portions of these data converters utilize the FPVTV compensation techniques listed above.

III. PROCESS IDENTIFICATION AND TAGGING

A. Methods

Many methods have been proposed to identify process variation for both critical transistors and broad chip-wide trends. Research has generally been split between device-level and functional tests. Device testing includes test structures that are used to extract information about transistor threshold voltage, oxide thickness, mobility, etc. [7]–[8]. These circuits can be operated in a number of regimes, including saturation, triode, and weak inversion. The device-level testing can be used for specific circuits or to gain a broad understanding of process variation across a single or multiple die. Beyond single-device testing, researchers have used circuits such as ring oscillators as a proxy for critical paths in digital circuits since the advent of FPVTV compensation schemes [1]. These structures provide a function-based way to identify FPVTV, rather than revealing more detailed device-level information.

B. Device Measurement and Storage

The disclosed circuitry minimizes complexity and maximizes flexibility. As shown in Fig. 1, an external current is driven onto the chip and passed over various transistor and resistor structures in succession during manufacture. At each step, the voltage is recorded, translated into a process corner, and then stored into non-volatile memory (NVM) within the chip. If NVM is not available, an alternative is shown in Fig. 2. Here, an on-chip MCU or digital state machine can control an integrated current source and ADC. The current source needs to be insensitive to FPVTV or can be calibrated during manufacture. The results can be stored in registers or RAM for later use.

Translation of the I-V characteristics of transistor and resistor structures require thorough comparisons and correlation of the simulation models, wafer acceptance test (WAT) data from the fabrication facility, and laboratory testing. Multiple device characteristics can be extracted, depending on the amount of current supplied to the test structures. For example, large currents yield information about IDSAT, and small currents provide information about threshold voltage.

IV. SYSTEM INTEGRATION

Knowing the process variation of transistors and digital structures on the chip allows us to use that information to optimize the power consumption of the die. In addition to the process corner, it is useful to calculate what frequencies the digital core and various analog circuits –mixers, VCOs, ADCs, DACs, etc.– require, the supply voltage, and the junction temperature of the die itself. All of this information can be built into a comprehensive biasing algorithm. An on-chip MCU, external MCU, or digital state machine can implement such an algorithm, described in Fig. 3. First, the chip needs to boot with biasing points that are guaranteed to ensure full functionality and performance over FPVTV. Once this is complete, process information is either measured or retrieved from memory, followed by calculation of operating frequencies and measurement of temperature. Finally, this information is translated into biasing points (e.g., voltages and currents).

Each subcircuit will have a different dependency on and

sensitivity to FPVTV and must therefore be biased

independently. This can include both voltage and current

scaling. In general, slower process corners and higher

temperatures require higher biasing voltages and currents to

maintain equivalent performance as typical corners and

temperatures.

Figure 1. Process measurement structure using off-chip components during

manufacture.

Figure 2. Fully-integrated process measurement structure.

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V. PRODUCTION FLOW

Process tagging is implemented on a previously established production flow for a similar product. The flow is demonstrated in Fig. 4 and starts with wafer fabrication, followed by wafer sort and probe, package assembly, and final test. In this flow, there are two options to implement process tagging: wafer probe and final test. Regardless of where process tagging is executed, temperature control is vital to producing consistent results. At wafer sort, the wafer under test sits in a chuck that can be set to a desired temperature. One prober, the TEL P12XL, has a ±2

oC tolerance. Testing above

room temperature is advantageous for distributing temperature evenly across the wafer. Since the wafer is in direct contact with the chuck, the junction temperatures are controlled easily.

At final test, a temperature sensor is placed near the device under test (DUT). During process measurement, the temperature is read by the tester and used to determine the final tagging result. However, controlling the temperature in test chamber better than ±5

oC is difficult. The temperature

sensor may not reflect the real temperature in the chamber or the silicon junction temperature inside of the package. This is

due to the large volume of test chamber, which is opening and closing during testing. Thus, a stable temperature of either the chamber or DUT is difficult to achieve. In production, wafer probe is the preferred step to execute process tagging, with final test tagging as a backup. The process tagging results are then monitored in full production to ensure that the process is centered and the wafer probe is functioning properly. A systematic process shift can cause undesired changes in average power consumption of large numbers of die. In addition, chips whose process corner results fall outside of a defined window can be easily screened.

VI. MEASURED DATA

There are three stages of data collection during product development. Initial I-V data from all transistor corners are collected on a set of skewed samples to determine the boundaries for process tagging. The second set of data is taken at wafer sort, where the chips are measured and tagged according to boundaries that have been set. Subsequently, the wafer is sent to assembly house for packaging so that the process tagging results can be correlated in final test, bench measurement, and WAT comparison. An example wafer probe dataset for low-voltage (LV) transistors is shown in Table I.

TABLE I. PROCESS TAGGING RESULTS FROM TWO WAFERS

LV Cornera Wafer A (Typical) Wafer B (Skewed)

Count % Count %

TT 20176 97.42% 3339 16.28%

TF 192 0.93% 29 0.14%

TS 192 0.93% 137 0.67%

FT 150 0.72% 12645 61.66%

FF 0 0.00% 4358 21.25%

FS/SF/ST/SS 0 0.00% 0 0.00%

Total 20710 100.00% 20508 100.00%

a. Split naming is NMOS and then PMOS (e.g. FT = fast NMOS, typical PMOS).

Both wafer A and B were fabricated as typical material, and Table I shows that wafer A is mostly typical. Unexpectedly, wafer B is heavily skewed toward the faster corner. This observation was confirmed by WAT data from the fabrication facility, as well as lab testing. A map of wafer B’s process tagging results is shown in Fig. 5.

When studied closely, many patterns emerge. First, the high-voltage transistors are all typical, as the fabrication facility has much better control over the larger geometries. Second, the FF die are clustered in the center, surrounded by FT die. The mask reticles are also visible as patterns of straight lines running the length of the wafer in the horizontal and vertical directions. Finally, note that even on this highly skewed wafer, there are still some slow chips. After viewing large amounts of wafers, it is reasonable to assume that every wafer will have fast, typical, and slow process variation in the low-voltage transistors.

Figure 3. Flow diagram of system operation.

Figure 4. Production flow with process tagging capabilities at wafer sort and final test.

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The last set of production data involves long term process corner measurements, where a large amount of production wafers are tested and examined. Fig. 6 shows the process tagging results in a histogram of 2.42 million die. As expected, most of the die are centered in the typical region, but there are more chips shifted toward the faster corner when compared to the slow corner. Since the slow process corner generally requires the highest voltage and current biasing points, this set of data gives us confidence that most die will benefit from reductions in voltage and current while still maintaining performance.

The final FPVTV compensation results are listed in Table II and show that typical and maximum power consumption can by reduced by 11.2% and 5.8%, respectively. The reductions in power consumption were achieved primarily through voltage scaling of the digital core and VCO partnered with current scaling in the LNA and ADC. Wafers yielded more than 98% for large volume.

TABLE II. FPVTV RESULTS

Result Chip Power Consumption (mA)

Typical Maximum

Without FPVTV compensation 21.4 24.0

With FPVTV compensation 19.0 22.6

Power savings2.4 2.6

11.2% 5.8%

VII. ADDITIONAL TOPICS

Many additional effects must be considered but are not covered here. These include the effects of backgrinding the wafer, package-induced process shift, proximity to wafer edge, process variation and thermal gradients across a single die, and lifetime aging. The successful implementation of biasing algorithms depends on inclusion of these effects.

VIII. CONCLUSION

A method for optimizing power consumption over FPVTV was presented, including measurement data. This algorithm was implemented in silicon and resulted in power savings of 11.2%, which can be extended 5-10% more on the existing platform.

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Figure 6. LV NMOS and PMOS process tagging results for 2.42 million die.

Figure 5. Wafer map of process tagging results on skewed wafer. The wafer is

300 mm in diameter and yields roughly 21000 chips. Process corners are

defined as LV NMOS, LV PMOS, HV NMOS, and finally HV PMOS. Thus,

the FTTT corner is fast for LV NMOS and typical for all other transistors.

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