A Hybrid Ferroelectric and Charge Nonvolatile Memory Shantanu R. Rajwade, Kshitij Auluck, Jonathan Shaw, Keith Lyon and Edwin C. Kan

School of Electrical and Computer Engineering, Cornell University, Ithaca NY 14853 Email: srr77@cornell.eduPhone: (607) 220 4344

Abstract We introduce a new nonvolatile memory that incorporates ferroelectric (FE) switching layer and charge-storage floating node in a single gate stack. This hybrid FE-charge design reduces the depolarization field in the FE layer as well as increases the memory window over conventional FE-FET. The magnitude of the electric field in the tunnel dielectric is reduced at retention and enhanced at program/erase from the FE polarization. This paper discusses the working principle, gate stack design, fabrication and experimental results of this hybrid design compared to FE-FET and charge-trap Flash. Keywords: hybrid memory, ferroelectric, gate injected charge

Introduction In spite of low-voltage operation, ferroelectric (FE) FET memory is known to suffer from issues of poor retention due to the depolarization field setup up in the FE layer [1], charge leakage through defect sites and large FE film thicknesses (> 100 nm) for realistic memory windows. We propose a new highly scalable hybrid nonvolatile memory designed with FE PVDF film and HID2 as charge-trap layer that takes advantage of low-voltage operation from FE-FET as well as reduces depolarization field by gate-injection of charge.

Memory Design and Working Principle Fig. 1 shows an example of experimental design for the gate stack and program/erase (PIE) operation of the hybrid cell. A floating gate (FG) (discrete/continuous) is included above the FE layer. A thin top oxide serves as a tunnel barrier for gate injection and removal of electrons [2]. Program condition (VPROG < 0) orients FE polarization with positive surface charge facing the gate and hence increases the VTH of the cell. The injected electrons into the FG add to the VTH shift. These electrons also stabilize the positive dipole charge on FE during retention and thus decrease the depolarization field. Erase operation (VERASE > 0) removes the electrons from FG and reverses the polarization of FE layer.

Fabrication and Experimental Results Fabrication procedure is outlined in Table I. 0.5 % solution of 70:30 P(VDF-TrFE) in MEK was spin coated and annealed at 140°C for 10 min [3] to obtain a film thickness of 35 nm . Subsequent processing of the hybrid device was limited below 110 °C. Control FE-FET and gate inject (01) Flash devices with the same corresponding FE layer and tunnel oxide thicknesses and identical EOTs were also fabricated for comparison. Fig. 2 shows hysteresis measurements for separate 80 nm thick PVDF MFM capacitors with inset (a) confirming the XRD peak in FE �-phase.

Hybrid devices showed larger LtVFB against FE-FET for VPROG > 10 V due to injected-electron contribution as seen in Fig. 3(a). Fig. 3(b) estimates the injected electron density and

contribution of FE switching to LtVFB in hybrid devices. No channel injection of electrons was observed until VPRoa=13 V

in all devices. 01 Flash showed poor LtVFB due to lesser tunnel oxide fields compared to hybrid devices. Reduced depolarization field improves retention in hybrid devices over

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FE-FET as seen in Fig. 4(a). 01 Flash also demonstrated limited retention due to inferior quality of top oxide constrained by present process integration. Hybrid device showed > 104 s retention and can present significantly better results with improved quality tunnel barrier. Fig. 4(b) shows retention characteristics in a single hybrid device for identical

LtVFB but different program condition. When programmed

with stronger pulse for shorter time, most of the LtVFB results from FE switching since dipole polarization responds significantly faster than charge injection. Therefore it shows poor retention on account of uncompensated depolarization field against programming with smaller pulse for a longer duration. During program, large amount of charge is trapped in the polycrystalline PVDF film {I-V of MFM devices in Fig. 2 inset (b)). This charge gradually leaks out to the gate with minimal positive bias in FE-FET thereby smearing C-V characteristics as seen in Fig. 5. The existence of the trapping layer in hybrid design provides an ideal sink to this leak path. Trapped charge in the FE layer is emitted to the trap layer assisted by the depolarization field. Fig. 6 shows calculated band diagram before and after charge relaxation and subsequent reduction in depolarization field which prevents C-V smearing in the hybrid cell. Fig. 7 illustrates pulsed program measurements indicating over 1 s saturation time. Presence of tunnel oxide reduces the fluence of charge in the FE film during PIE cycling which results in superior endurance of hybrid design as depicted in Fig. 8.

Simulation Results Electrostatic simulations incorporating FE hysteresis [4] were performed on the above gate stacks. Fig. 9 shows the decrease in the depolarization field with injected electrons. The stored electrons in the hybrid cell experience lower tunnel oxide fields during retention due to the counterbalancing positive surface charge on the FE compared to 01 Flash as seen in Fig. 10. Due to the huge electric displacement in the FE layer at small voltages, electric field is enhanced in the tunnel oxide (Fig. 11) during the PIE conditions that enables low-voltage operation. The charge storage increases the bottom oxide electric field during retention as displayed in Fig. 12, but renders sufficient design room for memory operation.

Scaling Implementation For the present geometry, Fig. 13 proposes a 40:60 division

of LtVFB=2.5 V into FE and stored charge showing reduced FE hysteresis of hybrid device over FE-FET. Seen in Table II, this benefits into 50 % reduced operating voltage, 70 % reduced depolarization field and significantly superior PIE and retention fields in top oxide over 01 Flash. Alternatively, shown in Fig. 14, to obtain realistic memory windows with inorganic FE films like BSTO or SBT [5] and 10 nm bottom oxide, hybrid design is more suited for aggressive scaling (in spite of increased EOT due to 3 nm tunnel oxide) than FE­FET due to lower FE thickness and longer retention for given PIE voltages.

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bottom oxide of hybrid memory 50% reduction in required SBT

follows FE-FET characteristics for thickness [5] even with

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higher LlV 10 V PIE operatIOn. TN.

T bl II Ad f FE h a e vantages 0 -c arg h b 'd d e lyl n esign Parameter Hybrid FE-FET GI )perating Voltage rVl 12 23 >20 Retention field top oxide [MV/cm] 1.89 - 4 Retention field bottom oxide [MV/cml -1.03 -0.64 -0.82 Program field top oxide rMV/cml (-12 V -6 - -4 Erase field too oxide rMV/cml (12 V) 7.6 - 7.8 Depolarization Field [kV/cm] 88.5 329 -

Table I Fabrication Procedure Step Hvbrid FE-FET GI

I.Thermal 98A 170A 230 bottom oxide A 2. PVDF 350A 350A N/A 3. Evap. lOA N/A lOA

Si02 4. 110 0( 25A N/A 25A

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References [1] T. P. Ma and I.-P. Han IEEE Elec. Dev. Lett. 23 386 (2002) [2] D. Wu et al Semi. Sci. Tech. 23, 7,075035 (2008) [3] G. A. Salvatore et al ESSDERC 2008 pp. 162-165 [4] H.-T. Lue, et al IEEE Tran. Elec. Dev 49 1790 (2002)

Figure 13 LlVrIF 2.5 V for hybrid memory has been split into 1 V through FE switching and 1.5 V by [5] S. Sakai et al IMW 2008 pp. 978 electron injection from the gate. FE in hybrid memory thus follows a smaller P-E loop against 2.5 V FE-FET. This provides electrostatic advantages over conventional devices as listed in Table II.

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