Session V.A (Corwin Pavilion East)

TunnelFETs

Tuesday PM, June 21S\ 2011

Session Chair: Heinz Schmid, IBM Zurich and William Frensley, University of Texas, Dallas

1 :30 PM V.A-1 Invited Paper Si-based Tunnel Field-Effect Transistors for Low-Power Nano-Electronics A. S. Verhulst1, W. G. Vandenbergh1,2, D. Leonelli1,2, R. Roo¥ackers1, A. Vandooren\ J. Zhuge4, K-H. Kao, B. Soree

1,5, W. Magnus

1,5, M. V. Fischetti , G. Pourtois

1, C.

Huyghebaert1, R. Huang4, Y. Wang4, K. De Me�er\ W. Dehaene1,2, M. M. Heyns1,3, and G. Groeseneken1,2, 1imec, Leuven, BELGIUM, Department of Electrical Engineering, 3Department of Metallurgy and Materials Engineering, K.U.Leuven, Leuven, BELGIUM,

41nstitute of Microelectronics, Peking University, Beijing, CHINA, 5Department of Physics, Universiteit Antwerpen, , Wilrijk, BELGIUM;

6Department of Materials Science and

Engineering, University of Texas Dallas, Richardson, Texas, USA

2:10 PM V.A-2 Compact Model and Performance Estimation for Tunneling Nanowire FET P. M. Solomon, D. J. Frank, and S.O. Koswatta, IBM, SRDC, T.J. Watson Research. Center, Yorktown Heights, New York, USA

2:30 PM V.A-3 Student Paper Using Dimensionality to Achieve a Sharp Tunneling FET (TFET) Turn-On S. Agarwal and E. Yablonovitch, University of Califomia, Berkeley, Califomia, USA

2:50 PM V.A-4 Investigation on Superlattice Heterostructures for Steep-Slope Nanowire FETs E. Gnani, P. Maiorano, S. Reggiani, A. Gnudi and G. Baccarani ARCES and DEIS, University of Bologna, Bologna, ITALY

3:10 PM Break

3:30 PM V.A-5 Student Paper Self-aligned Gate NanoPiliar Ino.53GaG.47As Vertical Tunnel Transistor D. K. Mohata, R. Bijesh, V. Saripalli, T. Mayer and S. Datta, The Pennsylvania State University, University Park, Pennsylvania, USA

3:50 PM V.A-6 Student Paper Self-aligned InAs/AIG.4sGao.ssSb vertical tunnel FETs G. Zhou1, Y. Lu

1, R. Li\ Q. Zhang

1, W. Hwang

1, Q. Liu

1, T. Vasen

1, H. Zhu

2, J. Ku0

2, S.

Koswatta3, T. Kosel1, M. Wistey1, P. Fai , A. Seabaugh1, and H. G. Xing1, 1D�artment of Electrical Engineering, University of Notre Dame, Notre Dame, Indiana, USA, IntelliEPl, Richardson, Texas, USA, and 31BM T. J. Watson Research Center, Yorktown Heights, New York, USA

4:10 PM V.A-7 Student Paper P-type Tunneling FET on Si (110) Substrate with Anisotropic Effect M. H. Lee

1, C.-Y. Kao

1, C.-L. Yang

1, and C.-H. Lee

2,

1 Institute of Electro-O�tical Science

and Technology, National Taiwan Normal University, Taipei, TAIWAN and Graduate Institute of Electronics Engineering (GlEE) and Department of Electrical Engineering, National Taiwan University, Taipei, TAIWAN

4:30 PM V.A-8 Late News

4:50 PM V.A-9 Late News

978-1-61284-244-8/11/$26.00 ©2011 IEEE 191

978-1-61284-244-8/11/$26.00 ©2011 IEEE 192