Double Gate MOSFET and its Application for Efficient Digital Circuits

Santosh Kumar Gupta Electronics & Communication Engineering Department

National Institute of Technology, Silchar Silchar, India–788010

e-mail: santoshty@gmail.com

1Gaurab G. Pathak, Debajit Das, Chandan Sharma Electronics & Communication Engineering Department

National Institute of Technology, Silchar Silchar, India–788010

e-mail: 1gaurabgunjan@gmail.com

Abstract— Double-Gate MOSFET (DGFET) is one of the promising technologies for sub-50 nm transistor design. To accommodate future technology nodes, transistor dimensions have to be reduced which leads to several disadvantages in transistor function. By using double-gate transistors many of these problems can be resolved to give efficient circuit performance. As we go for further scaling down, use of double-gate transistors in logic gate design gives significant improvements over conventional single-gate CMOS design. These are observed by comparing the designs of a full-adder circuit with single-gate and double-gate transistors using HSPICE simulations.

Keywords-double-gate; full-adder; HSPICE; PTM

I. INTRODUCTION In 1965 Gordon Moore predicted that the number of

transistors per chip would quadruple every three years [2]. In order to keep up with this, transistor dimensions have been reduced by half every three years. The sub-micron level was overcome in 1980’s. Silicon-on-Insulator (SOI) devices came into picture in 1990’s [2]. They give improved circuit speed and power consumption. However as transistor dimensions are shrunk, the close proximity between source and drain reduces the ability of the gate electrode to control the potential distribution and flow of current in the channel. This increases the electrostatic effect of the source/drain electrodes on the channel. As a result Short Channel Effects (SCEs) take prominence. To reduce SCEs we need to increase gate to channel coupling with respect to source/drain to channel coupling. For this planar CMOS requires high channel doping. But this leads to increased band-to-band tunneling, gate induced drain leakage and large variability due to channel doping level fluctuations. So, conventional bulk MOSFET cannot be scaled down below 20 nm [2]. These limitations can be overcome by the double-gate (DG) MOSFETs. With one more gate the gate to channel coupling is doubled resulting in good suppression of SCE’s [1, 2].

II. BASIC DESIGN AND TYPES OF DGFET The main idea of a double-gate MOSFET (DGFET) is to

have a Si channel of very small width and to control the Si channel by applying gate contacts to both sides of the channel. The double gate concept can be garnered from the fully depleted (FD) SOI structures [2]. If the buried oxide

thickness is reduced to that of the gate dielectrics and if the ground plane is electrically connected to the transistor gate, then the ground plane acts as a second gate. The double-gate structure is comprised of a conducting channel usually undoped surrounded by gate electrodes on either side.

The most common mode of operation is to switch both gates simultaneously. Another mode is to switch only one gate and apply bias to the other (back gate). DGFET is of the following types [4]-

a. Planar (Gates and channel are horizontal) b. Vertical (Conduction direction is vertical), c. FinFET (Channel is vertical; conduction is

parallel to wafer surface). A general DGFET structure is shown in Fig. 1 [3].

Figure 1. A General Double Gate MOSFET (DGFET) structure.

III. ADVANTAGES OF DGFET The double-gate concept considerably increases the

efficiency of transistors as they are scaled down as compared to planar CMOS. The gate to channel coupling is doubled and hence SCE’s are easily suppressed. Very lowly doped or even undoped channel can be used in DGFETs. This gives good carrier mobility in reduced dimensions and hence better intrinsic switching time. The leakage currents or off-state currents are reduced. The current driving capability of DGFET is twice that of planar CMOS and hence DGFETs can be operated at much lower input and threshold voltages. Hence power consumption is less in DGFETs. Due to the presence of two gates no part of the channel is far away from the gate. The voltage applied on the gate terminals control the electric field, determining the amount of current flow through the channel. This gives an

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ideal sub-threshold slope for suitable sub-threshold operation. Hence DGFETs can be operated at much lower voltages [1, 2].

IV. DOUBLE GATE (DG) MOSFET DIGITAL CIRCUITS The three most important metrics for measuring the

quality of a digital circuit are (1) area, (2) power and (3) delay [5]. With MOSFET scaling the size of circuits are bound to be reduced. But as we have seen planar CMOS transistors cannot be scaled down much as it gives rise to many undesirable effects. So for reduced feature size DGFETs are to be employed.

The power dissipation in a logic circuit is of three types- (i) static, (ii) dynamic and (iii) short circuit. The static power dissipation is due to the leakage currents which are largely reduced in DGFETs. So double-gate design will give less static power dissipation. The dynamic power dissipation can be expressed as 2=d L DDP C V f (1)

Where LC is the capacitive load, f is the clock frequency, and DDV is the supply voltage [6]. Thus at low operating voltages dynamic power dissipation ( dP ) is less. So, DGFET is more suitable as it can operate at much lower voltages than planar CMOS. The short circuit power dissipation depends on the intrinsic switching time which again depends on the supply voltage. Thus DGFET can reduce the short circuit power dissipation with small operating voltages. Due to these reduced power dissipation in DGFET circuits, the delay time is considerably less. Moreover with the use of undoped channel, carrier mobility’s are not affected by reduced dimensions. Hence use of DGFET for digital circuit is far more advantageous than planar CMOS as regards MOSFET scaling.

V. SIMULATION FRAMEWORK AND RESULTS A basic full adder circuit is as shown in Fig. 2. The sum ( S ) is = ⊕ ⊕S A B C (2) The carry-out ( OUTC ) is = + +OUTC AB BC CA (3) where A , B and C are inputs. First we implement the above circuit using the in-built

HSPICE MOSFET (single gate MOSFET) model level 57. The standard transistor dimensions are - width ( ) 1μ=W m , length ( ) 1μ=L m . At various input voltages, the power dissipated and delays are calculated for both sum (S) and carry-out (COUT) by HSPICE simulations. The results are tabulated as follows in Table I and Table II.

It is observed that power dissipation decreases with decrease in supply voltage, but at voltages less than around 0.8 V, the delay times show a rise. This is because below 0.8 V, it is in the sub-threshold region with less drive current. So optimum operating voltage for the adder, using single-gate MOSFET which gives the minimum delay is around 0.8V.

Figure 2. Implemented Full-Adder circuit.

TABLE I. RESULTS FOR POWER AND DELAY OF SUM FOR SINGLE GATE MOSFET ADDER CIRCUIT

Supply voltage

( )DDV

Power dissipated

( )μW

Rise time

( )ns

Fall time

( )ns Propagation delay ( )ns

0.9 2.5415 1.9436 2.0556 1.99960.8 1.8051 2.1427 2.1472 2.14490.7 1.2243 2.4603 2.4164 2.43840.6 0.7729 2.9546 2.8442 2.89940.5 0.4509 3.6583 3.4859 3.57210.4 0.2403 4.8538 4.6030 4.72840.3 0.1106 7.4715 7.3306 7.4010

TABLE II. RESULTS FOR DELAY OF COUT FOR THE SINGLE GATE MOSFET ADDER CIRCUIT

Supply voltage

( )DDV

Rise time

( )ns Fall time

( )ns

Propagation delay ( )ns

0.9 1.9140 2.4154 2.16470.8 2.0686 2.6343 2.35150.7 2.3441 2.9490 2.64660.6 2.7381 3.4778 3.10790.5 3.3183 4.2807 3.79950.4 4.3482 5.9114 5.12980.3 6.6793 9.4564 8.0679

The propagation delay ( )pdT is calculated from rise time

delay ( )riseT and fall time delay ( )fallT as-

2+

= rise fallpd

T TT (4)

From the above data, the variation of average power dissipated and propagation delay are as shown in Fig. 3.

Now, the same adder circuit is implemented with double-gate MOSFET transistors. For simulation we have used the PTM 32 nm FinFET model [8]. It is noteworthy that FinFET is the most useful double-gate structure because of the self-alignment of the two gates. Here tied gates are used, that is, both the gates are switched simultaneously.

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TABLE III. RESULTS FOR POWER AND DELAY OF SUM FOR DOUBLE GATE MOSFET ADDER CIRCUIT

TABLE IV. RESULTS FOR POWER AND DELAY OF COUT FOR DOUBLE GATE MOSFET ADDER CIRCUIT

Figure 3. Variation of power and delay with input voltage (single-gate)

The transistor dimensions are- Width ( )W = 80 nm, length ( )L = 32 nm. At various

input voltages, the power dissipated and delays are

calculated for both sum (S) and carry-out (COUT) by HSPICE simulations. The results have been tabulated in Table III and Table IV.

From the above data the variation of average power dissipated and propagation delay is observed as in Fig. 4. It is observed that power dissipation decreases with decrease in supply voltage, but at voltages less than 0.4 V-0.3 V, the delay times shows a rise. This is because below 0.4 V-0.3 V, it is in the sub-threshold region where DGFET shows ideal voltage transfer characteristics with less drive current. So, optimum operating voltage for the adder using double-gate gives the minimum delay of 0.4V-0.3V.

Figure 4. Variation of power and delay with input voltage (DGFET).

Figure 5. Variation of energy-delay product with input voltage for DGFET

The energy delay product is an important parameter for circuit design. Optimization of energy-delay product is

Supply voltage

( )DDV

Power dissipated

( )μW

Rise time

( )ns

Fall time

( )ns

Propagation delay ( )ns

0.9 1.0686 0.137 0.3617 0.24940.8 0.7986 0.1412 0.3626 0.25690.7 0.5758 0.1528 0.3689 0.26580.6 0.3967 0.1660 0.3745 0.27020.5 0.2630 0.1905 0.3854 0.28790.4 0.1605 0.1935 0.3997 0.29160.3 0.0870 0.2467 0.4875 0.36710.2 0.0382 0.9217 1.735 1.32830.18 0.0311 1.4391 2.5035 1.97130.15 0.0222 3.0720 4.9982 4.0351

Supply

( )DDV Rise time

( )ns Fall time

( )ns Propagation

( )ns Energy

( )1510−× J0.9 0.07217 0.3749 0.2235 181.8540.8 0.07298 0.3839 0.2374 147.6880.7 0.07432 0.3915 0.2414 101.7730.6 0.07507 0.4267 0.2584 69.0720.5 0.08082 0.4385 0.2647 45.3640.4 0.09402 0.4589 0.2765 27.73360.3 0.15517 0.5149 0.3350 14.96640.2 0.5847 1.9065 1.2456 6.49920.18 0.9171 2.5577 1.7374 5.24460.15 1.8800 5.0600 3.4700 3.6226

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obtained at its minimum value. Both energy and delay depend on the supply voltage. From the above data, the energy delay product variation with supply voltage is shown in Fig. 5.

As observed the energy delay product is minimum at around 0.3 V. At voltages less than 0.3 V, the energy delay product increases slightly as we enter into the sub-threshold region. Thus for adder circuit with double-gate concept, we get minimum energy-delay product and minimum power dissipation around 0.4 V-0.3 V.

Figure 6. Comparison of power, sum propagation delay and carry propagation delay for single-gate and double-gate adders.

Comparing the sub-threshold characteristics of both single-gate and double-gate adder circuits, we observe that the variation of power and delay in the sub-threshold region

is more prominent in single-gate design compared to double-gate. This is due to control of sub-threshold slope degradation and reduced leakage currents in DGFET due to greater gate to channel coupling.

A comparison of average power and propagation delays of the single-gate and double-gate adder circuits at their minimum operating voltages is shown in Fig. 6. As can be observed in the figure power and propagation delays have considerably lowered with the use of the DGFETs.

VI. CONCLUSION From the discussion and results we clearly observe that

DGFET adder circuit is more efficient than CMOS adder circuit for reduced transistor feature size. The DGFET adder circuit can operate at much lower voltages than planar CMOS added. The power dissipated, rise time delay, fall time delay and propagation delay are much less in DGFET design. Moreover the sub-threshold region exhibits less power and delay compared to CMOS design.

REFERENCES [1] Amara Amara, Oliver Rozeau, Editors,Planar Double-Gate Transistor

From Technology to Circuit, Springer, 2009, pp. 1-20. [2] Jean-Pierre Colinge, Editor, FinFET and Other Multi-Gate

Transistors, Springer, 2008, pp 1-13. [3] Kavita Ramasamy, Cristina Crespo, “Double-Gate MOSFETs,”

Portland State University, ECE 515- Winter 2003. [4] Mike Duffy, Eric Dattoli, Alain Espinosa, “Nanoscale Silicon

Technology” [5] Chetan Nagendra, Robert Michael Owens, and Mary Jane Irwin, [6] “Power-Delay Characteristics of CMOS Adders,” IEEE

Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2,no. 3, p. 377, September 1994

[7] Srinivasa R. Vemuru, and Norman Scheinberg, “Short-Circuit Power Dissipation Estimation for CMOS Logic Gates,” IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, vol. 41, no. 11, p.762, November 1994.

[8] Predictive Technology Model, http://ptm.asu.edu.

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