Abstract Uniform nanotube diameter and nanoarray pitch are

essential for low-cost and high-yield manufacturability of billions of carbon nanotube MOSFETs (CN-MOSFETs) with various sizes on a single chip. In this paper, the optimum uniform diameter and pitch of 16nm n-type CN-MOSFETs are determined with two different substrate bias voltages for a wide range of transistor sizes. A new quality metric is evaluated to identify the optimum device profiles suitable for very large scale integration.

Keywords Carbon nanotube very large scale integration (VLSI),

CN-MOSFET technology, uniform nanotube diameter, uniform nanoarray pitch, charge screening effect.

1. Introduction Carbon nanotube (CN) transistors display superior

properties as compared to silicon MOSFETs [1], [2]. Transistors with various driving strengths (different channel widths) are required to implement complex integrated circuits with the carbon nanotube technology. Nanotube diameter and nanoarray pitch play the most important roles in determining the performance and integration density of CN-MOSFETs [1], [2].

A multi-diameter (multi-threshold voltage) CN-MOSFET technology could be attractive for achieving superior logic and memory circuits [4]-[6]. For example, dual-diameter CN-MOSFET memory cells with enhanced data stability and faster data transfer characteristics are presented in [4]. In [5] and [6], new ternary logic gates are proposed with dual-diameter and triple-diameter CN-MOSFETs. To this day, however, there is no multi-diameter CN-MOSFET technology that has been successfully demonstrated by fabrication and experimental measurement of large scale integrated circuits. Controlled production of carbon nanotubes with different diameters or pitch values would require a significantly more complex fabrication process as compared to the technologies that are currently available [10]-[12]. Uniform nanotube diameter and nanoarray pitch are required (excluding the imperfections due to process parameter variations) among all the transistors on a chip fabricated with the current CN-MOSFET processing techniques.

Optimum device profiles for developing novel superior circuits with CN-MOSFETs are presented in [1] and [2]. A manufacturable uniform diameter is presented for achieving high-speed n-type CN-MOSFETs with various sizes in [1]. Alternative device profiles for achieving low-power and low-leakage n-type CN-MOSFETs with higher Ion/Ioff ratio are discussed in [2]. Transistor size optimization spaces

considered in [1] and [2] are however very limited to be useful for VLSI. A wide range of transistor sizes is not explored in [1] and [2]. Furthermore, the nanoarray pitch (s) is impractically long (s = 1µm) in these previous studies. The area efficiency is too low to be appropriate for VLSI.

In this paper, nanotube diameter and nanoarray pitch are concurrently optimized and unified for a practical high-performance carbon nanotube VLSI technology with high integration density. A new electrical metric is evaluated to identify a uniform pitch suitable for achieving high switch performance while maintaining high area efficiency. The study is based on the Stanford CN-MOSFET HSPICE compact model [7].

The paper is organized as follows. The previous work on diameter optimization of 16nm n-type CN-MOSFETs is reviewed in Section 2. Uniform diameter and pitch for achieving high-speed n-type CN-MOSFETs are identified with a high substrate bias voltage in Section 3. Alternative device profiles for achieving a low-leakage carbon nanotube transistor technology suitable for low-power chip design are presented in Section 4. The performances of high-speed and low-leakage devices are compared in Section 5. Finally, some conclusions are offered in Section 6.

2. Previous Work on Diameter Optimization of 16nm N-type CN-MOSFETs

In this section, the previous work on diameter optimization of 16nm n-type CN-MOSFETs is reviewed. In [1], high device speed is achieved by connecting the substrate (bottom gate) to the power supply (Vsub = VDD = 0.7V). Although channel inversion current (Ion) is enhanced, the subthreshold leakage current (Ioff) is also increased since the device can not be strongly cut-off with a high substrate bias voltage. The maximum achievable Ion/Ioff and the overall switch performance are thereby degraded with a higher substrate bias voltage. Alternative n-type CN-MOSFET profiles with a lower substrate voltage (Vsub = 0V) are presented in [2] for achieving lower subthreshold leakage current and enhanced overall switch performance. The performance of a transistor is characterized by Ion/Ioff in [1] and [2].

The strength of a CN-MOSFET is tuned by adjusting the number of tubes in the channel array. For a specific number of tubes and a fixed nanoarray pitch, enlarging the nanotube diameter increases both Ion and Ioff. When the nanotube diameter is enlarged, Ion and Ioff are increased at different rates. The Ion/Ioff is therefore maximized at an optimum diameter (dOPT). The optimum diameter for achieving maximum Ion/Ioff is however dependent on the transistor size [1], [2]. Controlled fabrication of nanotubes with different diameters for various sizes of CN-MOSFETs on a complex chip is not feasible with

Uniform Diameter and Pitch Co-Design of 16nm N-type Carbon Nanotube Channel Arrays for VLSI

Yanan Sun and Volkan Kursun Department of Electronic and Computer Engineering

The Hong Kong University of Science and Technology Clear Water Bay, Kowloon, Hong Kong

{eesyun, eekursun}@ust.hk

978-1-4577-0144-3/11/$26.00 ©2011 IEEE 211 3rd Asia Symposium on Quality Electronic Design

the existing process technologies. A uniform nanotube diameter suitable for a low-cost and high-yield single-Vth

CN-MOSFET technology is explored in [1] and [2]. The average value of the optimum nanotube diameters of a small set of transistor sizes is recommended as the uniform diameter for all of the transistors that are fabricated across a chip [1], [2].

A uniform nanoarray pitch of 1μm is assumed in [1] and [2] for eliminating the charge screening effect in the optimization process. This pitch is however impractically long from an integration density point of view. High-performance transistor profiles with a long pitch display very limited practical value for VLSI. Pitch and diameter optimization efforts need to be unified considering the integration density, device speed, and leakage current constraints in chip design. In this paper, uniform diameter and pitch values are determined with a comprehensive optimization study for achieving high-performance n-type CN-MOSFETs with different sizes and substrate bias voltages.

3. Diameter and Pitch Uniformity for Various Sizes of Transistors: High-Speed Device Profiles

In this section, both nanotube diameter and nanoarray pitch are concurrently optimized for achieving high-speed n-type CN-MOSFETs. All of the carbon nanotubes are assumed to be semiconducting with uniform inter-tube pitch. Fabrication imperfections such as diameter variations and metallic nanotubes are not considered in this paper. The supply voltage (VDD) is 0.7V for 16nm technology node (from ITRS [8]). The die temperature is assumed to be 90°C (a typical hot-spot temperature in current multi-core microprocessors [9]). The substrate is connected to the power supply (Vsub = 0.7V) [1]. The on-state current (Ion) is the drain current at VGS = VDS = VDD = 0.7V. The off-state current (Ioff) is the subthreshold leakage current at VGS = 0V and VDS = VDD = 0.7V.

3.1 Uniform Nanotube Diameter Selection for High-Speed N-type CN-MOSFETs with Negligible Charge Screening Effect

In this section, the uniform optimum diameter for achieving high-speed n-type CN-MOSFETs of various sizes is explored with Vsub = 0.7V. As presented in [1], for a specific number of tubes (N), Ion/Ioff is maximized at an optimum diameter (dOPT_0.7V). Similar to nanotube diameter, nanoarray pitch also influences the switch performance due to charge screening effect. The optimum diameter that maximizes the performance is however independent of the nanoarray pitch [1], [2]. Similar to the studies in [1] and [2], the diameter dependent performances of CN-MOSFETs (of various sizes) are initially examined assuming a relatively long pitch of 1μm. Charge screening effect is negligible at such long distances among nanotubes that form the channel array. The influence of nanoarray pitch on device performance is thereby eliminated in the initial step of this optimization study. A uniform optimum nanotube diameter that is independent of the nanoarray pitch is determined in this section. The diameter and pitch optimization studies are later unified for achieving enhanced integration density in addition to high device speed in Section 3.2.

The optimum diameter that maximizes Ion/Ioff is reduced with increased transistor size (higher number of tubes) [1]. Producing multiple nanotube diameters or pitch values for different transistors across a chip would require a significantly more complex and expensive fabrication process as discussed in Section 2. Uniform nanotube diameter and nanoarray pitch are required for very large scale integration of CN-MOSFETs with the current relatively simpler and lower cost carbon nanotube transistor fabrication techniques.

The ideal maximum Ion/Ioff is observed at an optimum diameter that is unique for a specific transistor size. In a practical single-diameter CN-MOSFET technology, using a nanotube diameter that differs from this unique optimum diameter causes a degradation in device performance characterized by Ion/Ioff. To determine a uniform diameter that is suitable for various sizes of transistors across a chip, the degradations / departures from the ideal maximum Ion/Ioff for different numbers of tubes and various potentially attractive uniform diameters are evaluated as shown in Fig. 1. Without loss of generality, up to 30% degradation from the ideal maximum Ion/Ioff is assumed to be acceptable for providing sufficiently high performance with a uniform carbon nanotube diameter. A wide range of transistor sizes with 1 ≤ N ≤ 1000 is considered in this study.

1 10 100 1000

0

10

20

30

40

50

60

70

80

d1 = 0.872nm (1 ≤ N ≤ 5)

d2 = 0.839nm (1 ≤ N ≤ 12)

d3 = 0.828nm (1 ≤ N ≤ 17)

d4 = 0.804nm (1 ≤ N ≤ 27)

d5 = 0.793nm (1 ≤ N ≤ 33)

d6 = 0.781nm (1 ≤ N ≤ 40)

d7 = 0.756nm (1 ≤ N ≤ 60)

d8 = 0.705nm (6 ≤ N ≤ 175)

d9 = 0.691nm (8 ≤ N ≤ 280)

d10

= 0.677nm (11 ≤ N ≤ 450)

d11

= 0.649nm (18 ≤ N ≤ 1000)

Number of tubes (N)

Deg

rada

tion

from

Ide

al M

axim

um I

on/I

off

(%)

Vsub

= 0.7V, s = 1m, T = 90oC

Figure 1: The degradations from the ideal maximum Ion/Ioff

(observed at dOPT_0.7V) at different potential uniform diameters for various sizes of high-speed transistors. Vsub = 0.7V. The 30% degradation from the ideal maximum Ion/Ioff is demarcated with a horizontal line.

Since the diameter and conductive properties of a carbon nanotube are determined by the chirality vector (n, m) [1], the diameters required to achieve semiconducting carbon nanotubes form a set of discrete numbers. Some of the uniform diameter options considered in this study are listed in Fig. 1 legend. The range of numbers of tubes for which the degradations from the ideal maximum Ion/Ioff are maintained below 30% is also indicated in parenthesis in Fig. 1 legend. For example, with a uniform diameter of d3 = 0.828nm, the degradation from the ideal maximum Ion/Ioff is smaller than 30% for 1 ≤ N ≤ 17. However, for larger transistors with N ≥

30% degradation demarcation line d7

d3

d11

17, the degradation is further increased up to 94% with this uniform diameter. Alternatively, if d11 = 0.649nm is employed as the uniform diameter, the degradation from the ideal maximum Ion/Ioff is below 30% for 18 ≤ N ≤ 1000. The performance degradation for smaller transistors is however increased up to 75%. Similar analysis is conducted for many other potentially suitable diameters. As shown in Fig. 1, no single uniform diameter can maintain the performance degradation below 30% for the whole range of transistor sizes considered in this study.

Since small transistors are more commonly used in VLSI circuits, d7 = 0.756nm could be the uniform diameter of all the n-type transistors in a 16nm high-speed CN-MOSFET technology. As shown in Fig. 1, with a uniform diameter of dUNI_0.7V = 0.756nm, Ion/Ioff differences as compared to the ideal transistor profiles are less than 30% for 1 ≤ N ≤ 60. For larger transistors with N > 60, the Ion/Ioff degradation exceeds 30%.

3.2 Uniform Nanoarray Pitch Selection for High-Speed N-type CN-MOSFETs with Uniform Diameter

Similar to the studies in [1] and [2], the uniform diameter is identified with a large nanoarray pitch of 1μm in Section 3.1. In this section, a more practical uniform pitch value is explored together with the uniform diameter that was determined in Section 3.1. Identification of a shorter nanoarray pitch is essential for achieving high-speed n-type CN-MOSFETs of various sizes that are fit for compact VLSI chips.

Although pitch does not influence the optimum diameter that maximizes performance, a shorter pitch is desirable to enhance the integration density (by reducing the physical gate width of transistors, Wg) of a chip with a CN-MOSFET technology [1]. For a fixed number of tubes in a nanoarray, however, lowering the pitch to reduce device area simultaneously degrades Ion and Ion/Ioff due to enhanced charge screening effect [1]. There is therefore a tradeoff between device area and performance when the nanoarray pitch is reduced.

A comprehensive new metric is evaluated in this paper to identify a practical uniform pitch value that can maintain high switch performance while also achieving a higher integration density. The Quality Metric is:

*on

off g

IQuality Metric

I W , (1)

where Wg is the physical gate width. Wg determines the total area of a CN-MOSFET [1]. Physical gate width is

( 1) 2g CN ovW s N d W , (2)

where nanoarray pitch (s) is the distance between the centers of two adjacent nanotubes that form the channel array of a CN-MOSFET. N is the number of tubes and dCN is the diameter of nanotubes in the channel array. Wov is the overhang width of the gate from the edge of the CN array. Wov at each end is assumed to be 2λ (16nm) [1] in this study.

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

0

5

10

15

20

25

30

35

40

45

Pitch (nm)

Qua

lity

Met

ric (

x 10

12)

Vsub

= 0.7V,

dUNI_0.7V

= 0.756nm,

(n, m) = (1, 9), (9, 1), (5, 6), or (6, 5)

Figure 2: The variations of Quality Metric with nanoarray pitch for various sizes of high-speed transistors (2 ≤ N ≤ 1000). Uniform diameter = 0.756nm. Vsub = 0.7V.

To determine a uniform nanoarray pitch suitable for VLSI, the variations of Quality Metric with pitch at the uniform diameter of dUNI_0.7V = 0.756nm for a wide range of transistor sizes are illustrated in Fig. 2. The nanoarray pitch cannot be smaller than the diameter of the nanotubes that form the channel array. The minimum pitch value considered in this study is therefore the nanotube diameter. Alternatively, the maximum nanoarray pitch feasible for maintaining high integration density is assumed to be 30nm.

As shown in Fig. 2, when N is increased from 2 to 1000, the optimum pitch that maximizes the Quality Metric is increased from 5.6nm to 6.4nm. The span of optimum pitch values is relatively narrow given the wide range of numbers of tubes that is considered in this study. Furthermore, the tips of the quality metric curves are relatively flat. Therefore, the average value (6nm) of 5.6nm and 6.4nm can be selected as the uniform pitch of all the CN-MOSFETs across a chip. The degradations from the maximum achievable Quality Metric are maintained below 10% by using sUNI_0.7V = 6nm as the uniform pitch for 2 ≤ N ≤ 1000.

Transistor sizing in a CN-MOSFET is performed by adjusting the number of carbon nanotubes in the channel array underneath the gate terminal. To enhance device speed and Ion, more nanotubes are added to the channel array of a CN-MOSFET. Wg is increased more significantly as compared to Ion/Ioff when more nanotubes are added to the channel array. Although Ion and Ion/Ioff are enhanced, the overall Quality Metric is degraded with the increased number of tubes in a CN-MOSFET channel array as shown in Fig. 2.

4. Diameter and Pitch Uniformity for Various Sizes of Transistors: Low-Leakage Device Profiles

Due to the aggressive scaling of CMOS technology, the subthreshold leakage currents contribute significantly to the total power consumption of an integrated circuit [3]. Low-leakage transistors are widely used for energy-efficiency in battery-powered portable devices. In this section, the uniform diameter and pitch are re-evaluated to identify

s = 5.6nm, N = 2

N is increased from 2 to 1000

s = 6.4nm, N = 1000

low-leakage and compact n-type CN-MOSFET profiles suitable for energy-efficient IC design. The substrate is connected to ground (0V) [2]. N-channel CN-MOSFETs with lower substrate voltage suppress the leakage currents and thereby enhance the overall switch quality as presented in [2].

Similar to the optimization process presented in Section 3, the uniform diameter is initially determined with a nanoarray pitch of 1μm in Section 4.1. In Section 4.2, a more practical (shorter) uniform pitch value is investigated using the overall switch Quality Metric. An n-type CN-MOSFET profile that is suitable for low-leakage integrated circuit design is presented.

4.1 Uniform Nanotube Diameter Selection for Low-Leakage N-type CN-MOSFETs with Negligible Charge Screening Effect

In this section, the uniform optimum diameter for achieving low-leakage n-type CN-MOSFETs of various sizes is explored with Vsub = 0V. The degradations from the ideal maximum Ion/Ioff (observed at dOPT_0V [2]) at different potential uniform diameters for various sizes of transistors are shown in Fig. 3. The range of numbers of tubes for which the performance degradation as compared to the ideal switch is less than 30% is also indicated in parenthesis in Fig. 3 legend for each diameter.

1 10 100 1000

0

10

20

30

40

50

60

70

d8 = 0.872nm (1 ≤ N ≤ 54)

d9 = 0.839nm (1 ≤ N ≤ 125)

d10

= 0.828nm (2 ≤ N ≤ 165)

d11

= 0.804nm (4 ≤ N ≤ 320)

d12

= 0.793nm (5 ≤ N ≤ 400)

d13

= 0.781nm (7 ≤ N ≤ 515)

d14

= 0.756nm (17 ≤ N ≤ 850)

d1 = 0.993nm (1 ≤ N ≤ 6)

d2 = 0.974nm (1 ≤ N ≤ 8)

d3 = 0.964nm (1 ≤ N ≤ 10)

d4 = 0.935nm (1 ≤ N ≤ 16)

d5 = 0.914nm (1 ≤ N ≤ 23)

d6 = 0.893nm (1 ≤ N ≤ 34)

d7 = 0.883nm (1 ≤ N ≤ 42)

Vsub

= 0V, s = 1m, T = 90oC

Deg

rada

tion

from

Ide

al M

axim

um I

on/I

off (

%)

Number of tubes (N) Figure 3: The degradations from the ideal maximum Ion/Ioff

(observed at dOPT_0V) at different potential uniform diameters for various sizes of low-leakage transistors. Vsub = 0V. The 30% degradation from the ideal maximum Ion/Ioff is demarcated with a horizontal line.

As shown in Fig. 3, there does not exist a single uniform diameter that can maintain the Ion/Ioff degradations as compared to the ideal switches smaller than 30% for the whole range of transistor sizes with Vsub = 0V. A uniform diameter of d9 = 0.839nm could be employed to maintain the Ion/Ioff degradation below 30% for the relatively smaller transistors with 1 ≤ N ≤ 125. For larger CN-MOSFETs with N > 125 and a uniform diameter of dUNI_0V = 0.839nm, Ion/Ioff difference as compared to an ideal switch can not be maintained below 30%.

4.2 Uniform Nanoarray Pitch Selection for Low-Leakage N-type CN-MOSFETs with Uniform Diameter

The Quality Metric defined in (1) is used to identify a feasible uniform pitch for achieving low-leakage and area efficient n-type CN-MOSFETs with Vsub = 0V in this section. The variations of Quality Metric with pitch at a uniform diameter of dUNI_0V = 0.839nm for 2 ≤ N ≤ 1000 are illustrated in Fig. 4.

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

0

5

10

15

20

25

30

35

40

45

50V

sub = 0V,

dUNI_0V

= 0.839nm,

(n, m) = (4, 8) or (8, 4)

Pitch (nm)

Qua

lity

Met

ric

(x 1

012)

Figure 4: The variations of Quality Metric with nanoarray pitch for various sizes of low-leakage transistors (2 ≤ N ≤ 1000). Uniform diameter = 0.839nm. Vsub = 0V.

As shown in Fig. 4, the optimum pitch that maximizes the Quality Metric varies between 3.6nm and 7nm for 2 ≤ N ≤ 1000. Similar to the approach in Section 3.2, a uniform pitch of sUNI_0V = 5.3nm (the average value of 7nm and 3.6nm) could be used to maintain the degradations from the maximum achievable Quality Metric below 10% for 2 ≤ N ≤ 1000.

5. Comparison of High-Speed and Low-Leakage Device Profiles

Performances of low-leakage (at Vsub = 0V) and high-speed n-type CN-MOSFETs (at Vsub = 0.7V) are compared in this section. The uniform nanotube diameter and nanoarray pitch values recommended for low-leakage and high-speed device profiles are summarized in Table 1. The variations of Ion and Ioff with the number of tubes in low-leakage and high-speed CN-MOSFETs are shown in Fig. 5.

The uniform diameter is larger (dUNI_0V > dUNI_0.7V) while the uniform pitch (sUNI_0V < sUNI_0.7V) is shorter in low-leakage CN-MOSFETs as compared to the high-speed transistors as listed in Table 1. Although the recommended uniform diameter is larger, the channel inversion in low-leakage CN-MOSFETs is weaker due to stronger charge screening effect (smaller-pitch) and lower substrate bias voltage as compared to the high-speed CN-MOSFETs as shown in Fig. 5. The percent difference of Ion between the low-leakage and high-speed CN-MOSFETs with various sizes is partially listed in Table 2. When the number of tubes is increased from 1 to

N is increased from 2 to 1000

s = 3.6nm, N = 1000

s = 7nm, N = 2

30% degradation demarcation line

1000, Ion produced by low-leakage CN-MOSFETs is 0.3% to 12.9% lower as compared to the high-speed CN-MOSFETs as listed in Table 2.

Table 1: Uniform diameter and pitch values recommended for high-speed and low-leakage 16nm n-type CN-MOSFETs.

16nm N-type CN-MOSFET Uniform Diameter (nm) Uniform Pitch (nm)

Vsub = 0.7V (High-speed) 0.756 6 Vsub = 0V (Low-leakage) 0.839 5.3

0 200 400 600 800 1000

1E-3

0.01

0.1

1

I off (

nA)

High-speed CN-MOSFETs with Vsub

= 0.7V, dUNI_0.7V

= 0.756nm, s = 6nm

Low-leakage CN-MOSFETs with Vsub

= 0V, dUNI_0V

= 0.839nm, s = 5.3nm

I on (

mA)

Number of tubes (N)

0.01

0.1

1

Figure 5: The variations of Ion and Ioff with the number of tubes (1 ≤ N ≤ 1000). Strong inversion and weak inversion currents of the low-leakage and high-speed CN-MOSFETs are compared.

Table 2: Percent differences of Ion, Ioff, and Ion/Ioff between low-leakage and high-speed CN-MOSFETs.

Percent Difference (%)

N* = 1 N = 10 N = 100 N = 1000

Ion 0.3 10.1 12.6 12.9

Ioff 2.1 28.7 57.2 63

Ion/ Ioff 1.9 26.1 104.1 135 *All the device sizes for 1 ≤ N ≤ 1000 are considered in this study. Only four transistor sizes are listed in the table due to limited space.

Although strong inversion current (and therefore device speed) is degraded in low-leakage CN-MOSFETs, the weak inversion current Ioff is also significantly suppressed primarily due to lower substrate bias voltage as compared to the high-speed CN-MOSFETs as shown in Fig. 5. Ioff produced by low-leakage CN-MOSFETs is 2.1% to 63% lower as compared to the high-speed CN-MOSFETs for 1 ≤ N ≤ 1000 as listed in Table 2.

The variation of overall switch performance (Ion/Ioff) with the transistor sizes (number of tubes) is illustrated in Fig. 6. Due to more significant reduction of Ioff as compared to Ion, Ion/Ioff offered by low-leakage CN-MOSFETs is 1.9% to 135% higher as compared to high-speed CN-MOSFETs depending on the number of tubes in the channel array (1 ≤ N ≤ 1000) as listed in Table 2.

0 100 200 300 400 500 600 700 800 900 10000

2

4

6

8

10

12

High-speed CN-MOSFETs, Vsub

= 0.7V, dUNI_0.7V

= 0.756nm, s = 6nm

Low-leakage CN-MOSFETs, Vsub

= 0V, dUNI_0V

= 0.839nm, s = 5.3nm

Number of tubes

I on/I

off (

x 1

06 )

Figure 6: The variation of Ion/Ioff with the number of tubes (1 ≤ N ≤ 1000). Performances of the low-leakage and high-speed device profiles are compared.

6. Conclusions For a low-cost and high-yield carbon nanotube VLSI

technology, nanotube diameter and nanoarray pitch values that are uniform across all the transistors on a chip are desirable. Diameter and pitch are concurrently optimized to identify high-speed and low-leakage n-type CN-MOSFET profiles fit for very large scale integration with two different substrate bias voltages and different transistor sizes in this paper.

A new quality metric is evaluated to determine a practical uniform pitch value that satisfies both high performance and area efficiency requirements of a complex integrated circuit. The recommended uniform nanotube diameter and nanoarray pitch values for achieving maximum switch performance while maintaining high integration density with a 16nm n-type CN-MOSFET technology are listed in Table 1.

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16nm n-channel carbon-nanotube transistors for manufacturability,” Proceedings of the IEEE International Conference on Microelectronics, pp. 28-31, December 2010.

[2] Y. Sun and V. Kursun, “Leakage current and bottom gate voltage considerations in developing maximum performance 16nm n-channel carbon nanotube transistors,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2513-2516, May 2011.

[3] V. Kursun and E. G. Friedman, Multi-Voltage CMOS Circuit Design. New York: Wiley, 2006.

[4] S. Lin, Y. Kim, and F. Lombardi, “Design of a CNTFET-based SRAM cell by dual-chirality selection,” IEEE Transactions on Nanotechnology, Vol. 9, No. 1, pp. 30-37, January 2010.

[5] H. Nan and K. Choi, “Novel ternary logic design based on CNFET,” Proceedings of the IEEE International SoC Design Conference, pp. 115-118, November 2010.

[6] S. Lin, Y. Kim, and F. Lombardi, “CNTFET-based design of ternary logic gates and arithmetic circuits,” IEEE Transactions on Nanotechnology, Vol. 10, No. 2, pp. 217-225, March 2011.

[7] http://nano.stanford.edu/model.php?id=23. [8] http://www.itrs.net/Links/2009ITRS/Home2009.htm. [9] B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L.

Jiang, G. H. Loh, D. McCauley, P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, and C. Webb, “Die stacking (3D) microarchitecture,” Proceedings of the IEEE/ACM International Symposium on Microarchitecture, pp. 469-479, December 2006.

[10] S. J. Kang, C. Kocabas, T. Ozel, M. Shim, N. Pimparkar, M. A. Alam, S. V. Rotkin, and J. A. Rogers, “High-performance electronics using dense, perfectly aligned arrays of single-walled carbon nanotubes,” Nature Nanotechnology, Vol. 2, No. 4, pp. 230-236, April 2007.

[11] N. Patil, A. Lin, E. R. Myers, K. Ryu, A. Badmaev, C. Zhou, H.-S. Philip Wong, and S. Mitra, “Wafer-scale growth and transfer of aligned single-walled carbon nanotubes,” IEEE Transactions on Nanotechnology, Vol. 8, No. 4, pp. 498-504, July 2009.

[12] J. Zhang, N. Patil, A. Lin, H.-S. P. Wong, and S. Mitra, “Carbon nanotube circuits: living with imperfection and variations,” Proceedings of the Conference on Design, Automation and Test in Europe, pp. 1159-1164, March 2010.