A New Type of Inverter with Juctionless (J-Less) Transistors

E. R. Hsieh and Steve S. Chung 1Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Taiwan,

Abstract- A new type of inverter built on a specific channel without source/drain junction is proposed. This inverter can be formed by a connected n- and p-doped channel as the substrate and with complementary p- and n-doped gates respectively. The transistor operation is in accumulation mode, different from the conventional CMOS devices with inversion mode of operation. Extensive simulations have been made to demonstrate this transistor with high current density and good short channel control on 10nm technology and beyond. Good inverter characteristics are also shown. This new inverter device will be ready for the 20nm node and beyond.

Introduction- Recently, junction-less (J-Less) transistor has been expected to be a good candidate in extremely scaled short-channel devices (Lg<20nm) without source and drain junctions [1-5], resulting in good short channel control and free of shallow junction control. In J-Less transistors, the gate controls the channel resistivity. In the off condition, the channel is depleted by gate electrostatic potential, resulting in high resistivity. While adding positive (negative) voltage biases on the gate for n-(p-) channel J-Less transistor, the major carriers in the channel will be accumulated, resulting in low resistivity and the channel is conducted. Since J-Less transistor can also perform n-channel or p-channel function, a new structure of inverter based on the concept of J-Less transistor is proposed. Fig. 1(a) shows the schematic of conventional CMOS structure. The same idea can also be applied to J-Less CMOS devices, Fig. 1(b). Then, in Fig. 1(c), we connect n- and p-channel J-Less transistors with neither interconnect nor isolation. In other words, the n- and p-channel J-Less transistor can be simply connected by using existing technologies, such as silicide in the formation of source/drain contacts. This new structure is even more compact and simple integration than CMOS devices. Extensive simulations have been made to demonstrate the behavior of this device and the inverter properties.

The Inverter Structure A two-dimensional double gate structure is chosen, Fig. 2.

In fact, this device can be implemented by FinFet, Nanowire, or ultran-thin body SOI structures. The gate-oxide thickness, Tox, is 1nm, and the thickness of channel, Tsi, is 5nm. Especially, for n-channel J-Less transistor, the gate electrode needs to be p-type doped; for p-channel one, the gate electrode should be n-type doped [5].

Characteristics of Juctionless(J-Less) Transistors Figs. 3 and 4 show the IDVGS and IDVDS of p-(left) and n-channel(right) J-Less transistor with Lg= 10nm respectively.

Good Ion and acceptable on-off ratio were observed. Fig. 5 shows the simulated roll-off characteristics of Vth,lin and Vth,sat. An appreciable short channel control is observed. Fig. 6 shows the DIBL and Subthreshold Swing (SW) characteristics. Higher DIBL but moderate SW was observed. Fig. 7 shows the Vth tuning ability by changing the gate doping concentration. It was found that a wide window for these devices can be achieved. In order to understand the transport of these devices, the cross-sections of the n-channel transistor are simulated. Fig. 8(a) is the simulated structure of n-channel transistor. In Fig. 8(b), the channel is depleted and transistor is off, with few carriers in the middle of the channel; then, channel turns into the threshold condition, Fig. 8(c). The conduction path is formed in the middle of the channel. Finally, transistor is fully turned-on, the channel is fully conducting and the energy-band achieved the flat-band condition; especially, the major conducting region is shifted to the channel surface from the middle. As a result, we conclude that, for J-Less transistor, the channel conduction is from depletion to accumulation, which is different from the conventional MOSFETs, in that the conduction is from accumulation to inversion, Fig. 8(e).

Characteristics of the Simple Inverter Fig. 9 shows Vin-Vout transfer curve for the inverter with

Lg=30, 20, and 10nm respectively. Good switching characteristic was observed. Fig. 10 shows the output transient behavior with the input pulse and a load capacitance of 10 fF. In order to improve the performance of inverter, an optimized structure is provided (Fig. 11). The terminals of contacts are silicided, and the spacer regions are highly doped. However, the channel region is lightly doped. Fig. 12 shows the IDVGS of the optimized structure in comparison to the control devices. It was found that the off current decreases and the on current increases. Fig. 12 shows Vin-Vout transfer curve for the optimized inverter in comparison to the control inverter. It was found that the characteristics of the optimized inverter exhibits fast switching behaviors. The rolling up and down are faster for the optimized inverter than those for the control. Fig. 13 shows the output transient behavior for the optimized inverter with input pulse and a load capacitance of 10 fF. The fast transient behavior for the optimized inverter was observed.

In summary, a new-type of inverter with J-Less transistors has been proposed. It exhibits features of high on-current, good short channel control, and Vth tuning ability. Various inverter properties have been verified. Finally, optimized conditions of the inverter structure have also been proposed to further improve the performance of inverter. This inverter will be a good candidate for future generation CMOS technologies.

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Fig. 1 (a) the schematic of CMOS inverter; (b) the schematic of modified CMOS devices, composed of n- and p-channel junctionless transistors; (c) a new structure of inverter, composed of n- and p-channel junctionless transistors.

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Fig. 2 The simulated structure. A two-dimensional double gate structure is chosen,Thickness of gate oxide, Tox, is 1nm, and thickness of channel, Tsi, is 5nm. Especially, for n-channel J-Less transistor, the gate elec-trode needs to be p-type; for p-channel J-Less transistor, the gate electrode needs to be n-type.

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Fig. 3 The IDVGS curves of p-channel(left) and n-channel(right) J-Less transistor with gate length of 10nm. Acceptable on-off ratios are obtained.

Fig. 5 The simulated results of VT roll-off, Vth,lin@VDS=0.05V and Vth,sat@VDS=1V. Appreciable short channel control of these devices is observed.

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Fig. 7 The threshold voltage tuning ability by changing the concentration of the gate electrode. It was found that there is a wide window for these devices to tune Vth.

Fig. 6 The simulated results of DIBL and Subthreshold swing(SW). Good SW of these devices is observed. But DIBL is higher.

Fig. 8 (a) The simulated structure of n-channel J-Less transistor. (b) the channel depleted condition; (c) the threshold condition; (d) the flatband; and (e) for J-Less transistor, the channel conduction is from depletion to accumulation. For conventional MOSFETs, the conduction is from accumulation to inversion.

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Fig. 4 The IDVDS curves of p-channel(left) and n-channel(right) J-Less transistor with gate length of 10nm. Good on current an be achieved.

Fig. 9 Vin v.s. Vout characteristics for our inverter with Lg=30, 20, 10nm respectively. Good switching characteristics can be achieved.

Fig. 10 The output transient characteristics with the input pulse and a load capacitance of 10 fF.

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Fig. 12 The IDVGS of the optimized structure in comparison to the control in Fig. 1(c). It was found that the off currentdecreases and the on current increases.

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Fig. 13 The output transient character-istics of new structure with the input pulse, with a load capacitance 10 fF. Better switching transient is obtained in comparison to the control ones, Fig. 1(c).

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References[1] C. W. Lee et al., Appl. Phys. Lett, 94, 053511, 2009.[2] Y Cui et al. Nano Lett. 3, p. 149, 2003.[3] Y. Shan et al., Appl. Phys. Lett., 91, 093518, 2007.[4] J. Xiang et al., Nature, 441, p. 489, 2006.[5] J-P Colinge et al., Nature Nanotech., Feb, 21, 2010.

Acknowledgments This work was sponsored by NSC, Taiwan, under project No. NSC96-2628-E009-168-MY3.