RADPro: Automatic RF Analyzer and Diagnostic Program Generation Tool

Sukeshwar Kannanl, Bruce Kiml, Ganesh Srinivasan2, Friedrich Taenzlar2, Richard Antlel,

Craig Force2, Falah Mohammed3

University of Alabama, Tuscaloosa, AL, USA I Texas Instruments Inc., Dallas, TX, USA2

AN-Najah National Universitl Bruce.kim@ieee.org

Abstract

This paper provides development of an RF circuit software tool that generates diagnostic programs automatically for device interface boards. The diagnostic tool utilizes novel techniques to differentiate faulty RF circuits embedded in printed circuit boards. The diagnostic tool provides user­transparent pseudocodes with high fault coverage and significantly decreases time to market.

1. Introduction

A typical RF Device Interface Board (OIB) used in testing RFICs consists of mixed-signal and RF circuits with hundreds of active and passive components. In addition, the majority of RF circuits are embedded in those layers of the circuit board that could be defective. As an example, RF filters are composed of microstrips embedded in the layers of the printed circuit board with copper metal traces. These embedded structures that make up the RF circuits are extremely difficult to validate its functionality. Our research work presented in this paper was inspired by the difficulty inherent in these embedded RF circuits along with the assembled parts on the board. We have previously published automatic program generation tools for analog and mixed-signal load boards [1, 2, 3, 4]. These beta­version diagnostic tools have been successfully developed into pre-production diagnostic tools and have been extremely successful in reducing time to market for new products. However, a proliferation of RFIC chips in the wireless market has triggered a surge of new RFIC chips requiring new load boards that must be validated for correct assembly and functionality. Typically, these load boards contain multi-sites with hundreds of passives and embedded RF circuits. Although the importance of testing these device interface boards in a timely and accurate manner is well understood, test engineers currently do not have the proper set of tools to achieve the goal of testing the RF boards in hours rather than days. In the absence of these tools, the engineer inserts new silicon into a new device interface board that is not certain to be fault-free. Hence there is an urgent need for automatic hardware diagnostic capability to ensure the functionality of the test hardware.

Device Interface Boards are designed as a means to provide test signals to the device under test (OUT). They also provide a means of stimulating the operating conditions for the device under test to evaluate its performance. The complexity of the boards is also determined by trace interconnecting these components on board. The overall complexity of OIBs primarily depends on the complexity of the OUT, the tester hardware platform and the test functions required [4]. The currently existing techniques on the market for testing D18s are very expensive, time-consuming and limited in their capability by the tester instrumentation. The paper is organized as follows. Section 2 provides an overview of the diagnostic software tool RADPro. Section 3 provides details on two novel test techniques used to test embedded RF circuits. Section 4 highlights fault modeling and developing a look­up table to perform diagnosis for Device Interface Boards and finally, section 5 shows the test coverage of the software tool and its limitations for ETS testers.

2. Approach

A typical troubleshooting technique for a device interface board involves manually writing tester-specific codes to test circuits on a 018. This process takes days and even months for multi-site 018s. Our approach is to automate this troubleshooting process, hence reducing test cost and becoming competitive in terms of time to market as shown in Fig. 1.

RF or Mixed Signal DIB

Automatic Test Equipment

Fig, 1: Block diagram of an automatic RF device interface board setup.

Paper 11.2 INTERNA TlONAL TEST CONFERENCE

978-1-4244-7207 -9/1 0/$26.00 ©20 1 0 IEEE

In order to do this properly, test generation and execution had to be automated to avoid labor-intensive and time­consuming manual programming. We have developed a software tool called RADPro (RF and Diagnostic Program) for the complete automation of DIB testing. 2.1 RF Analyzer and Diagnostic Program

Generator (RADPro)

This diagnostic software tool was originally developed for debugging ATE mixed-signal load boards [2]. The original design was intended for simple load boards, which had few relays and active components with a limited number of resources on the ATE. An RF DIB is comprised of mixed­signal and RF circuits with several component types including capacitors, resistors, embedded passive RF components, ICs and connectors. The complexity of boards is also determined by trace interconnecting these components on board. Hence there is a need to analyze these mixed-signal and RF components, perform diagnosis on the device interface board and locate the type of fault.

The main RADPro software architecture uses the schematic information of the DIB such as the netlist, bill of materials and pinmap files to replicate the schematic of the board along with all the components and necessary connections. A model library is built for all the active and passive components of the board to increase the test coverage of the respective board. The tool runs a simulation for the testable circuits in the DIB and stores the results in a lookup table. The output of the program is a pseudocode that consists of test instructions to be carried out on the ATE. After the pseudocode is converted into the native language of the tester using the VLCT bridge or test translation software as shown in Fig. I, the tests are run on the ATE and the output is sent back to the tool, which matches the values with the lookup table and outputs a pass or fail result for each individual component in the testable circuit.

Netlist, Bill of

I Pin Map File Library of

I Components

I Materials and Resource Passive RF Model Library (BOM), Package Constraints Components

File,

I 1 ETS

Channel PARSER '-----0 Type

Generation 1 Module -

1 Build Fault

Divide Relay Test ADS and

Circuit -Inducer

- Board Path Generation -t SPICE

Module Module Module Module Simulation

-

1 I Output Pseudocode I Fig. 2: RAOPro software architecture.

The software architecture of RAOPro consists of six different modules to automate the process of testing. Fig. 2 shows the architecture of RAOPro and how the testing process is done for each DIB board.

2.1.1 Parser

A parser has been implemented to construct the top-level circuit from the netlist and pinmap input files. Bill of materials (BOM), SPICE and ADS model files are read to obtain component information. Building the board circuit also involves prior knowledge of available terminations for the board under test. This information is carried forward to the generation of testable subcircuits. The parser also verifies whether the input files are in the required format [5,6,7]. Once the input files are processed, the tool proceeds to build the circuits as present in the OIB board. The termination information of the board is obtained from the pinmap files for the board, which are tester specific and also vary from board to board. The tool also checks for all the model files stored in the model library for active components.

2.1.2 Build Circuit Module

In the build circuit module, the DIB components are segregated and stored as active and passive libraries. The active components are tested based on the availability of a model file, which has to be user-created to increase the test coverage of the board. The passive component library is used to create a serially changing fault inducer module. In the module we automatically induce faults in the passive components of the board to obtain possible fault simulation values. These results are stored in the lookup table and matched with the actual results measured with ATE hardware.

2.1.3 Divide Board Module Using the partition algorithm, we divide the board into small testable circuits. The output of the build circuit module is taken to divide the board into testable subcircuits based on the availability of terminals for stimulating and measuring test signals. Fig. 3 shows a typical RF DIB circuit.

OUT Terminal

C

(133 I

10UF .,.GND

O.47uH llOZ

Pogo Pins

�------------�==> A

(26

Io.oluF .,. GND

o ohms \r---.,.---LY B

(15 I100PF

.,. GND

Fig. 3: Device interface board circuit.

Paper 11.2 INTERNA TlONAL TEST CONFERENCE 2

Let us consider the circuit shown in Fig. 3. We can use the following partition algorithm to divide the board into small testable circuits: 1. Choose a node X that is connected to a pogo pin of the

tester using the information from the pinmap files as shown in Fig. 3. Mark this node as visited.

2. Find all the components linked to the start node and group them as a single block. As an example, nodes A and B are connected to start node X.

3. Repeat step 2 for all the nodes in the previously grouped block until another termination node is encountered. Mark this node as a visited node.

4. Mark the path between the start node and the node with termination as a testable subcircuit.

5. For Fig. 3, paths A-X-C and B-X-C are the partitioned subcircuits.

6. Repeat steps 3 and 4 until all the nodes are marked as visited.

Once the circuits are divided into testable subcircuits, the circuits that contain relays are tested separately for the different operational modes of the relay.

2.1.4 Relay Path Module

This module validates functionality of relays with testable circuits. The circuits with relays are tested by switching the relay on or off to check for faults in the relay circuits. We have used stuck-at-O and stuck-at-1 fault models.

2.1.5 Channel Type Generation Module

This is a special module to accommodate floating ground used in high voltage testing performed in some tester platforms such as Eagle Test Systems (ETS). In ETS the source meters and the measuring instruments do not share common ground, and this is used as a pedestal to apply and measure higher voltages. In such cases the tool must specifically use the high or low channels available at the respective pogo pins. This information is taken from the pinmap files, and the channel type is created for each pogo pin to say whether it is high or low and whether force or sense activity is taking place at the pin. Fig. 4 shows a typical DlB circuit with floating ground used in ETS.

Pogo pins DUT Pin 1 Force High 8 0

::: Sense High I � � K_SP2BT_Sl

-:-OUT Pin 2

Force Low 8 0

::: Sense Low I � 1 K_SP2PH_Sl -:-

Fig. 4: DlB circuit with floating ground used in ETS.

2.1.6 Test Generation

This module prepares the ADS and SPICE netlists for each testable circuit. The ADS simulation is performed as a batch simulation. The ADS netIist consists of AEL commands, which are generated for each testable circuit as shown in Fig. 5.

Batch Simulation File Generation

ADS Simulation Module

Fig. 5: Process of generating the ADS netlist.

Simulation involves fault modeling and test technique. We have developed two different test techniques to perform fault analysis on RF device interface boards. The results of the simulation are stored in the lookup table and matched with the output of the ATE to find out whether a component has passed or failed the test.

2.1.7 ADS/SPICE Simulation Module

The output of the divide board module gives a set of testable and non-testable circuits using the partItIOn algorithm. To analyze the RF components in the testable circuits, we have performed fault modeling of the commonly present RF components and surface mount passive components. The simulations are run for a fault­free circuit and also by automatically inducing faults using the serially changing fault inducer module.

After automatically inducing the faults for all testable circuits, we will segregate the RF circuits from the mixed­signal circuits. SPICE simulation is run for mixed-signal components. The tests run on mixed-signal circuits are Force Voltage Measure Current (FVMC), Force Current Measure Voltage (FCMV) and Force Current Measure Voltage with Delay Time (FCMVDT). ADS simulation is run for testable circuits with embedded passive RF components. We run S-parameter simulations for RF components to generate the Force Power Measure Voltage (FPMV) test. There are two different types of test technique we have developed for detecting faults in RF components - RF power sensor testing and dither testing. Using the fault models and the test setup developed, we are

Paper 11.2 INTERNA TIONAL TEST CONFERENCE 3

able to detect faults in mixed-signal and embedded passive RF components.

3. Novel RF Circuit Testing Techniques

We developed two novel test techniques for RF circuits that are embedded in Device Interface Boards. This section provides details of these two test techniques that are used by the software tool (RADPro) to test RF device interface board circuits.

3.1 RF Power Sensor Testing

This technique was developed to identify process-related defects for embedded RF circuits. There are microstrip lines that connect to the discrete devices on the DIB. Due to the process-related defects that may occur during PCB manufacturing, power degradation may occur within the RF circuits. Therefore power loss was measured across the passive RF microstrip line using a power detector chip as shown in Fig. 6. The RF microstrip lines were modeled and stored in the model library. Then a simulation was performed on these microstrip lines to find the respective power levels for each of them. Fig. 7 shows the different faults on the RF microstrip line over a wide range of frequency. As seen in the figure, significant differences can be observed between fault-free, near open and near short defects. It is interesting to note that near open defects have higher voltage differences when compared to fault free. This may be due to narrowing in a microstrip line, which provides greater resistance. Near short defects were modeled as a capacitor between the two microstrip lines.

We used the LMV225 power sensor chips to convert the power measurements in terms of voltage. Fig. 8 shows the implemented RF power sensor attached to the DIB board at the OUT pins to detect defects. Furthermore, simulations were performed for different faults on the RF interconnect, and their behavior when subjected to RF power was studied.

ITIIl r- RF Trace

DUT s MA COmponent Socket

Power Detector Chip

Load Board

Fig. 6: RF power chip used for power loss measurements in the device interface board.

t.4,------------------------�

> ai C1 :l (5 >

o

Fault Free Near Short Defect

-t-----� -c __ -�------I Near Open Defect

2 4 6 8

Iieq,Giz Fig. 7: Simulation results of a subcircuit connected to a

power detector.

Fig. 8 shows hardware validation with two power sensors (PSI and PS2) at the DUT pin. We measured at different test frequencies of 1.5 GHz, 2 GHz and 2.5 GHz. Table 1 provides the results obtained for different faults induced in the RF Device Interface Board. We injected seven different faults as shown in Table 1. As can be seen from the table, the power sensor does not find all faults. Fig. 9 identifies faults that have higher contributions using power sensors.

Fig. 8: RF Power sensor implemented on a DIB.

Table 1: RF power sensor analysis for different faults.

1.50Hz 2.00Hz 2.50Hz

Type of Fault PSI PS2 PSI PS2 PSI PS2

Fault Free 1.41 0.937 1.24 1.146 1.05 1.04

Open common 1.478 0.937 1.24 1.105 1.047 1.042

point

Open one side 0.598 1.143 0.71 1.2 0.405 0.95 of Balun

Open LC filter 1.41 0.924 1.238 1.15 1.048 1.042

one side

Shorted 1.037 0.984 0.808 0.73 0.183 0.2 outputs

Open 0.186 0.204 0.183 0.2 0.183 0.199 Capacitor

Shorted Balun 1.436 0.841 1.227 1.5 0.999 1.051

Shorted Balun 1.178 1.155 0.741 0.652 0.306 0.413

and shorted outputs

Paper 11.2 INTERNATIONAL TEST CONFERENCE 4

1 0.9 0.8

> 0.7 tV aD 0.6 '" ... (5 O.S >

� 0.4 c: ., 0.3 Qj � 0.2 C

0.1 0

-0.1

Power Sensor Results

PSl

______________ ���"LPS2

open one side shorted shorted Balun shorted balun of balun ouputs and shorted

outputs

Fig. 9: Power sensor outputs for fault-free vs. induced fault circuits.

RAOPro provides an S-parameter simulation based on the power sensors. The output response of the power sensor is converted in terms of voltage using the transfer function equation of the LMV225 power sensor. The test performed is a force power measure voltage. The following pseudocode is obtained from RAOPro on testing for a RF subcircuit using the power sensor technique as shown in Fig.l O.

"*"S-PARAMETER TEST FOR RF SUB-CiRCUiT .. ••• CONDITION(VERIFY COMPO 'ENT = RFRI) FP IV(forced power = -15dBm, force pin = J2_DI, sense pin = RFANTB_DI, type = embedded passive)

COMPAREJIMITS(loll'er !imit = I.II( IIpper !imit = f..I5 V. nomina/willie = 1.32 V. tested pwr node = RFANTB_OVT_DI)

*****S-PARAMETER TEST FOR RF SUB-CIRCUIT*H**

CONDITION(VERIFY COMPONENT = RFBI) FPMV(forced power = -30dBm, force pin = J3_DI, sense pin = LOP _DI, type = embedded passive)

COMPARE LlMITS(/oll'er limit = 2.1 I( IIpper limit = 2.5./ V. nomina/,'a/lle = 2.32 V.tested pl\�·node = WJNPU7,--Dlj

Fig. 10: Pseudocode for an RF testable sub circuit.

3.2 Dither Testing

In the RF power sensor testing we checked the power loss at the OUT terminal for each testable circuit, as a defective circuit would contribute to lower power reaching the OUT terminal compared to a fault-free DIB circuit. However, some defects are difficult to recognize using this technique. The problem of aliasing also arises when two or more faults are difficult to distinguish.

Hence we developed a better technique called dither testing where we use a multitone signal and modulate it with the RF test signal. The frequencies of the multitone and RF source signal are maintained at the same level, and Gaussian noise is added to the muItitone signal [8]. The test signal prepared as shown in Fig, 11 is given as input to the circuit under test (CUT).

RF Carrier Signal

Modulation

Multitane Signal with

Noise (AWG)

RF Circuit

Fig. 11: Test setup for dither testing.

The prepared test signal is given to the circuit under test

(CUT), and the output power spectrum is monitored. The

test signal has a multitone signal with randomly changing

phases. Hence when there is a defect in the DIB circuit

such as opens, shorts in embedded passive components and

missing or misplaced discrete passive components, there is

a phase change in the output response that is identified

when we measure the RMS and peak values at the output

of the DIB circuit using a peak and envelop detector. The

input test signal, as shown in Fig. 12, depicts the signal in

both frequency and time domain.

Spectrum Multllone Signals WIth nOise

u�JJ (A) 05 1 15 2

Freq GHz Spectrum carner

. i . 1 (B)

05 1 15 2 Freq GHz

inl�1'1'"1-11j (C)

a 05 1 15 2 Freq GHz

Fig. 12: Input test signal for dither testing: (A) Multitone signal, (B) RF carrier signal, (C) multitone signal modulated with the RF carrier signal.

Paper 11.2 INTERNA TlONAL TEST CONFERENCE 5

Simulation was performed and the output power spectrum was monitored for a fault-free circuit vs. induced open and short faults. The simulated output power spectrum using the dither testing technique is shown in Fig. 13.

Power Spectrum using Dither Testing

Frequency, GHz o 0 .2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

o .... ..... � --.....

-50

'... _Fa u lt Free -100 � S h o rtDefect -

E __ Open Defect !:l -150 �' j -200

-250

-300

-350

• ....... ------- � -

Fig. 13: Power spectrum of dither testing.

The multitone signal prepared is mathematically represented by the following equation - Eq.(1) [9].

N -1 . A (t) = " } nl.J. Olt m L,.. mn-e n=O

Eq ( I)

The complex multitone signal mit) with N tones and an angular frequency of Llw = 27r1T. mit) is periodic with period T.

The real valued multitone signal is derived from Eq. (2).

N-I met) = L 1m n l cos( (Olo + n�Ol)t + arg{m n}) Eq (2)

n=O

The complex multitone signal can be regarded as the complex envelop of the real-valued signal m(t) with respect to (00 because it follows

m(t) =I�t�.costtv+ar g(n(t)) }) Eq (3)

The crest factor of the complex multitone signal m(t) is denoted by Eq. (4).

These equations were used to calculate the crest factor in MA TLAB and ADS simulations.

In the experimental setup using the peak and envelop detector, we measured the voltage outputs for a testable circuit. These output results were used to obtain the crest factor of the testable circuit. We noticed significant change in the crest factor values between fault-free and fault induced circuits.

Verification of the test technique was also performed on process defects in a 20-cm-Iong resistive trace and compared to outputs of the RF sensor technique for a long through line vs. input shorted and output shorted as shown in Fig. 14. Dither testing was comparatively more sensitive in identifying process defects in the embedded RF passive components. The results are as shown in Fig. 14.

r:c .., g v '" ... .. '" Qj oJ

9 8 7 6 5 4 3 2 1 0

long through line input short output short

Fig. 14: Dither testing result for embedded passive RF components.

4. Fault Modeling

Once the testing process was completed using either of the two test techniques for a testable circuit, we performed diagnosis of the DIB. We have developed fault models that can be induced to create opens and shorts in embedded passive RF components present on the DIB.

We have built a model library including the different SPICE and ADS models to perform simulations for the testable circuits. The different fault models are stored inside this model library, which helps us to build the simulation setup for each testable circuit. The open connection in traces for analog-mixed signal boards is modeled with a high resistance, and shorts are modeled with a capacitance to ground. The stuck-at-relay faults are also modeled with a capacitance to ground if the relay is stuck at 0 and a resistance if stuck at 1.

RF Trace is modeled as a transmission line and the power loss across the transmission line is calculated and checked with values obtained from the RMS detector in the physical setup [10, I I]. RF traces are modeled using the line calculator in Advanced Design System (ADS), and the fault conditions are induced into the model synthesized by the line calculator.

Paper 11.2 INTERNATIONAL TEST CONFERENCE 6

RF trace acting like a band pass filter is modeled as a passive band pass filter. A lookup table with measurements of bandwidth, amplitude, center frequency etc. for each possible fault occurrence is created by simulating the response for different missing components; this is compared with actual response values to match the type of fault occurring.

A balun transformer is commonly used in RF DIBs to connect two microstrip lines with different impedances to balance signals. They convert a balanced signal to an unbalanced signal. We will consider a balun transformer formed by an RF trace with open and short faults occurring on the trace at different positions on its surface and then prepare a lookup table. Consider the following DIB circuit in an RF load board with embedded passive components such as a balun transformer and SMT resistors and capacitors. We performed an ADS simulation and created a lookup table. Fig. 15 shows the actual RF DIB circuit with process-related defects induced at certain positions respectively. The dark lines indicate metal traces inside the layers of PCB to form an impedance-matched RF circuit. We perform a frequency sweep and use the data obtained at 50Hz as this shows the maximum difference in measurements. A lookup table is shown in Table 2 with different possible fault measurements, but we see some effect of aliasing, which shows that we will be able to find the faulty component, but localizing the fault in embedded passive components in these conditions is difficult.

Open Position 1 -. Balun ---Transformer

Open Position 2 -+

Short Position 2 ( .......

RIll SO Ohm TlKe

Oohml

-!iNo

SHEET I ION.oI

IIp!

\" , IIfANTB.oUT.o1 ( IIfAHT8.o1 1I �G I, �"11111-"'''''''' 11.01

I SOOhm lOOp! SOOhmTllCt .. ..;..,Oohmrvl .. __ .... -l TlKe RIll SOOlimTIlCt 10P.ol

RI SHEET I 31

GNO

GNO _ GNO -

Fig. 15: Testable RF subcircuit with open and short process-related defects at position 1 and 2 in the balun transformer (Dark lines indicate embedded RF lines.).

Table 2' Lookup Table to identity defects

Name Power Gain (dB)

Fault Free -40

Open at Position I -45

Open at Position 2 -52

Short at Position I -54

Short at Position 2 -56

Depending on the value of the power measured, we match the fault to their respective faults, and in cases where two or more faults share the same values at a given respective frequency for measurement as shown in Table 2, we call it aliasing and have to perform other measurements to differentiate between the faults.

5. Test Coverage and Limitations

The tester platform was one of the limitations the tool faced. The channel type generation module was incorporated into the tool to overcome this limitation. In the Eagle Test System (ETS), testers differential testing is performed. To facilitate a differential testing capability, the tester systems have a floating ground concept in which the signal sources are not connected to the tester ground but to a virtual ground so they can be used as a pedestal for performing high voltage testing.

The pinmap file of the device interface board carries the information on the pogo pin, which provides access to perform testing and also the specifications of the hardware resources on the tester side. Using this information from the pinmap file, we assign high and low sides of a testable differential path. Now for ETS boards the partition algorithm used is different from other device interface boards. The circuits are portioned into differentially testable circuits by grouping the high and low sides into one testable circuit. We ran tests on these device interface boards and the pseudocode was obtained as shown in Fig. 19.

*****POWER TO GROUND ONLYTEST***** CONDITlON(VERIFY COMPONENT = JP19-1_2)

FCMV(forced current = le-4 A, force high pin = CH-JI-I16,

sense high pin = CH-JI-H9, type = force high)

FCMV(forced current = le-4 A, force low pin = LowPin_Num3, sense low pin = LowPin_Ref3, type = force low) COMPARE_LlMITS(lower limit = 0.06 V, upper limit = 1.99 V, nominal vallie = 0.075 r� tested plllr node = + 3P3VjvJB)

Fig. 19: Pseudocode for differential testing.

Paper 11.2 INTERNATIONAL TEST CONFERENCE 7

We used two different DIB boards used on the Eagle Test Systems with RADPro. The results of the two different DlBs run on RADPro were highly successful, which indicated that all the components were tested. Furthermore, the fault coverage percentage with respect to each component type tested, along with the total board components, was reported by RADPro.

Table 3: Test coverage statistics obtained for DIB using RADPro.

Components Total # of Total # of % of tested % of

Component Testable component Fault

s in BOM Component s Coverag s e

Capacitors 193 174 90.15 84

Resistors 67 54 80.5 78

Relays for 23 19 82.6 79

functionality

SMA 31 31 100 100 Connectors

Diodes 56 45 80.35 76.5

Jumper 27 23 85.18 83 Wires

The test coverage percentage depends on the accessibility provided by the board [12, 13]. Tests are run only for circuits that originate at a pogo pin and terminate at a DUT pin as these two pins are used to provide input stimulus and measure the output response [14]. In addition, the total number of active components depends on the availability of their model in the model library, which the users have to keep updating to increase the board coverage. Table 4 provides the test coverage on ETS DIB boards with differential testing capability.

Table 4: Summary of test coverage.

% Coverage DIB 1(6486024C) DIB 2(WG2K ETS 364)

Total number 1174 1058 of components

Capacitors 67 81

Resistors 52 74

Inductors 29 23

Relays 47 58

Overall 71.32 84.48

Coverage

The above results indicate that the test coverage varies over a range of about 70% to 85%. This is due to accessibility that can be obtained on the DIB.

6. Conclusion This paper presented a novel test methodology for verification of RF device interface boards used for IC testing. Embedded RF circuits in DIB boards are extremely difficult to test in an automated test environment. This is due to non-classification of embedded RF circuits in the parts list and netlist of DIB.

There are two test techniques discussed in the paper for testing embedded passive RF components. Development efforts are in progress to obtain the pseudocode for an RF DIB using dither testing.

Acknowledgement

The authors would like to acknowledge Semiconductor Research Corporation and Texas Instruments for support and technical assistance.

References

[1] K. Pinjala, B. Kim, P. Variyam, "Automatic Diagnostic Program Generation for Mixed Signal Load Board," IEEE International Test Conference, pp. 403-409, 2003.

[2] V. Kalyanaraman, B. Kim, P. Variyam, S. Cherubal, "DIBPro: Automatic Diagnostic Program Generation Tool," IEEE International Test Conference, 2006.

[3] S. Sundar, B. Kim, "Circuit Analyzer and Test Generator (CATGEN) for Mixed-Signal Device Interface Boards," IEEE VLSI Test Symposium, San Diego, April 2008.

[4] S. Sundar, B. Kim, S. Wokhlu, E. Beskar, R. Rousselin, T. Byrd, F. Toledo, D. Cotton, G. Kendall, "Low Cost Automatic Mixed-Signal Board Test Using IEEE 1149.4," IEEE International Test Conference, Santa Clara, CA, October 2007.

[5] "Quantization and dither: A theoretical survey," Journal of Audio Engineering Society, vol. 40, no.5, pp. 355-375, May 1992.

[6] P. Carbone, C. Narduzzi and D. Pedri, "Dither signal effects on the resolution of nonlinear quantizers," IEEE Transactions on Instrumentation and Measurement, vol. 43, no. 2, pp. 139-145, April 1994.

[7] P.Carbone and D. Petri, "Effect of additive dither on the resolution of ideal quantizers," IEEE Transactions on Instrumentation and Measurement, vol. 43, no. 3, pp. 389-396, June 1994.

[8] G. Srinivasan, S. Cherubal, P. Variyam, M. Teklu, C.P.Wang, D. Guidry, A. Chatterjee, " Accurate Measurement of Multi-Tone Power Ratio (MTPR) of ADSL Devices using Low Cost Testers", IEEE European Test Symposium, Estonia, May 2005.

[9] M. Friese, "Multitone Signal with Low Crest Factor", IEEE Transactions on Communications, Vol. 45, No. 10, October 1997.

[10] S. Kannan, B. Kim, "Low Cost Test Technique for RF Interconnects in MCM Substrate", IMAPS Advanced Technology Workshop on RF and Microwave Packaging, San Diego, 2009.

Paper 11.2 INTERNATIONAL TEST CONFERENCE 8

[11] S. Kannan, B. Kim, G. Srinivasan, F. Taenzlar, R. Antley, C. Vogel and C. Force, "Development of Automatic Program Generation Tool for Analog-Mixed Signal and RF Load Boards", IEEE International Workshop on Reliability Aware System Design and Test, India January, 2010.

[12] R. Schuttert, D.C.L. van Geest; "On-chip mixed­signal test structures re-used for board test,"IEEE International Test Conference, pp. 375-383, 2004.

[13] R.E. Tulloss, C.W. Yau, "BIST and boundary-scan for board level test: test program pseudo-code," First IEEE European Test Conference, 1989.

[14] O. C. Woodard, "High density interconnects verification of unpopulated multichip modules," in Proceedings of I I th IEEEICHMT International Electronic Manufacturing Technology (IEMT) Symposium, pp. 434-439, 1991.

Paper 11.2 INTERNATIONAL TEST CONFERENCE 9