Automated Design and Optimization of Circuits in EmergingTechnologies

Rajesh A. Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini,V. Ramgopal Rao, Mahesh B. Patil

Department of Electrical Engineering, Indian Institute of Technology BombayMumbai, India, 400076. Tel: +91 22 2576 7401, e-mail: rajesht@ee.iitb.ac.in

Abstract— A novel table-based environment for

automatic design and optimization of FinFET circuits

is demonstrated. A new accurate look-up table (LUT)

technique is implemented in a circuit simulator and in-

tegrated with particle swarm optimization algorithm

for efficient circuit designs in novel devices. Op-amp

circuits are designed and optimized to demonstrate

the accuracy and usefulness of the proposed platform.

Further, it is shown that the proposed design method-

ology can take into account variations in process, sup-

ply voltage, and temperature.

I. Introduction

The continuous downward scaling to improve the per-formance of CMOS technology is hindered below 45 nmdue to various short-channel effects (SCE) and leakagecurrent problems. This has led to increased interest in de-velopment of novel device structures to reduce SCEs andto enhance performance. FinFET device, which is oneof the multiple gate structure devices, is emerging as astrong candidate to replace planar bulk MOSFETs due toits better gate control and reduced SCEs [1]. However,compact models for these novel devices take substantialtime for development. For FinFETs, analytical modelsare under investigation [2] and not fully developed to beused for circuit simulation. This makes it difficult for de-tailed circuit performance evaluation. In this scenario, thelook-up table (LUT) approach to represent the device isan attractive alternative for emerging technologies. TheLUT approach does not require physical understanding ofthe device and can be used effectively for circuit designsin advanced technologies.

Various LUT-based techniques have been demonstratedin the past [3], [4]. In general, they are not suitable formanual designs because it is not a mathematical descrip-tion. An LUT approach therefore needs to be combinedwith an optimization technique to enable automatic cir-cuit design. In this work, the integration of the LUT ap-proach with optimization algorithm is proposed for thefirst time for design and optimization of FinFET-basedcircuits. The particle swarm optimization (PSO) [5] algo-rithm is used as an optimization algorithm.

An accurate representation of the moderate inversion

region has become crucial in the present low-voltage andlow-power designs; where many transistors operate closeto the threshold voltage. Many of the LUT approaches re-ported in the literature do not handle this region satisfac-torily. We have used a new template-based LUT techniqueto accurately represent all three regimes (i.e subthreshold,moderate inversion, and strong inversion) of device oper-ation. New LUT technique is implemented in the simula-tion package, SEQUEL [6], and used to design and opti-mize FinFET-based circuits in combination with the PSOalgorithm. Variations such as process, supply, and tem-perature (PVT) are taken into account during the design.Simulation results obtained with the LUT approach arevalidated with mixed-mode (device-circuit) TCAD simu-lator.

The paper is organized as follows. The new template-based LUT approach is described in Sec. II. The PSOalgorithm and proposed design environment for FinFETcircuits design is explained in Sec. III. Simulation resultsfor FinFET circuits are presented in Sec. IV. Finally,conclusions are drawn in Sec. V.

II. New LUT Approach

The look–up table (LUT) approach basically consistsof tables of I − V , Q − V , and interpolation coefficientsfor the transistor. This table is used to compute currentsduring circuit simulation as follows.

IX(VG, VD, VS , t) = IDCX (VG, VD, VS , t) +

dQX

dt,

dQX

dt=

∂QX

∂VG

∂VG

∂t+

∂QX

∂VD

∂VD

∂t+

∂QX

∂VS

∂VS

∂t, (1)

where X = G, D, S. This equation is valid if the quasi–static approximation holds [7], which is generally true forshort–channel devices. Terminal charges (Q) can be cal-culated from C−V data. The I−V and C−V character-istics can be obtained either from measurements or devicesimulations.The LUT scheme should accurately interpo-late currents and charges at the specified voltages VG0 andVD0 (with respect to the source), which may not be a tablepoint. For accurate interpolation in all three regimes (i.e.subthreshold, moderate inversion, and strong–inversion),the following strategy is employed.

978-1-4244-2749-9/09/$25.00 ©2009 IEEE

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We use an ID − VG at V maxD as a template and repre-

sent all ID − VG characteristics in terms of this template.Although the drain current ID varies by orders of mag-nitude with respect to VG, the normalized ID(VG, VD)(i.e., ID(VG, VD)/ID(VG, V max

D ) where ID(VG, V maxD ) is

the template) is found to vary smoothly between 0 and 1,and can be accurately fitted with cubic splines. Therefore,we store one ID − VG at V max

D as a template and ID − VG

at other VD values in normalized format. Each segmentof the table is fitted with cubic splines and coefficientsare calculated with continuity of currents and its first twoderivatives taken into account. Langrage approximationsare used in the VD direction to calculate the coefficientsif VD0 is not a table point. Thus, in the proposed LUTapproach, I − V table consists of a template, normalizedID − VG characteristics, and pre-computed coefficients.

Interpolation of the terminal charges is much simplerthan that of ID since the charges do not vary by orders ofmagnitude with VG and VD. It is therefore possible to usethe charge values directly rather than normalizing them.

From the point of computational efficiency, it is best topre-compute the interpolation coefficients and store themfor ID as well as for the terminal charges. This would savesubstantial amount of run time in circuit simulation. Theadditional storage requirement is found to be smaller forthe LUT approach implemented in this work compared tosome other LUT approaches [8].

III. PSO Algorithm and Design Flow

In the context of emerging technologies, it is highly de-sirable to be able to design circuits in a short time andexplore the potential of the technology. However, lack ofdevice models for a new technology often makes circuitdesign a difficult task. To address this issue, the LUT ap-proach can be used instead of compact models. In orderto use the LUT approach effectively in the design pro-cess, it needs to be integrated with a suitable automaticdesign technique. This would also allow the designer toaccount for complexities such as process, supply, and tem-perature variations, and low-power architectures. Variousoptimization methods have been reported for automaticdesign of circuits. The commonly used gradient-basedoptimization methods [9] suffer with following problems;computation of derivatives of the objective function and agood initial guess to ensure that the algorithm does indeedconverge to the globally optimum solution.

Evolutionary algorithms, which can be used to solvemultimodal optimization problems, do not suffer from dif-ficulties associated with the gradient-based methods. Inmost cases, the particle swarm optimization (PSO) algo-rithm [5] has been shown to perform better than other sta-tistical techniques such as genetic algorithm and simulatedannealing [10], [11]. The PSO algorithm has been also re-ported for circuit design applications [10], [11]. We haveintegrated the PSO algorithm with the LUT approach toenable efficient design of FinFET circuits.

B

C

A

xi

x1

x2 xg

vi

xi

Fig. 1. Two-dimensional representation of the various componentsinvolved in velocity update of particles.

A. PSO Algorithm

In PSO, a cooperative approach is used among ran-domly generated “particles” to find the globally optimumsolution [5]. For a problem with n variables (x1, x2, ...,xn), a population of N particles is initially generated byrandomly assigning positions and velocities to each par-ticle for each variable. In circuit design, these variablescorrespond to the design variables to be obtained such asW/L ratios, resistance and capacitance values. If we de-note the position and velocity of the ith particle by xi andvi, respectively, then

xi ≡ (x1i , x

2i , ....., x

ni ), and vi ≡ (v1

i , v2i , ....., vn

i ). (2)

Each particle in the population is a candidate for thesolution, and the particles are moved towards the fittestparticle. In this process, the algorithm finds a better solu-tion, and it is expected to reach the desired solution overtime. Each particle keeps in memory the best position(denoted by xi) it has attained during its trajectory. Thevelocity of a particle is updated on the basis of three vec-tors (see Fig. 1): (i) its own velocity (vector A), (ii) thedisplacement of the particle from its past best position(i.e., xi − xi, vector B), (iii) the displacement of the par-ticle from the globally best particle (i.e., xg − xi, vectorC). The particle moves in a direction which is a weightedaddition of these three vectors. The velocity and posi-tion update of a particle at time t + Δt is mathematicallyrepresented as follows.

vi(t + Δt) = w (t) vi(t) + p1r1(xi − xi) + p2r2(xg − xi),

xi(t + Δt) = xi(t) + vi(t + Δt)Δt, Δt = 1. (3)

Here, i is the particle index and t is time. In actual im-plementation, t is generally taken to be the same as theiteration number, and therefore Δt is numerically equalto 1. The multiplicative constants w, p1, and p2 are pa-rameters of the PSO algorithm, and r1 and r2 are randomnumbers uniformly distributed in the range [0, 1]. w iscalled “inertia” of the particle, and p1 and p2 are the ac-celeration coefficients.

The inertia parameter (w), which is used to update thevelocity of particles, can be either kept constant or variedwith iteration number. The most commonly used linearapproach to update inertia is implemented in this workand is given below,

w(t) = (wi − wf )(tmax − t)/tmax + wf , (4)

505

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vari

able

sD

esig

n

Desired

specifications

Circuit

PSO−based automatic

sizing and optimizer

Algorithmic

parametersschematic

satisfied?

criteria

Termination No

Yes

FinFET I−V

FinFET tables

LUT−based simulator

(SEQUEL)

* Computation of

currents and charges

* Derivative computation

* Newton−Raphson

solver

and C−V data

and optimized

circuit

Designed

Sim

ulat

ion

resu

lts

Preprocessing

coefficients for

* Computation of

charges

* Computation of

I and chargesD

Fig. 2. LUT-PSO-based design flow for automatic FinFET circuitdesign.

where wi and wf represent the initial and final values ofw, respectively, t is the current iteration number, and tmax

is the maximum number of iterations.In this work, the PSO parameters are assigned following

values: wi = 0.9, wf = 0.4, p1 = p2 = 1.49 and N = 20.

B. Design flow for the FinFET Circuit Optimizer

In circuit design, values of circuit elements, called designvariables, need to be determined such that the circuit sat-isfies the desired specifications. Fig. 2 shows the steps andvarious modules involved in the design flow for automaticFinFET circuit design. The FinFET tables are gener-ated before the optimization process begins. The circuitsimulator uses these tables and the design variables (pro-vided by the optimizer) to simulate the circuit and returnsthe performance measures. The optimizer compares theperformance measures returned by the simulator with thespecified values using a RMS error criteria and generatesa new set of design variables. This sequence is repeateduntil the specifications are met to an acceptable tolerance.

HFIN

S

D

G

(a) (b)

Tox

Gate

Spac

er

S

Spac

er

DLeff WFIN

L

Fig. 3. (a) 3-D structure and (b) cross-sectional diagram ofFinFET used for simulations.

IV. Design Examples and Results

We have used 45 nm FinFET technology with a mini-mum gate length (L) of 20 nm for circuit designs. I − Vand C−V data are generated using TCAD simulator [12].The TCAD simulator parameters (such as mobility anddoping densities) are first calibrated to fit experimentaldata [13]. Look-up tables are then generated using theTCAD simulator as discussed in Sec. II. The FinFETstructure used for simulations is shown in Fig. 3. The ef-fective oxide thickness (EOT) is 0.9 nm, fin width (WFIN)is 6 nm, and fin height (HFIN) is 30 nm. The channeldoping is 1 × 1015 cm−3 and the source/drain doping is 1× 1020 cm−3 with an overlap distance (LOV) of 2 nm anda 1 nm/decade Gaussian doping gradient into the chan-nel. The device parasitics such as overlap and junctioncapacitances are automatically considered during the ta-ble generation. To account for process variations, 3σ val-ues for LG, WFIN, EOT, LOV and doping, used in thiswork are: ±2 nm, ±1 nm, ±0.1 nm, ±1 nm and ±10% re-spectively [14]. Process corners such as fast (FF), typical(TT) and slow (SS) are generated at room temperatureand 70 ◦C. Metal-insulator-metal structure is used to re-alize capacitive elements, which gives a variation of ±15 %in capacitance values for 3σ variations in process param-eters, mentioned above. Fins that do not have the gatestack over them are used as on-chip resistors [15]. Thesefin resistors (FIN-RES) have As doping of 1 × 1015 cm−3.The 3σ values, mentioned above, are used to account forprocess variations in the resistors, and it is found to gen-erate a variation of ±20 % in resistance values.

All simulations are performed on a system with a 3 GHzprocessor, 4 GB RAM and 1024 Kb cache.

M1

M3

M7M

5

Vout

(18 fF)

CL

M4

Vin

M6

M8

DDV

M2

(a)

(26)

(26)(8)

(8)

(3)

(3)

(1)

(1)

(b)

TT

FF SS

1

0.5

0 0 10 20 30 40 50 60 70 80

Vol

tage

(V

)

Time (ps)

Vout: LUTVout: TCAD

Vin: Input

Vin

Vout

Fig. 4. (a) Buffer chain circuit with Nfin shown in brackets, L = 20nm and VDD = 1 V. (b) Comparison of LUT and TCAD results.

A. Buffer Chain

The buffer chain, shown in Fig. 4, is commonly usedfor driving large capacitive loads in digital integratedcircuits. This circuit is designed using FinFETs with

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506

L = 20 nm, VDD = 1 V and with the same W/L (Num-ber of fins/Gate length) for the n- and p-FinFETs. Inputtransistors M1 and M2 are chosen to have minimum size.The number of fins (Nfin, an integer) of the remainingthree NMOS/PMOS transistors are considered as designvariables. The buffer chain is designed to minimize therise and fall propagation delay while driving a 18 fF ca-pacitive load. Process variations are taken into accountduring the design cycle. The design obtained with PSOalgorithm is given in Fig. 4 along with the simulationresults at different process corners for the rising edge ofthe input signal. The design given by the optimizer gavedelay values very close to the manually designed bufferchain circuit using the logical effort theory. This serves toverify the effectiveness of the optimizer, particularly forcircuits where efficient manual design is difficult to obtainwith PVT variations taken into account.

The design obtained with the PSO algorithm is also sim-ulated at all three process corners using TCAD simulatorfor the purpose of validation of the new LUT techniqueand proposed platform for FinFET circuit designs. TheTCAD simulation results are plotted in the Fig. 4(b) andan excellent match can be observed between the LUT andTCAD simulation results.

102

100

104

106

108

1010

Vin2

M8M7

Vout

M1 M

2

M3 M

5

Vin1

(b)

DDV

M

(8) (160)

LC

(20 fF)

(4.4 fF)

C

R1(19.1 K)

(20)(2)

(18) (18)

6M

4

(8)

(a)

(16)

−40

0

40

80

−225

−180

−135

−90

−45

0

Phas

e (D

egre

e)

Frequency (Hz)

Gai

n (d

B)

LUTTCAD

Fig. 5. (a) Two-stage wide-band Miller op-amp circuit. Numbersin brackets show Nfin for transistors and other component values.(b) Comparison of LUT and TCAD results for the TT processcorner, VDD = 1 V, CL = 20 fF and L = 50 nm for M1 to M5,250 nm for M6 to M8.

B. Two-stage wide-band Operational Amplifier

A two-stage Miller op-amp circuit is shown in Fig. 5.Process variations (TT, FF, SS, FS, SF), supply variations(± 10 % at 1.0 V), and temperature variations (27 ◦C to70 ◦C) are taken into account during the design cycle. Thecircuit is designed for following specifications:Open loop gain ≥ 80 dB, power dissipation ≤ 100 μW,

phase margin ≥ 65◦, unity gain frequency ≥ 1 GHz, andrise and fall slew rates ≥ 100 V/μs.

The op-amp specifications have different orders of mag-nitudes, which require different weights to be assigned tothem during the design process. There are various schemesreported in the literature for assignments of weights, suchas constant weights, adaptive weights, etc. We use theconstant weight approach in our work. To take care ofstability of the designed circuit, a particle in PSO algo-rithm is considered to be leader only if it has a phasemargin greater than 55◦. This ensures that solutions witha smaller error but with poor phase margin would notevolve.

TABLE IPerformance measures at various process corners for the

automatically designed op-amp circuit of Fig. 5. PM (Phase

Margin), UGF (Unity Gain Frequency), PD (Power

Dissipation), SR (Slew Rate Rise) and SF (Slew Rate Fall).

The desired specifications are shown in the brackets.

Desired VDD= 1.1 V VDD= 0.9 VSpecifications TT FF SS TT FF SS

Gain (≥ 80 dB) 81.5 79 83.4 83.4 80.4 84.4

PM (≥ 65◦) 63.7 65.5 61.8 62 65 61

UGF (≥ 1 GHz) 1.34 1.45 1.3 1.17 1.2 1.06

PD (≤ 100 μW) 83 102 69 48 59 40

SR (≥ 100 V/μS) 493 521 486 344 362 339

SF (≥ 100 V/μS) 474 498 468 254 270 246

The design variables for the op-amp are: number of fins(Nfin) for each transistor, R1, and C. The systematic off-set criterion is used during the design cycle. Only the so-lutions which have the transistors operating in the properoperating regime (e.g., M2 in the saturation regime) areconsidered for optimization. Fig. 5(a) shows the designobtained using PSO algorithm, and Table I shows the per-formance measures at various process corners, supply volt-ages and T = 27 ◦C, which are close to the desired spec-ifications. The performance measures at T = 70 ◦C werealso observed to be within the specified values.

To validate the proposed LUT-PSO-based design ap-proach in frequency domain, the op-amp design obtainedwith the LUT-PSO-based platform is simulated usingTCAD simulator and simulation results are shown in Fig.5(b) along with the results obtained with the LUT ap-proach. A very good agreement between LUT and TCADsimulation results for a small-signal analysis is an indica-tion of accurate representation of derivative informationby the LUT technique.

C. Three-stage high-gain operational amplifier

The next circuit designed in this work is the three-stagehigh-gain op-amp generally used in current generator cir-cuit [16]. The schematic diagram of this circuit is shownin Fig. 6. The circuit is designed for FinFET devices withL = 50 nm and for following specifications:Open loop gain ≥ 100 dB, power dissipation ≤ 100 μW,

507

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M3

M5

DDV

CL

DDV /2

M1 M2 M7

M6

M11M12

M10

M8 M13

R 1

M9

DDV /2

M4 Vout

Vin2Vin1(1)

C

(7)

(18)(18)

(8) (8) (16) (16)

(38)

(7)

(14)

(11.42 K) pF)

(0.18(0.1 pF)

(38)

(1)

0 102 4 6 8

(a)

(b)

10 10 10 10 10 10

Frequency (Hz)

PhaseGain

0

50

100

−225

−180

−135

−90

−45

0

Gai

n (d

B)

Phas

e (D

egre

e)

Fig. 6. (a) Three-stage high-gain op-amp circuit. Numbers inbrackets show Nfin for transistors and other component values. (b)Frequency-domain simulation results obtained with LUT approachat TT process corner for VDD = 1 V, CL = 0.1 pF and L = 50 nmfor all transistors.

10 1

10 0

10−1

10−3

10−4

10−5

0 50 100 150 200Iterations

RM

S E

rror

100

102

104

106

Gai

n (d

B)

Off

set V

olta

ge (

V)

GainOffset Voltage

Fig. 7. (a) Plots of gain, and offset voltage at TT corner forVDD = 1.1 V, T = 27 ◦C and (b) RMS error versus iterationnumber for the three-stage op-amp circuit shown in Fig. 6 duringthe first phase of design cycle.

phase margin ≥ 65◦, unity gain frequency ≥ 100 MHz, off-set voltage ≤ 50 μV, and rise, fall slew rates ≥ 100 V/μs.

This circuit has nine design variables, which include:seven fin (Nfin) values, R1, and C. To reduce the designtime, this circuit is designed in two phases, both steps per-formed using PSO algorithm. Initially, the circuit is de-signed at room temperature with supply variation (±10%)taken into account. After the completion of first phase,design is refined to obtain the performance measures asclose as possible to the desired specifications with PVTvariations (same as that specified for two-stage opamp cir-cuit) considered. The design solution obtained with theLUT approach is shown in Fig. 6(a) (numbers in brack-ets) and simulation results for small-signal analysis at TTprocess corner for VDD = 1 V is shown in Fig. 6(b). Ta-ble II shows the performance measures at various processcorners, supply voltages and at T = 27 ◦C, which areclose to the desired specifications. The specifications atT = 70 ◦C was also observed to be within the specifiedvalues.

TABLE IIPerformance measures at various process corners for the

automatically designed three-stage op-amp circuit of

Fig. 6. PM (Phase Margin), UGF (Unity Gain Frequency),

PD (Power Dissipation), OV (Offset Voltage), SR (Slew

Rate Rise), and SF (Slew Rate Fall). The desired

specifications are shown in the brackets.

Desired VDD= 1.1 V VDD= 0.9 VSpecifications TT FF SS TT FF SS

Gain (≥ 100 dB) 100 97.3 102 100.5 98.3 103

PM (≥ 65◦) 70 76 64 82 87 78

UGF (≥ 100 MHz) 193 205 185 179 187 172

PD (≤ 100 μW) 95 116 80 47 58 39

OV (≤ 50 μV) 33 36 32 9 14 7

SR (≥ 100 V/μS) 797 791 785 543 531 540

SF (≥ 100 V/μS) 432 508 374 309 367 266

A typical plot of evolution of gain in dB and offset volt-age for three-stage op-amp circuit at TT process cornerand VDD = 1.1 V is shown in Fig. 7(a). A plot ofrms error (between desired specifications and simulator-returned specifications) versus iteration number duringthe first phase of design cycle for three-stage op-amp isshown in 7(b).

TABLE IIITotal CPU time taken by the LUT-PSO-based platform for

the design of examples considered in this work.

Design Example Design variables CPU time

Buffer chain 3 0 h 26 m

Two-stage op-amp 7 4 h 21 m

Three-stage op-amp 9 4 h 30 m

The total CPU time taken by the proposed platformfor the design of three examples is shown in Table III.The results clearly point to the practical utility of the

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TABLE IVCPU time taken by LUT and TCAD for simulations of final

design of buffer chain and two-stage op-amp circuits

generated by LUT-PSO-based platform.

Example Analysis LUT TCAD

Buffer chain Transient 0.45 s 1 h 19 m

Two-stage op-amp AC 0.2 s 0 h 46 m

Two-stage op-amp Transient 1.48 s –

proposed platform. To observe the computational advan-tage of using LUT simulator instead of the TCAD simu-lator, the final designs obtained with the LUT-PSO-basedplatform are simulated with TCAD and LUT simulators,and CPU time taken by both simulators are shown in Ta-ble IV. For the two-stage op-amp circuit, the transientanalysis is performed using LUT circuit simulation onlyand it is not performed using TCAD simulation becauseof the limitation of large amount of simulation time re-quired by TCAD simulator. It can be clearly seen fromthe table that it is not practical to use the TCAD-basedapproach for design of large circuits in novel technologies,since both the memory requirement and CPU time wouldbe prohibitively large.

V. Summary and Conclusions

In conclusion, a new template-based LUT approach forcircuit simulation is described. A novel automatic designplatform combining the new LUT approach and the PSOalgorithm is presented for design of circuits in novel tech-nologies. Buffer chain and op-amp FinFET circuit designexamples are discussed to demonstrate the effectivenessand robustness of the proposed design environment. Theproposed LUT technique and platform is validated usingTCAD simulator, and an excellent agreement is observedbetween simulation results obtained with LUT and thatobtained with TCAD. It is also shown that proposed LUT-PSO-based platform can taken into account PVT varia-tions during the design cycle.

Acknowledgment

The authors are thankful to Synopsys, Inc. for provid-ing TCAD tools for this work. This work was performedat the Centre of Excellence for Nanoelectronics, IIT Bom-bay, which is supported by the Ministry of Communica-tions and Information Technology, Govt. of India.

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