SEU MITIGATION-Using 1/3 Rate Convolution Coding

Aabhas Rastogi, Manu Agarawal, Bhawna Gupta, Electronics & communications Electronics & communications Electronics & communications

JIIT University, JIIT University, JIIT University,321, Sector-37, Noida, India A-10, Sector-62, Noida, India A-10, Sector-62, Noida, India Aabhas1987@gmail.com manu.alone.101@gmail.com bhawna.gupta@jiit.ac.in

Abstract-With the new emerging fabrication technologythere has been scaling of components size, leading toreduction in the physical size of devices. This increasesthe frequency of radiation induced temporary faults alsocalled soft errors, which corrupts the content of thememory system.This paper proposes a new technique to protect the datafrom these soft errors which occurs in form of bit flips inthe memory. The technique introduced is based onsimple convolution codes and is proven to give goodperformance.

Keywords: Single Event Upset (SEU), Error Detection AndCorrection coding (EDAC), First in First out FIFO, Bit Error Rate(BER).

I. INTRODUCTION

The purpose of this paper is to present a sequentialencoding-decoding scheme that can be used to mitigate orcheck bit flips in the memory system. These errors are theresult of the scaling of components. The reduction in thedevice size results in decrement of the supply and operatingvoltages. Thus the device becomes more vulnerable toradiations which were once negligible and now are able toproduce upset. These types of errors resulting fromradiations are known as soft-errors [1].

These bit flips reverse the state of the transistor; thissituation is referred to as Single Event Upset (SEU). Thisproblem of SEU must be addressed and a solution must beintroduced. Various techniques can be used like space, timeor information redundancy [2]. We propose a scheme basedon information redundancy technique. The proposed schemeuses convolutional codes to encode and decode the datasequence. Convolutional codes are among the most usedEDAC techniques and are usually exploited to protect datastreams, especially during transmissions [3].

The encoder is used to introduce informationredundancy and the sequential decoder reconstructs theoriginal data and corrects it if there are any errors.Sequential decoding has the Advantage that it can performvery well with long-constraint length convolutional codes,

but it has a variable decoding time [4]. The discussion ofsequential decoding algorithms will be highlighted here inthe later half of this project.

The paper is divided into V parts. Section II gives a gistabout the convolution codes. The scheme is a sequentialnetwork which is presented in section III. Section IV reportsexperimental results and section V concludes the paper.

II. CONVOLUTIONAL CODES

A convolutional code is an error-correction code wherethe source information is processed as a stream and thetransmitted bits are a linear function of the past source bits.A convolutional code produces a n-bits coded word startingfrom a m-bits word (m /n). The quantity m/n is called rateand represents the number of generated bits for each inputbit. For example in Fig,3, with a rate of 1/3, the encoderproduces three output bits for each input bit.

Figure 1. Sequential Encoder. Rate 1/3 generator polynomial G1=(1,1,1)G2=(1,0,1) and G3=(1,1,0)

Usually the rule for generating the transmitted bitsinvolves feeding the present source bit into a linear Shift-register (state register) of length k, and transmitting one ormore linear functions of the state of the shift register at eachiteration [6].The way in which the original bits arecombined to generate the output is described by generatorpolynomials.

_____________________________ 978-1-4244-4520-2/09/$25.00 ©2009 IEEE

Figure 2. Memory Protection SchemeIII. SEQUENTIAL CODING

The scheme has two parts encoding and decoding. Theencoding is performed as in classical convolutionalencoding, processing the input stream with a shift-registerbased architecture. The decoder, however, is a bit differentfrom classical decoding schemes. Instead of requiringseveral stages for the word decoding, the proposed decodercan produce the correct bits every clock cycle (after aninitial latency of two computational steps). This is possiblesince we are working under the hypothesis of double error.

This architecture can be exploited to protect bothtransmitted data as well as soft error affected data. Asshown in fig 2. transmit data passes through two modules ofa FIFO. Data stored in the FIFO can be affected by SEU. Inthis case the data can be encoded while being stored anddecoded after reading it from a FIFO, this will make thedata error resistant even in case of upsets.

In the following the sequential encoder and decoder arepresented in detail.

A. Sequential encoding

The encoder is the presented in fig1. The circuit consistsof a three register architecture processing three informationbits and producing three coded bits at each cycle.

The entire data word is passes through the encoder thusallowing the coding in a number of steps which isproportional to the word’s length. Specifically, for an n bitdata stream the coding process requires n + 1 cycles. This isbecause the 2 terminating bits, having value 0 has to beadded at the end of the stream, to allow the decoding. Theencoder’s state registers are initially loaded with the state 00before the encoding process begins, in order to allow thedecoding process to start from a known state.

Equation 1 shows the relation of three polynomials withthe data bits.

1

2

21

−

−

−−

⊕=⊕=

⊕⊕=

nnn

nnn

nnnn

ddzddy

dddx (1)

B. Sequential decoding

The sequential decoder is intended to produce, after aninitial delay, a decoded bit at every clock cycle,

receiving as input couples of coded bits.The decoding scheme is derived by applying simple

algebraic considerations. Considering equation 1 we canderive three possible decoding for the bit dn, that we call dnx,dny and dnz :

1

2

21

−

−

−−

⊕=

⊕=⊕⊕=

nnnz

nnny

nnnnx

dzd

dydddxd

(2)

The process of decoding is depicted in fig.3. where thedata bits corresponding to each polynomial are beinggenerated by DEC SEQ and are being correlated usingCORR SEQ detect the type of error conditions it satisfied.Hence reconstruct the original data.

Fig. 3. Sequential Decoder

When receiving an input sequence has no errors,dnx ,dny and dnz coincide at each time instant and

represent the correct decoded value of dn. Otherwise, if anerror is present (xn or yn or zn is corrupted), the generatedvalues do not match. In order to understand which valuesare correct, the propagation of the fault is observed. Let’sselect dnx as possible incorrect result and compute equation2 at time instant n + 1.

nznzn

nnyn

nnxnxn

dzd

dydddxd

⊕=

⊕=⊕⊕=

++

−++

−++

11

111

111

(3)

As it can be noticed the value of dnx affects onlyone of the three equations in 3.Similar is the case withdnz.Under the condition of single error, 3 situations arepossible.

1) xn is corrupt, yn and zn correct, dnx and dn+1x arecorrupt and values dny and dnz, dn+1y and dn+1z areidentical.

2) yn is corrupt, xn and zn correct, dny is corrupt and

values dnx and dnz are equal. And dn+1x, dn+1y anddn+1z are identical

3) zn is corrupt then dnz is corrupted too, dn+1z isincorrect and dn+1x and dn+1y will be equal. Thismeans that dn+1x and dn+1z disagree

All these conditions are presented in Table I.

TABLE I CONDITIONS FOR ERROR IN THE POLYNOMIALS

The conditions for detecting error are listed in Table I Hence for single errors there are three cases:

– dnx , dny and dnz are equal: all represent the correctdecoded value dn

– dnx ,dny are different and dnx ,dnz are also different: anerror occurred.

If dn+1z and dn+1y are equal and dn+1x and dn+1z aredifferent (using as decoded value dnx, dny, dnz ): dn iscorrupt, dn = dny or dnz. Similarly we can form cases whendny or dnz is corrupt.

Let us discuss a condition for double error. Assumingthat an error has occurred in xn and xn+1 simultaneously. dnxwill be corrupted, dnx, dny would differ and dnx ,dnz would

differ as well. At this stage we know an error has occurred.But to trace the error we need to use equation 3.

As dn+1x is dependent on dnx and xn+1 and both arecorrupt. Thus no change will occur in dnx+1.hence dn+1x ,dn+1y dn+1z will coincide. It is a unique condition and willonly occur when both xn and xn+1 are corrupted. Only intwo cases of error it appears that all the conditions up tillcolumn 4 in table I are identical. The problem can be solvedusing equation 5 which gives different results for the twocases.

znnzn

nynyn

nxxnnxn

dzd

dydddxd

122

22

122

+++

++

+++

⊕=

⊕=⊕⊕=

(4)

This way considering the relationships provided byequations 2, 3 and 4 different types of errors can bedetected.

IV. EXPERIMENTAL RESULTS

This section reports the experimental results relatedto the implementation of the proposed architectures.The solutions have been validated by randomlygenerating one or more errors in the coded word andverifying the effects on the decoded word.

Figure 4. Bit Error Rate Vs Eb/No comparison between 1/2- rate and 1/3- rate sequential decoder.

The architecture is able to properly identify and correctup to two errors in the every three bits. Moreover, multipleerrors can be properly corrected if having a minimumdistance of five couples of coded bits. Finally, simulation

results show that sequences of two errors can be detectedand corrected in 60% of the case, depending on theirposition.For double error the scheme corrects all double errors inevery 3 bits except simultaneous errors in

- xn, yn+1 or xn zn+1

- yn, xn+1 or yn, zn+1

- zn xn+1 or zn yn+1

The Fig 4. shows the comparison of proposed codingscheme with ½ rate sequential encoding[5].The proposedscheme has lower BER compared to later.

V. CONCLUSION

This paper discusses the use of convolutional codes forthe protection of memory and critical data from the effectsof SEU (Single Event Upset) in electronic devices.Convolutional encoding has not been exploited yet in thisfield, due to the lack of simple decoding architectures thatcan allow the protection of two single bit-flip withoutintroducing heavy penalties in terms of area and timeoverhead. To end this, architecture has been presented thatrequires little area and time for the encoding and decodingphases that allow the recovery of data from up to 2 faultsevery 3 source bits, thus incrementing the correcting powerwith respect to single-error protection schemes [5].Thearchitecture is well suited for strem-based coding (like incase of stream communication between two modules on thesame device).

The proposed solutions can be therefore a validalternative to current techniques for SEU mitigation. In

future works, we believe that the exploration of differentpolynomial generators and of techniques like puncturing canfurther improve the presented encoding schemes.

ACKNOWLEDGMENT

The authors would like to thank Jaypee Institute ofInformation Technology University for providing all theresources and support in doing this research work.

REFERENCES

[1] Allan. H. Johnston, Scaling and Technology Issuesfor Soft Error Rates, 4th Annual Research Conferenceon Reliability, Stanford University, Oct. 2000

[2] F. Lima Kanstensmidt, L. Carro, R. Reis, Faulttolerant techniques for SRAM-based FPGAs,Springer, 2006.

[3] Ajay Dholakia, Introduction to convolutional codeswith applications, Kluwer Academic Publishers,1994.

[4] Viterbi .J, "Error Bounds for Convolutional Codesand an Asymptotically Optimum DecodingAlgorithm," IEEE Transactions on InformationTheory, Vol.13, April, 1967, pp. 260-269.

[5] Frigerio,L. Convolutional Coding for SEUmitigation , F.European Test, 2008 13th VolumeIssue ,25-29 May

[6] D.J.C. MacKay, Information Theory, Inference,and Learning Algorithms, Cambridge University Press,2003.