Stability Enhancement Techniques for Nanoscale SRAM Circuits: A Comparison

Sherif A. Tawfik* and Volkan Kursun** *Department of Electrical and Computer Engineering,

University of Wisconsin–Madison, Madison, Wisconsin, 53706-1691, USA

**Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology,

Clear Water Bay, Kowloon, Hong Kong Abstract –Four circuit techniques for high data stability and low leakage power consumption in static CMOS memory circuits are compared in this paper. The techniques that provide the highest data stability, the lowest leakage power consumption, and the smallest memory cell area are identified. The first circuit technique employs a dynamic voltage swing wordline driver to control the operation of the standard six-transistor (6T) memory cells. The wordline voltage swing is dynamically tuned during read and write operations in order to simultaneously enhance the read stability and the write margin without increasing the size of the transistors in the SRAM cell. The other three circuit techniques tackle the data stability challenge by modifying the memory cell circuit structure. A nine-transistor (9T), an eight-transistor (8T), and a dual-threshold-voltage (dual-Vt) seven-transistor (7T) SRAM circuit are considered in this paper. The data storage nodes are isolated from the bitlines with these techniques, thereby significantly enhancing the read stability as compared to the standard 6T SRAM circuits. Among the evaluated memory circuits, the 9T and the 8T SRAM cells provide the highest data stability during a read operation. The read stability of the 9T and the 8T SRAM cells is 80% higher as compared to a standard 6T SRAM cell sized for data stability (with � = 3) in a 65nm CMOS technology. Alternatively, the dynamic wordline voltage swing technique offers the smallest area and the dual-Vt 7T SRAM cell consumes the lowest leakage power among the evaluated memory cells.

I. INTRODUCTION The amount of embedded SRAM in modern systems-on-chips

(SoCs) increases to meet the performance requirements in each new technology generation [1]. Lower voltages and smaller devices cause a significant degradation in SRAM cell data stability with the scaling of CMOS technology. In addition to the data stability issues, SRAM arrays are also an important source of leakage due to the enormous number of transistors in the memory banks. The development of a memory technology with higher data stability and lower leakage power consumption characteristics is therefore highly desirable.

A conventional 6T SRAM cell in a 65 nm CMOS technology is shown in Fig. 1. The data stability of a 6T SRAM cell is characterized by the static noise margin (SNM) during a read operation [3]-[6]. The data is most vulnerable to external noise during a read operation due to the intrinsic disturbance caused by the direct data-read-access mechanism of a standard 6T SRAM cell. A minimum size SRAM cell is highly desirable for maximizing the memory integration density. The noise margins of a minimum size standard SRAM cell are, however, dangerously low. The SNM of the standard 6T SRAM cell is typically enhanced by increasing the size of the pull-down devices of the cross-coupled inverters. This standard approach based on transistor sizing, however, also causes a significant increase in the cell area and a higher leakage power consumption while enhancing the stability.

Four alternative circuit techniques [3]-[6] for enhancing the data stability and reducing the leakage power are explored in this paper. The first technique is based on a dynamic voltage swing wordline driver for the simultaneous enhancement of the read data stability and the write margin with minimum sized transistors. The other three circuits are 9T, 8T, and dual-threshold-voltage (dual-Vt) 7T SRAM circuits with modified memory cell structures implementing separate read and write access mechanisms to enhance the data stability and the read speed.

The paper is organized as follows. The different static CMOS memory techniques are described in Section II. The SRAM circuits are characterized for read stability, write margin, read current, leakage power, and cell area in Section III. The techniques that

provide the highest data stability, the lowest leakage power consumption, and the smallest memory cell area are identified. Finally, conclusions are offered in Section IV.

VDDVDDBL BLB

P2P1

N2N1

N4N3

WL WL

�*65 / 65

65 / 6565 / 65

65 / 65 65 / 65

Node1 Node2

�*65 / 65

Fig. 1. A standard 6T SRAM cell in a 65nm CMOS technology. The size of each transistor is given as W/L. W: transistor width (nm). L: transistor channel length (nm). The � is typically in the range of 2 to 3 for data stability.

II. ROBUST SRAM CIRCUIT TECHNIQUES Alternative static CMOS memory technologies for achieving enhanced data stability are explored in this section. The 6T SRAM circuit with dynamic wordline voltage swing technique is presented in Section II.A. The 9T, the 8T, and the dual-Vt 7T SRAM circuits are described in Sections II.B, II.C, and II.D, respectively.

A. 6T SRAM Circuit with Dynamic Wordline Voltage Swing A 6T SRAM circuit technique with dynamic wordline voltage

swing is proposed in [5] for enhanced data stability, reduced leakage power consumption, and smaller cell area. A specialized wordline driver for dynamically adjusting the voltage swing of the wordline signal is utilized with this technique. The circuit schematic of the dynamic voltage swing wordline driver is shown in Fig. 2. The wordline driver is formed by cascaded inverters. Two extra transistors (P3 and P4) are added in the last stage inverter as shown in Fig. 2.

The wordline driver has two modes of operation: the reduced-voltage-swing mode and the full-voltage-swing mode. The technique is based on dynamically adjusting the strength of the bitline access transistors by tuning the channel resistance with the gate voltage. The variation of the drain-to-source resistance of a minimum sized bitline access transistor (NMOS) with the gate voltage is shown in Fig. 3. The drain-to-source resistance is increased by 82% when the gate voltage is reduced by 30% (from 1V to 0.7V). The gate voltage of the bitline access transistors is determined by the Read signal. During a read operation the Read signal is connected to VDD. P3 is turned off. A threshold voltage drop (|Vtp|) is observed across P4. The voltage swing of the driver output is thereby reduced by |Vtp|. After WLin transitions to VDD, WL rises only up to VDD - |Vtp| for achieving data stability during a read operation. Alternatively, during a write operation, the Read signal is connected to GND. P3 is turned on. After WLin is asserted, WL rises all the way up to VDD for achieving write ability with a high write margin.

The operation of a minimum sized 6T SRAM cell (� = 1 in Fig. 1) with the dynamic voltage swing wordline driver is described next. Prior to a read operation, the bitlines are pre-charged to VDD. The Read signal is maintained at VDD. WLin transitions to VDD to start the read operation. The wordline driver operates in the reduced-voltage-swing mode. The WL transitions to VDD - |Vtp|, thereby weakly activating the bitline access transistors of the addressed memory cell. Provided that Node1 (in the SRAM cell) stores “0”, BL is discharged through N3 and N1. Alternatively, provided that Node2 (in the SRAM cell) stores “0”, BLB is discharged through N4 and N2. The voltage disturbance at the data storage nodes during a read operation is suppressed, thereby enhancing the data stability without increasing

978-1-4244-2599-0/08/$25.00 ©2008 IEEE 2008 International SoC Design ConferenceI-113

the size of the pull-down transistors (N1 and N2 are minimum sized with � = 1 in Fig. 1).

P5

P4P3

VDDVDD

Read

WLin WL

N5

Fig. 2. The schematic of the variable voltage swing wordline driver [5].

1.E+04

1.E+06

1.E+08

0 0.2 0.4 0.6 0.8 1

VG (V)

RD

S(�

)

L = W = 65nmT = 27oC

82% higher resistance

VG = 0.7V

VG

1V

Fig. 3. Variation of the drain-to-source resistance of a minimum-sized bitline access (NMOS) transistor with the gate voltage in a 65nm CMOS technology.

Both bitlines are periodically precharged to VDD. Prior to a write operation, one of the bitlines is selectively discharged to VGND depending on the data to be written into the SRAM cell. In order to start the write operation, the WLin transitions to VDD. During a write operation the Read signal is maintained at 0V. The wordline driver therefore operates in the full-voltage-swing mode. WL transitions to VDD. Data is forced into the SRAM cell through the access transistors. The access transistors are strongly turned on (VG = VDD) during the write operation due to the full voltage swing WL signal. The write-ability is thereby achieved with a high write margin with the dynamic wordline voltage swing memory technique.

B. 9T SRAM Circuit The 9T SRAM cell [3] is presented in this section. The schematic of the 9T SRAM cell, with transistors sized for a 65-nm CMOS technology, is shown in Fig. 4. The upper sub-circuit of the 9T memory circuit is essentially a conventional 6T SRAM cell with minimum sized devices (composed of N1, N2, N3, N4, P1, and P2). The two write access transistors (N3 and N4) are controlled by a write signal (WR). The data is stored within this upper memory sub-circuit. The lower sub-circuit of the new cell is composed of the bit-line access transistors (N5 and N6) and the read access transistor (N7). The operations of N5 and N6 are controlled by the data stored in the cell. N7 is controlled by a separate read signal (RD).

During a write operation, WR signal transitions high while RD is maintained low. N7 is cutoff. The two write access transistors N3 and N4 are turned on. In order to write a “0” to Node1, BL and BLB are discharged and charged, respectively. A “0” is forced into the SRAM cell through N3. Alternatively, for writing a “0” to Node2, BL and BLB are charged and discharged, respectively. A “0” is forced onto Node2 through N4. During a read operation, RD signal transitions high while WR is maintained low. The read access transistor N7 is activated. Provided that Node1 stores “1”, BL is discharged through N5 and N7. Alternatively, provided that Node2 stores “1”, the complementary bitline (BLB) is discharged through N6 and N7. Since N3 and N4 are cutoff, the storage nodes Node1 and Node2 are completely isolated from the bitlines during a read operation. Unlike the 6T SRAM cell, the voltage of the node which stores “0” is strictly maintained at the ground level during a read operation with the 9T SRAM circuit. The read stability of the 9T SRAM cell is thereby enhanced as compared to the standard 6T SRAM circuits.

VDD VDDBL

WR WR

RD

P1 P2

N1 N2

N3 N4

N5 N6

N7

Node1 Node2

65/65 65/65

65/6565/65

65/65 65/65

100/65100/65

130/65

Node3

BLB

Fig. 4. The schematic of the 9T SRAM circuit [3] in a 65nm CMOS technology. The size of each transistor is given as W/L. W: transistor width in nanometer. L: transistor channel length in nanometer. C. 8T SRAM Circuit The 8T SRAM circuit [4] is presented in this section. The schematic of the 8T SRAM cell sized for a 65nm CMOS technology is shown in Fig. 5. The left sub-circuit of the 8T memory cell is a conventional 6T SRAM cell with minimum sized devices (composed of N1, N2, N3, N4, P1, and P2). Two data access transistors (N3 and N4) and two bitlines (WBL and WBLB) are used for writing to the SRAM cell. An alternative communication channel (composed of a separate read bitline RBL and the transistor stack formed by N5 and N6) is used for reading the data from the cell.

Two separate control signals R and W are used for controlling the read and the write operations, respectively, with the 8T SRAM circuit as shown in Fig. 4. During a read operation, the read signal R transitions to VDD while the write signal W is maintained at VGND. The read bitline (RBL) is conditionally discharged based on the data stored in the SRAM cell. The storage nodes (Node1 and Node2) are completely isolated from the bitlines during a read operation. The data stability is thereby significantly enhanced as compared to the standard 6T SRAM cells. Utilizing single-ended read access mechanism with the 8T SRAM circuit reduces the memory cell area overhead as compared to the 9T SRAM circuit. However, unlike all the other techniques evaluated in this paper, the 8T SRAM cells require 3 bitlines for performing the read and write operations. The additional bitline to provide a data-isolated read communication channel could cause larger memory array area despite the smaller sizes of the individual memory cells with this technique as compared to the 9T SRAM cells.

VDD VDDWBL WBLB

P2P1

N2N1

N4N3

W W

65/65 65/65

65/6565/65

65/65 65/65 R

N5

N6

RBL

130/65

130/65Node1

Node2

VDD VDDWBL WBLB

P2P1

N2N1

N4N3

W W

65/65 65/65

65/6565/65

65/65 65/65 R

N5

N6

RBL

130/65

130/65Node1

Node2

Fig. 5. The schematic of the 8T SRAM circuit [4] in a 65nm CMOS technology. The size of each transistor is given as W/L. W: transistor width in nanometer. L: transistor channel length in nanometer.

D. Dual-Vt 7T SRAM Circuit The circuit schematic of the 7T dual-Vt SRAM cell [6] with transistors sized for a 65nm CMOS technology is shown in Fig. 6. The cross-coupled inverters formed by the transistors N1, P1, N2, and P2 store a single bit of information. The write bitline WBL and the pass transistor N3 are used for transferring new data into the cell. Alternatively, the read bitline RBL and the transistor stack formed by N4 and N5 are used for reading data from the cell. Two separate control signals R and W are used for controlling the read and the write operations, respectively, with the 7T SRAM circuit as shown in Fig. 6. Utilizing single-ended read and write data access mechanisms reduce the area overhead of the 7T SRAM circuit as compared to the 9T and the 8T SRAM circuits. Prior to a read operation, the RBL is pre-charged to VDD. To start the read operation, the read signal R transitions to VDD while the

2008 International SoC Design ConferenceI-114

write signal W is maintained at VGND. If a “1” is stored at Node1, RBL is discharged through the transistor stack formed by N4 and N5. Alternatively, if a “0” is stored at Node1 RBL is maintained at VDD. The storage nodes (Node1 and Node2) are completely isolated from the bitlines during a read operation. The data stability is thereby significantly enhanced as compared to the standard 6T SRAM cells.

VDD VDDWBL

P2P1

N2N1

N3

W

65/65 65/65

65/65

65/65 65/65 R

N5

N4

RBL

130/65

130/65

Node1

Node2

Fig. 6. The schematic of the 7T dual-Vt SRAM circuit [6] in a 65nm CMOS technology. The size of each transistor is given as W/L. W: transistor width in nanometer. L: transistor channel length in nanometer. Thick line in the channel area indicates a high-Vt transistor.

Prior to a write operation the WBL is charged (discharged) to VDD (VGND) to get ready to force a “1” (“0”) onto Node1. To start the write operation, the write signal W transitions to VDD while the read signal R is maintained at VGND. The data is forced onto Node1 through the low-Vt bitline access transistor N3. The following design constraints exist for achieving write ability through only one bitline with the 7T SRAM cell. To be able to write a “0” onto Node1, the pass transistor N3 must be stronger as compared to the pull-up transistor P1. Alternatively, to be able to write a “1” onto Node1, the pass transistor N3 must be stronger as compared to N1. Furthermore, since N3 transfers a degraded “1” (due to the Vt drop across the N-channel access transistor), the inverter formed by N2 and P2 is required to have a low switching threshold voltage that assists the transfer of a full “1’ onto Node1. These design requirements are achieved by employing dual-Vt transistors within the cross-coupled inverters (high-threshold-voltage transistors N1, P1, and P2 and a low-threshold-voltage transistor N2), as shown in Fig. 6. The use of minimum sized high-Vt transistors reduces the leakage power without degrading the read speed since the high-Vt devices are off the critical read delay path in a 7T SRAM circuit.

III. COMPARISONS The standard 6T SRAM cells (with � = 1, 2, and 3), a minimum sized 6T SRAM cell with a dynamic wordline voltage swing driver, the 9T SRAM cell, the 8T SRAM cell, and the 7T dual-Vt SRAM cell are characterized in this section for read stability, write margin, read current, leakage power consumption, and layout area. The techniques that provide the highest data stability, the lowest leakage power consumption, and the smallest memory cell area are identified. The SRAM circuits are simulated in a 65nm CMOS technology (Vtn = |Vtp| = 0.22V, Vtn-high = |Vtp-high| = 0.42V, and VDD = 1V). Data are measured at 70°C. A. Data Stability

Static noise margin (SNM) is the metric used in this paper to characterize the read stability of the SRAM cells. The SNM is the minimum DC noise voltage necessary to flip the state of an SRAM cell. The read SNM of the SRAM cells is depicted in Fig. 7. When Node1 of a 6T SRAM cell is at VDD, Node2 rises to a higher steady state voltage due to the voltage division between the bitline access transistor and the pull-down transistor in the inverter during a read operation. Data stored in the 6T SRAM cell is highly vulnerable to noise due to the raised Node2 voltage during a read operation. The read SNM is significantly enhanced with the 9T, the 8T, and the 7T SRAM cells by decoupling the bitlines from the data storage nodes during a read operation as described in Section II. The read SNM is enhanced by 235% (80%) with the 9T and 8T SRAM cells as compared to a standard 6T SRAM cell with � = 1 (� = 3). The SNM of the 7T SRAM cell is slightly lower (9.5%) as compared to the 9T and the 8T SRAM cells due to the asymmetrical design of the dual-Vt cross-coupled inverters.

Alternatively, with the dynamic wordline voltage swing technique,

the access transistors of the conventional 6T memory cells are intentionally weakened to reduce the voltage disturbance at the data storage nodes during a read operation. The data stability is enhanced by 122% and 19% with the dynamic wordline voltage swing technique as compared to a standard full voltage swing 6T SRAM cells with � = 1 and 3, respectively, as illustrated in Fig. 7.

0

50

100

150

200

250

300

350

6T (� = 1) 6T (� = 2) 6T (� = 3) Dynamic Wordline Voltage

9T 8T 7T

SNM

(mV)

Highest

Fig. 7. A comparison of the read static noise margins provided by the different techniques evaluated in this paper.

B. Write Margins Writing to the 6T, the 8T, and the 9T SRAM cells is achieved by discharging one of the bitlines to ground. Writing to an SRAM cell is, however, possible with a voltage higher than 0V on the discharged bitline (performing a write operation with an incomplete/partially discharged bitline). The write margin is the maximum incomplete bitline discharge voltage for which the successful transfer of new data into the 6T, 9T, and 8T SRAM cells is achieved [8]. The content of an SRAM cell with a higher write margin is easier to be modified.

For the 7T SRAM cells, two different write margins exist. The definition and the measurement of the write margin when writing a “0” are similar to the 6T, the 8T, and the 9T SRAM cells. Alternatively, when writing a “1” into the 7T SRAM cell, the write margin is the difference between VDD and the minimum bitline voltage required to achieve a successful transfer of a “1” into the 7T SRAM cell. The write margins for the SRAM cells are listed in Table I. Increasing the size of the pull-down devices of the standard 6T SRAM cells for enhanced read stability comes at the cost of degraded write margin as listed in Table I. The dynamic voltage swing wordline driver technique, the 9T SRAM cell, and the 8T SRAM cell offer the highest write margin due to the minimum transistor size in the cross-coupled inverters. The worst-case write margin of the 7T SRAM cell is degraded as compared to the other SRAM circuits due to the utilization of a single-ended write access.

TABLE I. WRITE MARGINS OF THE SRAM CELLS. SRAM Cell Write Margin (mV)6T (� = 1) 410 6T (� = 2) 310 6T (� = 3) 250

6T with dynamic voltage swing wordline driver 410

9T 410 8T 410

7T writing “0” 240 7T writing “1” 420

C. Read Current The cell read currents produced by the different SRAM circuits are compared in Fig. 8. The cell read current is the maximum current drawn from the bitline during a read operation. The bitline is discharged faster with a higher cell read current. The cell read current is reduced with the dynamic wordline voltage swing technique by 24% as compared to a standard full-voltage swing read operation with the conventional 6T SRAM cells due to the weaker bitline/data access transistors. Alternatively, the cell read currents of the 9T, 8T, and 7T SRAM cells are significantly enhanced by up to 107% because of the smaller resistance of the isolated read communication channels as compared to the critical read delay path in a conventional full-voltage swing 6T SRAM cell.

2008 International SoC Design ConferenceI-115

0

10

20

30

40

50

Rea

d C

urre

nt (μ

A)

6T (� = 1) 6T (� = 2) 6T (� = 3) Dynamic Wordline Voltage

9T 8T 7T

Highest

Fig. 8. Comparison of the peak read current produced by the SRAM cells.

D. Leakage Power Consumption The leakage power consumption of the SRAM circuits is shown in

Fig. 9. The leakage power of an SRAM cell is determined by the total effective transistor width and the threshold voltages of the transistors that produce the leakage current. Transistor sizing for enhanced data stability comes at a cost of significant additional leakage power with the standard full-voltage-swing 6T SRAM circuits. The leakage power is doubled when � is increased from 1 to 3 with the standard 6T SRAM circuit, as illustrated in Fig. 9.

The dual-Vt 7T SRAM cell consumes the lowest leakage power by utilizing minimum sized high-Vt transistors in the cross-coupled inverters. The leakage power of the dynamic wordline voltage swing technique, the 9T SRAM cell, the 8T SRAM cell, and the dual-Vt 7T SRAM cell is reduced by 51%, 23%, 21%, and 57%, respectively, as compared to a standard 6T SRAM cell sized for read stability (� =3).

0

10

20

30

40

50

60

Leak

age

Pow

er (n

W)

6T (� = 1) 6T (� = 2) 6T (� = 3) Dynamic Wordline Voltage

9T 8T 7T

Lowest

Fig. 9. Leakage power consumption of the SRAM circuits. T = 70oC.

C. Area Comparison The thin cell layouts of the 6T SRAM cells are shown in Fig. 10.

The 6T SRAM cells with � = 1 and � = 2 have the smallest area due to the fewer transistors. The area overhead of the dynamic voltage swing wordline technique is caused by the extra transistors in the wordline drivers (transistors P3 and P4 in Fig. 2). These transistors can be shared between the wordline drivers of the different rows in an SRAM array. Hence, the area overhead of these transistors is small. The 9T, 8T, and 7T SRAM cells have an area overhead of 36%, 19%, and 4.8%, respectively, as compared to a standard 6T SRAM cell sized for data stability (� = 3).

IV. CONCLUSIONS Four circuit techniques for providing enhanced data stability and

low leakage power in static memory circuits are explored in this paper. The first technique is a 6T SRAM circuit with a dynamic voltage swing wordline driver. The wordline voltage is reduced in order to suppress the voltage disturbance on the storage nodes during a read operation. The data stability is enhanced by dynamically tuning the channel resistance of the bitline access transistors as opposed to the traditional approach based on increasing the sizes of the transistors in the cross-coupled inverters. The other three SRAM techniques evaluated in this paper modify the circuit structure of the memory cells to achieve enhanced reliability. With these 9T, the 8T, and the dual-Vt 7T SRAM circuits, the bitlines are decoupled from the data, thereby eliminating the voltage disturbance at the data storage nodes during a read operation. Data stability is therefore significantly enhanced without the need to increase the sizes of the transistors in the cross-coupled inverters. While all four techniques are effective to significantly enhance the cell static noise margin, the

highest data stability is provided by the 9T and the 8T SRAM circuits. Alternatively, the dual-Vt 7T SRAM circuit consumes the lowest leakage power and the memory cells with the dynamic voltage swing wordline driver have the smallest area.

BLBVGND

WL

BL VDD VGND

WL

VDD BLBVGND

WL

BL VDD VGND

WL

VDD (a) (b)

BLBVGND

WL

BL VDD VGND

WL

VDD (c)

VDD BLBVGND

WR

BL VDD VGND

WR

BL

R

VGND

BLB (d)

VDD WBLBVGND

W

WBL

R

VDD VGND

RBL

W

VGND

(e)

VDD

RBL

VGND

W

WBL

R

VDD VGND

VGND

(f)

Fig. 10. The layouts of the SRAM cells. (a) Standard 6T SRAM cell with � = 1. (b) Standard 6T SRAM cell with � = 2. (c) Standard 6T SRAM cell with � = 3. (d) 9T SRAM cell. (e) 8T SRAM cell. (f) 7T SRAM cell.

0.4

0.6

0.8

1

1.2

1.4

1.6

Nor

mal

ized

Are

a

6T (� = 1) 6T (� = 2) 6T (� = 3) Dynamic Wordline Voltage

9T 8T 7T

Smallest

Fig. 11. Normalized layout cell area comparison of the memory circuits.

REFERENCES [1] V. Kursun, S. A. Tawfik, and Z. Liu, “Leakage-Aware Design of Nanometer SoC,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3231-3234, May 2007. [2] G. Sery et al., “Life is CMOS: Why Chase Life After?,” Proceedings of the IEEE Design Automation Conference, pp. 78-83, June 2002. [3] Z. Liu and V. Kursun, “Characterization of a Novel Nine-Transistor SRAM Cell,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 4, pp. 488-492, April 2008. [4] L. Chang et al., “An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches,” IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, pp. 956-962, April 2008. [5] S. A. Tawfik and V. Kursun, “Dynamic Wordline Voltage Swing for Low Leakage and Stable Static Memory Banks,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1894-1897, May 2008. [6] S. A. Tawfik and V. Kursun, “Low Power and Robust 7T Dual-Vt SRAM Circuit,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1452-1455, May 2008.

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